From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Paulo Zanoni <przanoni@gmail.com>
Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: Re: [PATCH 8/9] drm/i915: MCH_SSKPD is a 64 bit register on Haswell
Date: Mon, 20 May 2013 16:38:20 +0300 [thread overview]
Message-ID: <20130520133820.GD14974@intel.com> (raw)
In-Reply-To: <1367612625-4823-9-git-send-email-przanoni@gmail.com>
On Fri, May 03, 2013 at 05:23:44PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> And the SNB_READ_WM0_LATENCY macro is not valid anymore because we
> have the "New WM0" at 63:56, so the "Old WM0" could maybe be zero if
> the new one is not zero.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 59bac2e..b56de92 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4491,7 +4491,7 @@ void intel_init_pm(struct drm_device *dev)
> }
> dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
> } else if (IS_HASWELL(dev)) {
> - if (SNB_READ_WM0_LATENCY()) {
> + if (I915_READ64(MCH_SSKPD)) {
> dev_priv->display.update_wm = haswell_update_wm;
> dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
> } else {
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
next prev parent reply other threads:[~2013-05-20 13:38 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-05-03 20:23 [PATCH 0/9] Haswell watermarks, round 1 Paulo Zanoni
2013-05-03 20:23 ` [PATCH 1/9] drm/i915: ILK, SNB and IVB don't have linetime watermarks Paulo Zanoni
2013-05-20 13:41 ` Ville Syrjälä
2013-05-03 20:23 ` [PATCH 2/9] drm/i915: fix linetime_watermarks code Paulo Zanoni
2013-05-05 7:19 ` Chris Wilson
2013-05-06 13:13 ` Paulo Zanoni
2013-05-06 13:43 ` Chris Wilson
2013-05-09 19:55 ` [PATCH 2/9] drm/i915: remove intel_update_linetime_watermarks Paulo Zanoni
2013-05-20 13:48 ` Ville Syrjälä
2013-05-03 20:23 ` [PATCH 3/9] drm/i915: use the mode->htotal to calculate linetime watermarks Paulo Zanoni
2013-05-20 13:42 ` Ville Syrjälä
2013-05-21 9:26 ` Daniel Vetter
2013-05-21 14:33 ` Paulo Zanoni
2013-05-21 14:59 ` Daniel Vetter
2013-05-03 20:23 ` [PATCH 4/9] drm/i915: fix haswell linetime watermarks calculation Paulo Zanoni
2013-05-20 13:53 ` Ville Syrjälä
2013-05-03 20:23 ` [PATCH 5/9] drm/i915: use the correct clock when calculating linetime watermarks Paulo Zanoni
2013-05-20 14:00 ` Ville Syrjälä
2013-05-21 9:35 ` Daniel Vetter
2013-05-03 20:23 ` [PATCH 6/9] drm/i915: make intel_ddi_get_cdclk_freq return values in KHz Paulo Zanoni
2013-05-05 7:20 ` Chris Wilson
2013-05-06 13:53 ` Paulo Zanoni
2013-05-20 14:11 ` Ville Syrjälä
2013-05-03 20:23 ` [PATCH 7/9] drm/i915: set the IPS linetime watermark Paulo Zanoni
2013-05-20 14:05 ` Ville Syrjälä
2013-05-03 20:23 ` [PATCH 8/9] drm/i915: MCH_SSKPD is a 64 bit register on Haswell Paulo Zanoni
2013-05-20 13:38 ` Ville Syrjälä [this message]
2013-05-03 20:23 ` [PATCH 9/9] drm/i915: set FORCE_ARB_IDLE_PLANES workaround Paulo Zanoni
2013-05-20 13:37 ` Ville Syrjälä
2013-05-21 10:01 ` Daniel Vetter
2013-05-21 13:27 ` Paulo Zanoni
2013-05-23 10:36 ` Ville Syrjälä
2013-05-23 10:51 ` Daniel Vetter
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