From: Daniel Vetter <daniel@ffwll.ch>
To: Stuart Abercrombie <sabercrombie@google.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] Lower threshold for pixel doubling.
Date: Wed, 29 May 2013 17:22:07 +0200 [thread overview]
Message-ID: <20130529152206.GL15743@phenom.ffwll.local> (raw)
In-Reply-To: <CAEzf47xddzOBuUF99Vz9Yn5pie3vQvSaWhV=P_nZnn8LeoyKSg@mail.gmail.com>
On Tue, May 28, 2013 at 10:39:07AM -0700, Stuart Abercrombie wrote:
> Any comments?
>
> Without this, plugging one of the older Chromebook models into a Dell U3011
> monitor produces a garbled display at the default 2048x1280 resolution.
>
> The original threshold was apparently fairly arbitrary:
>
> http://cgit.freedesktop.org/~anholt/xf86-video-intel/commit/?id=8fcf9a81179ee8577ddab5e904c58fbfd14cf59c
Do you see any pipe underruns without this patch? There are some not-yet
implemented tricks we should be pulling around re-splitting DSP_ARB fifo
entries, which tend to totally kill high-res modes.
-Daniel
> .
>
> Stuart
>
>
> On Mon, May 20, 2013 at 11:15 AM, Stuart Abercrombie <
> sabercrombie@chromium.org> wrote:
>
> > 90% of core speed (=180MHz dot clock) is too high for 2048x1280 to get
> > pixel doubling on Pineview, which it needs to avoid underruns, so
> > lower this to 85%.
> >
> > Signed-off-by: Stuart Abercrombie <sabercrombie@chromium.org>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index efe8299..9c924e9 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4564,14 +4564,14 @@ static void i9xx_set_pipeconf(struct intel_crtc
> > *intel_crtc)
> > pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
> >
> > if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
> > - /* Enable pixel doubling when the dot clock is > 90% of
> > the (display)
> > + /* Enable pixel doubling when the dot clock is > 85% of
> > the (display)
> > * core speed.
> > *
> > * XXX: No double-wide on 915GM pipe B. Is that the only
> > reason for the
> > * pipe == 0 check?
> > */
> > if (intel_crtc->config.requested_mode.clock >
> > - dev_priv->display.get_display_clock_speed(dev) * 9 /
> > 10)
> > + dev_priv->display.get_display_clock_speed(dev) * 17 /
> > 20)
> > pipeconf |= PIPECONF_DOUBLE_WIDE;
> > else
> > pipeconf &= ~PIPECONF_DOUBLE_WIDE;
> > --
> > 1.8.2.1
> >
> >
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
next prev parent reply other threads:[~2013-05-29 15:22 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-05-20 18:15 [PATCH] Lower threshold for pixel doubling Stuart Abercrombie
2013-05-28 17:39 ` Stuart Abercrombie
2013-05-29 15:22 ` Daniel Vetter [this message]
2013-05-29 16:22 ` Stuart Abercrombie
2013-06-21 22:52 ` Stuart Abercrombie
2013-06-24 6:59 ` Daniel Vetter
2013-06-24 23:28 ` Stuart Abercrombie
2013-07-08 18:52 ` Stuart Abercrombie
2013-07-13 0:29 ` Stuart Abercrombie
2013-07-26 6:01 ` Daniel Vetter
2013-07-26 6:19 ` Stéphane Marchesin
2013-08-16 8:20 ` Chris Wilson
2013-08-16 12:15 ` Daniel Vetter
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