* [PATCH i-g-t 1/3] quick_dump: Add automagic DPIO register support
@ 2013-06-26 17:57 ville.syrjala
2013-06-26 17:57 ` [PATCH i-g-t 2/3] quick_dump: Document the register definition format ville.syrjala
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: ville.syrjala @ 2013-06-26 17:57 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Repurpose the (currently unused) third element in the register
definition tuple to indicate the type of the register. 'DPIO'
is the only special register type for now.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
tools/quick_dump/quick_dump.py | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/tools/quick_dump/quick_dump.py b/tools/quick_dump/quick_dump.py
index 6111b5d..390cafa 100755
--- a/tools/quick_dump/quick_dump.py
+++ b/tools/quick_dump/quick_dump.py
@@ -13,7 +13,10 @@ def parse_file(file):
print('-' * 54)
for line in file:
register = ast.literal_eval(line)
- val = reg.read(register[1])
+ if register[2] == 'DPIO':
+ val = reg.dpio_read(register[1])
+ else:
+ val = reg.read(register[1])
intreg = int(register[1], 16)
print('{0:#010x} | {1:<28} | {2:#010x}'.format(intreg, register[0], val))
print('')
--
1.8.1.5
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH i-g-t 2/3] quick_dump: Document the register definition format
2013-06-26 17:57 [PATCH i-g-t 1/3] quick_dump: Add automagic DPIO register support ville.syrjala
@ 2013-06-26 17:57 ` ville.syrjala
2013-06-26 17:57 ` [PATCH i-g-t v2 3/3] quick_dump: Add VLV DPIO registers ville.syrjala
2013-07-01 5:09 ` [PATCH i-g-t 1/3] quick_dump: Add automagic DPIO register support Ben Widawsky
2 siblings, 0 replies; 5+ messages in thread
From: ville.syrjala @ 2013-06-26 17:57 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add a small comment about what the elements in the register
tuple mean.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
tools/quick_dump/quick_dump.py | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/tools/quick_dump/quick_dump.py b/tools/quick_dump/quick_dump.py
index 390cafa..8fdd169 100755
--- a/tools/quick_dump/quick_dump.py
+++ b/tools/quick_dump/quick_dump.py
@@ -1,5 +1,12 @@
#!/usr/bin/env python3
+# register definition format:
+# ('register name', 'register offset', 'register type')
+#
+# register types:
+# '' - normal register
+# 'DPIO' - DPIO register
+
import argparse
import os
import sys
--
1.8.1.5
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH i-g-t v2 3/3] quick_dump: Add VLV DPIO registers
2013-06-26 17:57 [PATCH i-g-t 1/3] quick_dump: Add automagic DPIO register support ville.syrjala
2013-06-26 17:57 ` [PATCH i-g-t 2/3] quick_dump: Document the register definition format ville.syrjala
@ 2013-06-26 17:57 ` ville.syrjala
2013-06-26 18:48 ` Ben Widawsky
2013-07-01 5:09 ` [PATCH i-g-t 1/3] quick_dump: Add automagic DPIO register support Ben Widawsky
2 siblings, 1 reply; 5+ messages in thread
From: ville.syrjala @ 2013-06-26 17:57 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add the names of all VLV DPIO registers.
v2: Use the third element to signal DPIO registers, and split
the code changes to a separate patch
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
tools/quick_dump/Makefile.am | 2 +-
tools/quick_dump/valleyview | 1 +
tools/quick_dump/vlv_dpio.txt | 53 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 55 insertions(+), 1 deletion(-)
create mode 100644 tools/quick_dump/vlv_dpio.txt
diff --git a/tools/quick_dump/Makefile.am b/tools/quick_dump/Makefile.am
index afd6814..cc19987 100644
--- a/tools/quick_dump/Makefile.am
+++ b/tools/quick_dump/Makefile.am
@@ -25,7 +25,7 @@ EXTRA_DIST = \
base_display.txt base_interrupt.txt base_other.txt base_power.txt base_rings.txt \
gen6_other.txt sandybridge \
gen7_other.txt ivybridge \
- vlv_display.txt valleyview \
+ vlv_display.txt vlv_dpio.txt valleyview \
quick_dump.py \
reg_access.py \
chipset.i chipset.py
diff --git a/tools/quick_dump/valleyview b/tools/quick_dump/valleyview
index 4d7dee1..6b6e16c 100644
--- a/tools/quick_dump/valleyview
+++ b/tools/quick_dump/valleyview
@@ -5,3 +5,4 @@ base_other.txt
base_power.txt
base_rings.txt
gen7_other.txt
+vlv_dpio.txt
diff --git a/tools/quick_dump/vlv_dpio.txt b/tools/quick_dump/vlv_dpio.txt
new file mode 100644
index 0000000..8359149
--- /dev/null
+++ b/tools/quick_dump/vlv_dpio.txt
@@ -0,0 +1,53 @@
+('DPIO_TX3_SWING_CTL4_A', '0x690', 'DPIO')
+('DPIO_TX3_SWING_CTL4_B', '0x2a90', 'DPIO')
+('DPIO_DIV_A', '0x800c', 'DPIO')
+('DPIO_DIV_B', '0x802c', 'DPIO')
+('DPIO_REFSFR_A', '0x8014', 'DPIO')
+('DPIO_REFSFR_B', '0x8034', 'DPIO')
+('DPIO_CORE_CLK_A', '0x801c', 'DPIO')
+('DPIO_CORE_CLK_B', '0x803c', 'DPIO')
+('DPIO_IREF_CTL_A', '0x8040', 'DPIO')
+('DPIO_IREF_CTL_B', '0x8060', 'DPIO')
+('DPIO_IREF_BCAST', '0xc044', 'DPIO')
+('DPIO_IREF_A', '0x8044', 'DPIO')
+('DPIO_IREF_B', '0x8064', 'DPIO')
+('DPIO_PLL_CML_A', '0x804c', 'DPIO')
+('DPIO_PLL_CML_B', '0x806c', 'DPIO')
+('DPIO_LPF_COEFF_A', '0x8048', 'DPIO')
+('DPIO_LPF_COEFF_B', '0x8068', 'DPIO')
+('DPIO_CALIBRATION', '0x80ac', 'DPIO')
+('DPIO_FASTCLK_DISABLE', '0x8100', 'DPIO')
+('DPIO_PCS_TX_0', '0x8200', 'DPIO')
+('DPIO_PCS_TX_1', '0x8400', 'DPIO')
+('DPIO_PCS_CLK_0', '0x8204', 'DPIO')
+('DPIO_PCS_CLK_1', '0x8404', 'DPIO')
+('DPIO_PCS_CTL_OVR1_A', '0x8224', 'DPIO')
+('DPIO_PCS_CTL_OVR1_B', '0x8424', 'DPIO')
+('DPIO_PCS_STAGGER0_A', '0x822c', 'DPIO')
+('DPIO_PCS_STAGGER0_B', '0x842c', 'DPIO')
+('DPIO_PCS_STAGGER1_A', '0x8230', 'DPIO')
+('DPIO_PCS_STAGGER1_B', '0x8430', 'DPIO')
+('DPIO_PCS_CLOCKBUF0_A', '0x8238', 'DPIO')
+('DPIO_PCS_CLOCKBUF0_B', '0x8438', 'DPIO')
+('DPIO_PCS_CLOCKBUF8_A', '0x825c', 'DPIO')
+('DPIO_PCS_CLOCKBUF8_B', '0x845c', 'DPIO')
+('DPIO_TX_SWING_CTL2_A', '0x8288', 'DPIO')
+('DPIO_TX_SWING_CTL2_B', '0x8488', 'DPIO')
+('DPIO_TX_SWING_CTL3_A', '0x828c', 'DPIO')
+('DPIO_TX_SWING_CTL3_B', '0x848c', 'DPIO')
+('DPIO_TX_SWING_CTL4_A', '0x8290', 'DPIO')
+('DPIO_TX_SWING_CTL4_B', '0x8490', 'DPIO')
+('DPIO_TX_OCALINIT_0', '0x8294', 'DPIO')
+('DPIO_TX_OCALINIT_1', '0x8494', 'DPIO')
+('DPIO_TX_CTL_0', '0x82ac', 'DPIO')
+('DPIO_TX_CTL_1', '0x84ac', 'DPIO')
+('DPIO_TX_LANE_0', '0x82b8', 'DPIO')
+('DPIO_TX_LANE_1', '0x84b8', 'DPIO')
+('DPIO_DATA_CHANNEL1', '0x8220', 'DPIO')
+('DPIO_DATA_CHANNEL2', '0x8420', 'DPIO')
+('DPIO_PORT0_PCS0', '0x0220', 'DPIO')
+('DPIO_PORT0_PCS1', '0x0420', 'DPIO')
+('DPIO_PORT1_PCS2', '0x2620', 'DPIO')
+('DPIO_PORT1_PCS3', '0x2820', 'DPIO')
+('DPIO_DATA_CHANNEL1', '0x8220', 'DPIO')
+('DPIO_DATA_CHANNEL2', '0x8420', 'DPIO')
--
1.8.1.5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH i-g-t v2 3/3] quick_dump: Add VLV DPIO registers
2013-06-26 17:57 ` [PATCH i-g-t v2 3/3] quick_dump: Add VLV DPIO registers ville.syrjala
@ 2013-06-26 18:48 ` Ben Widawsky
0 siblings, 0 replies; 5+ messages in thread
From: Ben Widawsky @ 2013-06-26 18:48 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Wed, Jun 26, 2013 at 08:57:34PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add the names of all VLV DPIO registers.
>
> v2: Use the third element to signal DPIO registers, and split
> the code changes to a separate patch
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
Series is:
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
--
Ben Widawsky, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH i-g-t 1/3] quick_dump: Add automagic DPIO register support
2013-06-26 17:57 [PATCH i-g-t 1/3] quick_dump: Add automagic DPIO register support ville.syrjala
2013-06-26 17:57 ` [PATCH i-g-t 2/3] quick_dump: Document the register definition format ville.syrjala
2013-06-26 17:57 ` [PATCH i-g-t v2 3/3] quick_dump: Add VLV DPIO registers ville.syrjala
@ 2013-07-01 5:09 ` Ben Widawsky
2 siblings, 0 replies; 5+ messages in thread
From: Ben Widawsky @ 2013-07-01 5:09 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Wed, Jun 26, 2013 at 08:57:32PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Repurpose the (currently unused) third element in the register
> definition tuple to indicate the type of the register. 'DPIO'
> is the only special register type for now.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> tools/quick_dump/quick_dump.py | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/tools/quick_dump/quick_dump.py b/tools/quick_dump/quick_dump.py
> index 6111b5d..390cafa 100755
> --- a/tools/quick_dump/quick_dump.py
> +++ b/tools/quick_dump/quick_dump.py
> @@ -13,7 +13,10 @@ def parse_file(file):
> print('-' * 54)
> for line in file:
> register = ast.literal_eval(line)
> - val = reg.read(register[1])
> + if register[2] == 'DPIO':
> + val = reg.dpio_read(register[1])
> + else:
> + val = reg.read(register[1])
> intreg = int(register[1], 16)
> print('{0:#010x} | {1:<28} | {2:#010x}'.format(intreg, register[0], val))
> print('')
I can't recall if you have push access, but I've pushed it.
--
Ben Widawsky, Intel Open Source Technology Center
_______________________________________________
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
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2013-06-26 17:57 [PATCH i-g-t 1/3] quick_dump: Add automagic DPIO register support ville.syrjala
2013-06-26 17:57 ` [PATCH i-g-t 2/3] quick_dump: Document the register definition format ville.syrjala
2013-06-26 17:57 ` [PATCH i-g-t v2 3/3] quick_dump: Add VLV DPIO registers ville.syrjala
2013-06-26 18:48 ` Ben Widawsky
2013-07-01 5:09 ` [PATCH i-g-t 1/3] quick_dump: Add automagic DPIO register support Ben Widawsky
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