Updated drm-intel-testing tree

Updated drm-intel-testing tree

[Daniel Vetter]

Hi all,

So new testing cycle! Due to rebasing stuff around it's there's almost
some patches from the previous cycle in the git log. But recollecting from
memory we have here:
- First slice of real ppgtt prep stuff from Ben.
- error state in sysfs and independent of CONFIG_DEBUG_FS (Mika)
- interrupt handling code improvements
- and an assorted pile of smaller stuff

In other words: Not much, people are on vacation ;-)

Happy testing!

Cheers, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Updated drm-intel-testing tree

[Daniel Vetter]

Hi all,

New feature tree pushed, hightlights:
- proper eLLC support for HSW from Ben
- more interrupt refactoring
- add w/a tags where we implement them already (Damien)
- hangcheck fixes (Chris) + hangcheck stats (Mika)
- flesh out the new vm structs for ppgtt and ggtt (Ben)
- PSR for Haswell, still disabled by default (Rodrigo et al.)
- pc8+ refclock sequence code from Paulo
- more interrupt refactoring from Paulo, unifying ilk/snb with the ivb/hsw
  interrupt code
- full solution for the Haswell concurrent reg access issues (Chris)
- fix racy object accounting, used by some new leak tests
- fix sync polarity settings on ch7xxx dvo encoder
- random bits&pieces, little fixes and better debug output all over

Happy testing!

Cheers, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch