From: Daniel Vetter <daniel@ffwll.ch>
To: Paulo Zanoni <przanoni@gmail.com>
Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: Re: [PATCH 1/2] drm/i915: check the power well when redisabling VGA
Date: Wed, 14 Aug 2013 16:51:06 +0200 [thread overview]
Message-ID: <20130814145106.GW9296@phenom.ffwll.local> (raw)
In-Reply-To: <20130805154612.GL22035@phenom.ffwll.local>
On Mon, Aug 05, 2013 at 05:46:12PM +0200, Daniel Vetter wrote:
> On Fri, Aug 02, 2013 at 04:22:24PM -0300, Paulo Zanoni wrote:
> > From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >
> > If the power well is disabled VGA is guaranteed to be disabled.
> >
> > This fixes unclaimed register messages that happen on suspend/resume.
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67517
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Have you seen my other comment asking whether we could just force-enable
> the power well a bit earlier in the resume sequence instead? Imo that
> feels a notch more robust, since we didn't sprinkle tons of power well
> checks in all the other hw readout paths either.
Ok, I've merged this one here (plus comments and the follow-up patch)
instead of the other one.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
prev parent reply other threads:[~2013-08-14 14:50 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-08-02 19:22 [PATCH 1/2] drm/i915: check the power well when redisabling VGA Paulo Zanoni
2013-08-02 19:22 ` [PATCH 2/2] drm/i915: clarify Haswell power well bit names Paulo Zanoni
2013-08-05 15:46 ` [PATCH 1/2] drm/i915: check the power well when redisabling VGA Daniel Vetter
2013-08-14 14:51 ` Daniel Vetter [this message]
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