[PATCH 0/9] drm-intel-collector - update

[PATCH 0/9] drm-intel-collector - update

[Rodrigo Vivi]

This is another drm-intel-collector updated notice:
http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=drm-intel-collector

Here goes the update list in order for better reviewers assignment:

Patch     drm/i915: Asynchronously perform the set-base for a simple modeset - Reviewed by me.
Patch     drm/i915: Fix gen3/4 vblank counter wraparound - Reviewer:
Patch     drm/i915: Use frame counter for intel_wait_for_vblank() on CTG - Reviewer:
Patch     drm/i915: Do hw quiescing first during unload - Reviewer:
Patch     drm/i915: print object bindings in debugfs - Reviewer:
Patch     drm/i915/vlv: enable HDMI audio for Valleyview2 - Reviewer:
Patch     drm/i915: Hold pc8 lock around toggling pc8.gpu_idle - Reviewed by Paulo
Patch     drm/i915: Do not enable package C8 on unsupported hardware - Reviewed by Paulo
Patch     drm/i915: Enable pipe gamma for sprites - Reviewer:

Overall Process:

drm-intel-collector - review request
 1. Daniel pushs drm-intel-testing (every 2 weeks)
 2. I rebase drm-intel-collector onto drm-intel-testing
 3. Add Reviewer: tag with voluntered reviewers. If you don't believe you should be assigned on a particular patch please don't get mad just tell you wont review or volunteer someone else.
 4. I resubmit remaining patches for review without picking any new (drm-intel-collector - review request)

drm-intel-collector - updated
 5. One week later I collect all simple (1-2) patches that wasn't yet reviewed and not queued by Daniel from one testing update until another.
 6. Request automated QA's PRTS automated i-g-t tests comparing drm-intel-testing x drm-intel-collector
 7. If tests are ok I send the update notification or the patches as a series to intel-gfx mailing list for better tracking and to be reviewed. (drm-intel-collector - updated)
 8. Let me know volunteers for review new patches and also let me know if I've picked any patch that I shouldn't.

There are some reasons that some patches can be left behind:
1. Your patch didn't applied cleanly and I couldn't easily solve the conflicts.
2. Kernel didn't compiled with your patch.
3. I simply missed it. If you believe this is the case please warn me.

Please help me to get these patches reviewed and queued by Daniel.

Also, please let me know if you have further ideas how to improve this process.

Thanks in advance,
Rodrigo.


Chris Wilson (4):
  drm/i915: Asynchronously perform the set-base for a simple modeset
  drm/i915: Do hw quiescing first during unload
  drm/i915: Hold pc8 lock around toggling pc8.gpu_idle
  drm/i915: Do not enable package C8 on unsupported hardware

Daniel Vetter (1):
  drm/i915: print object bindings in debugfs

Mengdong Lin (1):
  drm/i915/vlv: enable HDMI audio for Valleyview2

Ville Syrjälä (3):
  drm/i915: Fix gen3/4 vblank counter wraparound
  drm/i915: Use frame counter for intel_wait_for_vblank() on CTG
  drm/i915: Enable pipe gamma for sprites

 drivers/gpu/drm/i915/i915_debugfs.c  |  6 ++++
 drivers/gpu/drm/i915/i915_dma.c      | 10 +++---
 drivers/gpu/drm/i915/i915_drv.h      |  1 +
 drivers/gpu/drm/i915/i915_irq.c      |  2 +-
 drivers/gpu/drm/i915/i915_reg.h      | 20 ++++++++++-
 drivers/gpu/drm/i915/intel_display.c | 65 ++++++++++++++++++++++++++++--------
 drivers/gpu/drm/i915/intel_sprite.c  | 18 ++++++++++
 7 files changed, 103 insertions(+), 19 deletions(-)

-- 
1.8.3.1

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[PATCH 1/9] drm/i915: Asynchronously perform the set-base for a simple modeset

[Rodrigo Vivi]

From: Chris Wilson <chris@chris-wilson.co.uk>

A simple modeset, where we only wish to switch over to a new framebuffer
such as the transition from fbcon to X, takes around 30-60ms. This is
due to three factors:

1. We need to make sure the fb->obj is in the display domain, which
incurs a cache flush to ensure no dirt is left on the scanout.

2. We need to flush any pending rendering before performing the mmio
so that the frame is complete before it is shown.

3. We currently wait for the vblank after the mmio to be sure that the
old fb is no longer being shown before releasing it.

(1) can only be eliminated by userspace preparing the fb->obj in advance
to already be in the display domain. This can be done through use of the
create2 ioctl, or by reusing an existing fb->obj.

However, (2) and (3) are already solved by the existing page flip
mechanism, and it is surprisingly trivial to wire them up for use in the
set-base fast path. Though it can be argued that this represents a
subtle ABI break in that the set_config ioctl now returns before the old
framebuffer is unpinned. The danger is that userspace will start to
modify it before it is no longer being shown, however we should be able
to prevent that through proper domain tracking.

By combining all of the above, we can achieve an instaneous set_config:

[     6.601] (II) intel(0): switch to mode 2560x1440@60.0 on pipe 0 using DP2, position (0, 0), rotation normal
[     6.601] (II) intel(0): Setting screen physical size to 677 x 381

v2 (by Vivi): page_flip_flag was added to intel_crtc_page_flip
              in a previous commit. using 0.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
---
 drivers/gpu/drm/i915/intel_display.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f34252d..64390f3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9687,10 +9687,13 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
 		ret = intel_set_mode(set->crtc, set->mode,
 				     set->x, set->y, set->fb);
 	} else if (config->fb_changed) {
-		intel_crtc_wait_for_pending_flips(set->crtc);
-
-		ret = intel_pipe_set_base(set->crtc,
-					  set->x, set->y, set->fb);
+		if (to_intel_framebuffer(set->fb)->obj->ring == NULL ||
+		    save_set.x != set->x || save_set.y != set->y ||
+		    intel_crtc_page_flip(set->crtc, set->fb, NULL, 0)) {
+			intel_crtc_wait_for_pending_flips(set->crtc);
+			ret = intel_pipe_set_base(set->crtc,
+						  set->x, set->y, set->fb);
+		}
 	}
 
 	if (ret) {
-- 
1.8.3.1

[PATCH 2/9] drm/i915: Fix gen3/4 vblank counter wraparound

[Rodrigo Vivi]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

When the hardware frame counter reads 0xffffff and we're already past
vblank start, we'd return 0x1000000 as the vblank counter value. Once
we'd cross into the next frame's active portion, the vblank counter
would wrap to 0. So we're reporting two different vblank counter values
for the same frame.

Fix the problem by masking the cooked value by 0xffffff to make sure
the counter wraps already after vblank start.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2a44816..c474dac 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -583,7 +583,7 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 	 * Cook up a vblank counter by also checking the pixel
 	 * counter against vblank start.
 	 */
-	return ((high1 << 8) | low) + (pixel >= vbl_start);
+	return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 }
 
 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
-- 
1.8.3.1

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[PATCH 3/9] drm/i915: Use frame counter for intel_wait_for_vblank() on CTG

[Rodrigo Vivi]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use the same wait_for_vblank code for CTG that we use for ILK+.

Also fix the name of the frame counter register while at it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
---
 drivers/gpu/drm/i915/intel_display.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 64390f3..7595d5a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -748,10 +748,10 @@ enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 	return intel_crtc->config.cpu_transcoder;
 }
 
-static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
+static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	u32 frame, frame_reg = PIPEFRAME(pipe);
+	u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
 
 	frame = I915_READ(frame_reg);
 
@@ -772,8 +772,8 @@ void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int pipestat_reg = PIPESTAT(pipe);
 
-	if (INTEL_INFO(dev)->gen >= 5) {
-		ironlake_wait_for_vblank(dev, pipe);
+	if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
+		g4x_wait_for_vblank(dev, pipe);
 		return;
 	}
 
-- 
1.8.3.1

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[PATCH 4/9] drm/i915: Do hw quiescing first during unload

[Rodrigo Vivi]

From: Chris Wilson <chris@chris-wilson.co.uk>

If we force the hw to idle as our first step during unload, we can abort
the unload upon failure. Later we can probe whether the hardware remain
active even after we try to shut it down.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_dma.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 0cab2d0..479abc0 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1704,6 +1704,12 @@ int i915_driver_unload(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	int ret;
 
+	ret = i915_gem_suspend(dev);
+	if (ret) {
+		DRM_ERROR("failed to idle hardware: %d\n", ret);
+		return ret;
+	}
+
 	intel_gpu_ips_teardown();
 
 	if (HAS_POWER_WELL(dev)) {
@@ -1719,10 +1725,6 @@ int i915_driver_unload(struct drm_device *dev)
 	if (dev_priv->mm.inactive_shrinker.scan_objects)
 		unregister_shrinker(&dev_priv->mm.inactive_shrinker);
 
-	ret = i915_gem_suspend(dev);
-	if (ret)
-		DRM_ERROR("failed to idle hardware: %d\n", ret);
-
 	io_mapping_free(dev_priv->gtt.mappable);
 	arch_phys_wc_del(dev_priv->gtt.mtrr);
 
-- 
1.8.3.1

[PATCH 5/9] drm/i915: print object bindings in debugfs

[Rodrigo Vivi]

From: Daniel Vetter <daniel.vetter@ffwll.ch>

This is useful when we only have aliasing ppgtt and want to figure out
what exactly is accesssible and what not. Paulo can somehow overwrite
the fbcon framebuffer with the blitter on his hsw machine ...

v2: Actually make it compile.

Cc: Paulo Zanoni <przanoni@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 7008aac..3426118 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -124,7 +124,9 @@ static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
 static void
 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 {
+	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
 	struct i915_vma *vma;
+
 	seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
 		   &obj->base,
 		   get_pin_flag(obj),
@@ -155,6 +157,10 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 		seq_printf(m, "gtt offset: %08lx, size: %08lx)",
 			   vma->node.start, vma->node.size);
 	}
+	if (dev_priv->mm.aliasing_ppgtt)
+		seq_printf(m, " (bindings: %s%s)",
+			   obj->has_global_gtt_mapping ? "g" : "",
+			   obj->has_aliasing_ppgtt_mapping ? "pp" : "");
 	if (obj->stolen)
 		seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
 	if (obj->pin_mappable || obj->fault_mappable) {
-- 
1.8.3.1

[PATCH 6/9] drm/i915/vlv: enable HDMI audio for Valleyview2

[Rodrigo Vivi]

From: Mengdong Lin <mengdong.lin@intel.com>

This patch defines audio configuration registers and adds audio enabling code
for Valleyview2.

Signed-off-by: Mengdong Lin <mengdong.lin@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
---
 drivers/gpu/drm/i915/i915_reg.h      | 18 ++++++++++++++++++
 drivers/gpu/drm/i915/intel_display.c | 23 ++++++++++++++++++++---
 2 files changed, 38 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3f303ba..8f4916d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4948,6 +4948,18 @@
 					CPT_AUD_CNTL_ST_B)
 #define CPT_AUD_CNTRL_ST2		0xE50C0
 
+#define VLV_HDMIW_HDMIEDID_A		(VLV_DISPLAY_BASE + 0x62050)
+#define VLV_HDMIW_HDMIEDID_B		(VLV_DISPLAY_BASE + 0x62150)
+#define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
+					VLV_HDMIW_HDMIEDID_A, \
+					VLV_HDMIW_HDMIEDID_B)
+#define VLV_AUD_CNTL_ST_A		(VLV_DISPLAY_BASE + 0x620B4)
+#define VLV_AUD_CNTL_ST_B		(VLV_DISPLAY_BASE + 0x621B4)
+#define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \
+					VLV_AUD_CNTL_ST_A, \
+					VLV_AUD_CNTL_ST_B)
+#define VLV_AUD_CNTL_ST2		(VLV_DISPLAY_BASE + 0x620C0)
+
 /* These are the 4 32-bit write offset registers for each stream
  * output buffer.  It determines the offset from the
  * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
@@ -4964,6 +4976,12 @@
 #define CPT_AUD_CFG(pipe) _PIPE(pipe, \
 					CPT_AUD_CONFIG_A, \
 					CPT_AUD_CONFIG_B)
+#define VLV_AUD_CONFIG_A			0x62000
+#define VLV_AUD_CONFIG_B			0x62100
+#define VLV_AUD_CFG(pipe) _PIPE(pipe, \
+					VLV_AUD_CONFIG_A, \
+					VLV_AUD_CONFIG_B)
+
 #define   AUD_CONFIG_N_VALUE_INDEX		(1 << 29)
 #define   AUD_CONFIG_N_PROG_ENABLE		(1 << 28)
 #define   AUD_CONFIG_UPPER_N_SHIFT		20
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7595d5a..be810c5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6989,6 +6989,11 @@ static void ironlake_write_eld(struct drm_connector *connector,
 		aud_config = IBX_AUD_CFG(pipe);
 		aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
 		aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
+	} else if (IS_VALLEYVIEW(connector->dev)) {
+		hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
+		aud_config = VLV_AUD_CFG(pipe);
+		aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
+		aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
 	} else {
 		hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
 		aud_config = CPT_AUD_CFG(pipe);
@@ -6998,8 +7003,19 @@ static void ironlake_write_eld(struct drm_connector *connector,
 
 	DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
 
-	i = I915_READ(aud_cntl_st);
-	i = (i >> 29) & DIP_PORT_SEL_MASK;		/* DIP_Port_Select, 0x1 = PortB */
+	if (IS_VALLEYVIEW(connector->dev))  {
+		struct intel_encoder *intel_encoder;
+		int port = 0;
+		intel_encoder = intel_attached_encoder(connector);
+		if (intel_encoder)
+			port = intel_ddi_get_encoder_port(intel_encoder);
+		i = port;
+	} else {
+		i = I915_READ(aud_cntl_st);
+		i = (i >> 29) & DIP_PORT_SEL_MASK;
+		/* DIP_Port_Select, 0x1 = PortB */
+	}
+
 	if (!i) {
 		DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
 		/* operate blindly on all ports */
@@ -10320,7 +10336,8 @@ static void intel_init_display(struct drm_device *dev)
 		}
 	} else if (IS_G4X(dev)) {
 		dev_priv->display.write_eld = g4x_write_eld;
-	}
+	} else if (IS_VALLEYVIEW(dev))
+		dev_priv->display.write_eld = ironlake_write_eld;
 
 	/* Default just returns -ENODEV to indicate unsupported */
 	dev_priv->display.queue_flip = intel_default_queue_flip;
-- 
1.8.3.1

[PATCH 7/9] drm/i915: Hold pc8 lock around toggling pc8.gpu_idle

[Rodrigo Vivi]

From: Chris Wilson <chris@chris-wilson.co.uk>

We need to hold the pc8 lock around toggling the value of gpu_idle.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
---
 drivers/gpu/drm/i915/intel_display.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index be810c5..cfcad82 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6540,18 +6540,22 @@ done:
 
 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
 {
+	mutex_lock(&dev_priv->pc8.lock);
 	if (!dev_priv->pc8.gpu_idle) {
 		dev_priv->pc8.gpu_idle = true;
-		hsw_enable_package_c8(dev_priv);
+		__hsw_enable_package_c8(dev_priv);
 	}
+	mutex_unlock(&dev_priv->pc8.lock);
 }
 
 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
 {
+	mutex_lock(&dev_priv->pc8.lock);
 	if (dev_priv->pc8.gpu_idle) {
 		dev_priv->pc8.gpu_idle = false;
-		hsw_disable_package_c8(dev_priv);
+		__hsw_disable_package_c8(dev_priv);
 	}
+	mutex_unlock(&dev_priv->pc8.lock);
 }
 
 #define for_each_power_domain(domain, mask)				\
-- 
1.8.3.1

[PATCH 8/9] drm/i915: Do not enable package C8 on unsupported hardware

[Rodrigo Vivi]

From: Chris Wilson <chris@chris-wilson.co.uk>

If the hardware does not support package C8, then do not even schedule
work to enable it. Thereby we can eliminate a bunch of dangerous work.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  1 +
 drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++++++
 2 files changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b12d942..bb6a302 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1791,6 +1791,7 @@ struct drm_i915_file_private {
 #define HAS_POWER_WELL(dev)	(IS_HASWELL(dev))
 #define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
 #define HAS_PSR(dev)		(IS_HASWELL(dev))
+#define HAS_PC8(dev)		(IS_HASWELL(dev)) /* XXX HSW:ULX */
 
 #define INTEL_PCH_DEVICE_ID_MASK		0xff00
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index cfcad82..b39d0df 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6473,6 +6473,9 @@ static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
 
 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
 {
+	if (!HAS_PC8(dev_priv->dev))
+		return;
+
 	mutex_lock(&dev_priv->pc8.lock);
 	__hsw_enable_package_c8(dev_priv);
 	mutex_unlock(&dev_priv->pc8.lock);
@@ -6480,6 +6483,9 @@ void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
 
 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
 {
+	if (!HAS_PC8(dev_priv->dev))
+		return;
+
 	mutex_lock(&dev_priv->pc8.lock);
 	__hsw_disable_package_c8(dev_priv);
 	mutex_unlock(&dev_priv->pc8.lock);
@@ -6517,6 +6523,9 @@ static void hsw_update_package_c8(struct drm_device *dev)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	bool allow;
 
+	if (!HAS_PC8(dev_priv->dev))
+		return;
+
 	if (!i915_enable_pc8)
 		return;
 
@@ -6540,6 +6549,9 @@ done:
 
 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
 {
+	if (!HAS_PC8(dev_priv->dev))
+		return;
+
 	mutex_lock(&dev_priv->pc8.lock);
 	if (!dev_priv->pc8.gpu_idle) {
 		dev_priv->pc8.gpu_idle = true;
@@ -6550,6 +6562,9 @@ static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
 
 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
 {
+	if (!HAS_PC8(dev_priv->dev))
+		return;
+
 	mutex_lock(&dev_priv->pc8.lock);
 	if (dev_priv->pc8.gpu_idle) {
 		dev_priv->pc8.gpu_idle = false;
-- 
1.8.3.1

[PATCH 9/9] drm/i915: Enable pipe gamma for sprites

[Rodrigo Vivi]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We send the primary and cursor plane data through the gamma unit.
In order to get matching output from sprites, also send the sprite
data through the gamma unit.

In the future we should add some properties to control this
explicitly, and also add properties for the per-sprite gamma ramps
what have you, but for now this seems like a reasonable thing to do.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
---
 drivers/gpu/drm/i915/i915_reg.h     |  2 +-
 drivers/gpu/drm/i915/intel_sprite.c | 18 ++++++++++++++++++
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8f4916d..7b454d2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3745,7 +3745,7 @@
 
 #define _SPACNTR		(VLV_DISPLAY_BASE + 0x72180)
 #define   SP_ENABLE			(1<<31)
-#define   SP_GEAMMA_ENABLE		(1<<30)
+#define   SP_GAMMA_ENABLE		(1<<30)
 #define   SP_PIXFORMAT_MASK		(0xf<<26)
 #define   SP_FORMAT_YUV422		(0<<26)
 #define   SP_FORMAT_BGR565		(5<<26)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 8afaad6..cb7ffd3 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -104,6 +104,12 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
 		break;
 	}
 
+	/*
+	 * Enable gamma to match primary/cursor plane behaviour.
+	 * FIXME should be user controllable via propertiesa.
+	 */
+	sprctl |= SP_GAMMA_ENABLE;
+
 	if (obj->tiling_mode != I915_TILING_NONE)
 		sprctl |= SP_TILED;
 
@@ -257,6 +263,12 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 		BUG();
 	}
 
+	/*
+	 * Enable gamma to match primary/cursor plane behaviour.
+	 * FIXME should be user controllable via propertiesa.
+	 */
+	sprctl |= SPRITE_GAMMA_ENABLE;
+
 	if (obj->tiling_mode != I915_TILING_NONE)
 		sprctl |= SPRITE_TILED;
 
@@ -453,6 +465,12 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 		BUG();
 	}
 
+	/*
+	 * Enable gamma to match primary/cursor plane behaviour.
+	 * FIXME should be user controllable via propertiesa.
+	 */
+	dvscntr |= DVS_GAMMA_ENABLE;
+
 	if (obj->tiling_mode != I915_TILING_NONE)
 		dvscntr |= DVS_TILED;
 
-- 
1.8.3.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 0/9] drm-intel-collector - update

[Rodrigo Vivi]

Hi Daniel,

could you help me to assign best reviewers for these patches?
also, please let me know if I should just remove patch 1 out from -collector.

Thanks in advance,
Rodrigo.

On Mon, Nov 18, 2013 at 6:32 PM, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
>
> This is another drm-intel-collector updated notice:
> http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=drm-intel-collector
>
> Here goes the update list in order for better reviewers assignment:
>
> Patch     drm/i915: Asynchronously perform the set-base for a simple modeset - Reviewed by me.
> Patch     drm/i915: Fix gen3/4 vblank counter wraparound - Reviewer:
> Patch     drm/i915: Use frame counter for intel_wait_for_vblank() on CTG - Reviewer:
> Patch     drm/i915: Do hw quiescing first during unload - Reviewer:
> Patch     drm/i915: print object bindings in debugfs - Reviewer:
> Patch     drm/i915/vlv: enable HDMI audio for Valleyview2 - Reviewer:
> Patch     drm/i915: Hold pc8 lock around toggling pc8.gpu_idle - Reviewed by Paulo
> Patch     drm/i915: Do not enable package C8 on unsupported hardware - Reviewed by Paulo
> Patch     drm/i915: Enable pipe gamma for sprites - Reviewer:
>
> Overall Process:
>
> drm-intel-collector - review request
>  1. Daniel pushs drm-intel-testing (every 2 weeks)
>  2. I rebase drm-intel-collector onto drm-intel-testing
>  3. Add Reviewer: tag with voluntered reviewers. If you don't believe you should be assigned on a particular patch please don't get mad just tell you wont review or volunteer someone else.
>  4. I resubmit remaining patches for review without picking any new (drm-intel-collector - review request)
>
> drm-intel-collector - updated
>  5. One week later I collect all simple (1-2) patches that wasn't yet reviewed and not queued by Daniel from one testing update until another.
>  6. Request automated QA's PRTS automated i-g-t tests comparing drm-intel-testing x drm-intel-collector
>  7. If tests are ok I send the update notification or the patches as a series to intel-gfx mailing list for better tracking and to be reviewed. (drm-intel-collector - updated)
>  8. Let me know volunteers for review new patches and also let me know if I've picked any patch that I shouldn't.
>
> There are some reasons that some patches can be left behind:
> 1. Your patch didn't applied cleanly and I couldn't easily solve the conflicts.
> 2. Kernel didn't compiled with your patch.
> 3. I simply missed it. If you believe this is the case please warn me.
>
> Please help me to get these patches reviewed and queued by Daniel.
>
> Also, please let me know if you have further ideas how to improve this process.
>
> Thanks in advance,
> Rodrigo.
>
>
> Chris Wilson (4):
>   drm/i915: Asynchronously perform the set-base for a simple modeset
>   drm/i915: Do hw quiescing first during unload
>   drm/i915: Hold pc8 lock around toggling pc8.gpu_idle
>   drm/i915: Do not enable package C8 on unsupported hardware
>
> Daniel Vetter (1):
>   drm/i915: print object bindings in debugfs
>
> Mengdong Lin (1):
>   drm/i915/vlv: enable HDMI audio for Valleyview2
>
> Ville Syrjälä (3):
>   drm/i915: Fix gen3/4 vblank counter wraparound
>   drm/i915: Use frame counter for intel_wait_for_vblank() on CTG
>   drm/i915: Enable pipe gamma for sprites
>
>  drivers/gpu/drm/i915/i915_debugfs.c  |  6 ++++
>  drivers/gpu/drm/i915/i915_dma.c      | 10 +++---
>  drivers/gpu/drm/i915/i915_drv.h      |  1 +
>  drivers/gpu/drm/i915/i915_irq.c      |  2 +-
>  drivers/gpu/drm/i915/i915_reg.h      | 20 ++++++++++-
>  drivers/gpu/drm/i915/intel_display.c | 65 ++++++++++++++++++++++++++++--------
>  drivers/gpu/drm/i915/intel_sprite.c  | 18 ++++++++++
>  7 files changed, 103 insertions(+), 19 deletions(-)
>
> --
> 1.8.3.1
>



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

Re: [PATCH 0/9] drm-intel-collector - update

[Ausmus, James]

On Mon, Nov 18, 2013 at 6:32 PM, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
>
> This is another drm-intel-collector updated notice:
> http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=drm-intel-collector
>
> Here goes the update list in order for better reviewers assignment:
>
> Patch     drm/i915: Asynchronously perform the set-base for a simple modeset - Reviewed by me.
> Patch     drm/i915: Fix gen3/4 vblank counter wraparound - Reviewer:
> Patch     drm/i915: Use frame counter for intel_wait_for_vblank() on CTG - Reviewer:
> Patch     drm/i915: Do hw quiescing first during unload - Reviewer:
> Patch     drm/i915: print object bindings in debugfs - Reviewer:
> Patch     drm/i915/vlv: enable HDMI audio for Valleyview2 - Reviewer:
> Patch     drm/i915: Hold pc8 lock around toggling pc8.gpu_idle - Reviewed by Paulo
> Patch     drm/i915: Do not enable package C8 on unsupported hardware - Reviewed by Paulo
> Patch     drm/i915: Enable pipe gamma for sprites - Reviewer:
>
> Overall Process:
>
> drm-intel-collector - review request
>  1. Daniel pushs drm-intel-testing (every 2 weeks)
>  2. I rebase drm-intel-collector onto drm-intel-testing
>  3. Add Reviewer: tag with voluntered reviewers. If you don't believe you should be assigned on a particular patch please don't get mad just tell you wont review or volunteer someone else.
>  4. I resubmit remaining patches for review without picking any new (drm-intel-collector - review request)
>
> drm-intel-collector - updated
>  5. One week later I collect all simple (1-2) patches that wasn't yet reviewed and not queued by Daniel from one testing update until another.
>  6. Request automated QA's PRTS automated i-g-t tests comparing drm-intel-testing x drm-intel-collector
>  7. If tests are ok I send the update notification or the patches as a series to intel-gfx mailing list for better tracking and to be reviewed. (drm-intel-collector - updated)
>  8. Let me know volunteers for review new patches and also let me know if I've picked any patch that I shouldn't.
>
> There are some reasons that some patches can be left behind:
> 1. Your patch didn't applied cleanly and I couldn't easily solve the conflicts.
> 2. Kernel didn't compiled with your patch.
> 3. I simply missed it. If you believe this is the case please warn me.
>
> Please help me to get these patches reviewed and queued by Daniel.
>
> Also, please let me know if you have further ideas how to improve this process.
>
> Thanks in advance,
> Rodrigo.
>
>
> Chris Wilson (4):
>   drm/i915: Asynchronously perform the set-base for a simple modeset
>   drm/i915: Do hw quiescing first during unload
>   drm/i915: Hold pc8 lock around toggling pc8.gpu_idle
>   drm/i915: Do not enable package C8 on unsupported hardware
>
> Daniel Vetter (1):
>   drm/i915: print object bindings in debugfs
>
> Mengdong Lin (1):
>   drm/i915/vlv: enable HDMI audio for Valleyview2

A v4 of this patch was already merged in with a slightly renamed subject:

9ca2fe731b3f12afbc97cf0050dfa4184bd2234c drm/i915/vlv: enable HDA
display audio for Valleyview2


-James

>
> Ville Syrjälä (3):
>   drm/i915: Fix gen3/4 vblank counter wraparound
>   drm/i915: Use frame counter for intel_wait_for_vblank() on CTG
>   drm/i915: Enable pipe gamma for sprites
>
>  drivers/gpu/drm/i915/i915_debugfs.c  |  6 ++++
>  drivers/gpu/drm/i915/i915_dma.c      | 10 +++---
>  drivers/gpu/drm/i915/i915_drv.h      |  1 +
>  drivers/gpu/drm/i915/i915_irq.c      |  2 +-
>  drivers/gpu/drm/i915/i915_reg.h      | 20 ++++++++++-
>  drivers/gpu/drm/i915/intel_display.c | 65 ++++++++++++++++++++++++++++--------
>  drivers/gpu/drm/i915/intel_sprite.c  | 18 ++++++++++
>  7 files changed, 103 insertions(+), 19 deletions(-)
>
> --
> 1.8.3.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 8/9] drm/i915: Do not enable package C8 on unsupported hardware

[Daniel Vetter]

On Mon, Nov 18, 2013 at 06:32:37PM -0800, Rodrigo Vivi wrote:
> From: Chris Wilson <chris@chris-wilson.co.uk>
> 
> If the hardware does not support package C8, then do not even schedule
> work to enable it. Thereby we can eliminate a bunch of dangerous work.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

Ok, I've merged this and the previous patch. Paulo, care to follow up with
an is_ult or something like that in the intel_info struct? We don't really
care about is_mobile on recent platforms any more, but having an is_ult
sounds useful ...
-Daniel

> ---
>  drivers/gpu/drm/i915/i915_drv.h      |  1 +
>  drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++++++
>  2 files changed, 16 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b12d942..bb6a302 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1791,6 +1791,7 @@ struct drm_i915_file_private {
>  #define HAS_POWER_WELL(dev)	(IS_HASWELL(dev))
>  #define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
>  #define HAS_PSR(dev)		(IS_HASWELL(dev))
> +#define HAS_PC8(dev)		(IS_HASWELL(dev)) /* XXX HSW:ULX */
>  
>  #define INTEL_PCH_DEVICE_ID_MASK		0xff00
>  #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index cfcad82..b39d0df 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6473,6 +6473,9 @@ static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
>  
>  void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
>  {
> +	if (!HAS_PC8(dev_priv->dev))
> +		return;
> +
>  	mutex_lock(&dev_priv->pc8.lock);
>  	__hsw_enable_package_c8(dev_priv);
>  	mutex_unlock(&dev_priv->pc8.lock);
> @@ -6480,6 +6483,9 @@ void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
>  
>  void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
>  {
> +	if (!HAS_PC8(dev_priv->dev))
> +		return;
> +
>  	mutex_lock(&dev_priv->pc8.lock);
>  	__hsw_disable_package_c8(dev_priv);
>  	mutex_unlock(&dev_priv->pc8.lock);
> @@ -6517,6 +6523,9 @@ static void hsw_update_package_c8(struct drm_device *dev)
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	bool allow;
>  
> +	if (!HAS_PC8(dev_priv->dev))
> +		return;
> +
>  	if (!i915_enable_pc8)
>  		return;
>  
> @@ -6540,6 +6549,9 @@ done:
>  
>  static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
>  {
> +	if (!HAS_PC8(dev_priv->dev))
> +		return;
> +
>  	mutex_lock(&dev_priv->pc8.lock);
>  	if (!dev_priv->pc8.gpu_idle) {
>  		dev_priv->pc8.gpu_idle = true;
> @@ -6550,6 +6562,9 @@ static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
>  
>  static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
>  {
> +	if (!HAS_PC8(dev_priv->dev))
> +		return;
> +
>  	mutex_lock(&dev_priv->pc8.lock);
>  	if (dev_priv->pc8.gpu_idle) {
>  		dev_priv->pc8.gpu_idle = false;
> -- 
> 1.8.3.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 3/9] drm/i915: Use frame counter for intel_wait_for_vblank() on CTG

[Chris Wilson]

On Mon, Nov 18, 2013 at 06:32:32PM -0800, Rodrigo Vivi wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Use the same wait_for_vblank code for CTG that we use for ILK+.
> 
> Also fix the name of the frame counter register while at it.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 2/9] drm/i915: Fix gen3/4 vblank counter wraparound

[Chris Wilson]

On Mon, Nov 18, 2013 at 06:32:31PM -0800, Rodrigo Vivi wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> When the hardware frame counter reads 0xffffff and we're already past
> vblank start, we'd return 0x1000000 as the vblank counter value. Once
> we'd cross into the next frame's active portion, the vblank counter
> would wrap to 0. So we're reporting two different vblank counter values
> for the same frame.
> 
> Fix the problem by masking the cooked value by 0xffffff to make sure
> the counter wraps already after vblank start.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

Already applied: edc08d0a40f7ddab6bf7249e59ecf692d36c7192
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 5/9] drm/i915: print object bindings in debugfs

[Chris Wilson]

On Mon, Nov 18, 2013 at 06:32:34PM -0800, Rodrigo Vivi wrote:
> From: Daniel Vetter <daniel.vetter@ffwll.ch>
> 
> This is useful when we only have aliasing ppgtt and want to figure out
> what exactly is accesssible and what not. Paulo can somehow overwrite
> the fbcon framebuffer with the blitter on his hsw machine ...
> 
> v2: Actually make it compile.
> 
> Cc: Paulo Zanoni <przanoni@gmail.com>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

This is still too ugly.

(bindings: )
(bindings: g)
(bindings: pp)
(bindings: gpp)
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 3/9] drm/i915: Use frame counter for intel_wait_for_vblank() on CTG

[Daniel Vetter]

On Tue, Nov 19, 2013 at 01:46:55PM +0000, Chris Wilson wrote:
> On Mon, Nov 18, 2013 at 06:32:32PM -0800, Rodrigo Vivi wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Use the same wait_for_vblank code for CTG that we use for ILK+.
> > 
> > Also fix the name of the frame counter register while at it.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

Already merged as 57e22f4add51b, apparently from a previous -collector
round (sinc it has your sob on it). Rebase gone wrong?
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

Re: [PATCH 0/9] drm-intel-collector - update

[Rodrigo Vivi]

On Mon, Nov 18, 2013 at 7:28 PM, Ausmus, James <james.ausmus@intel.com> wrote:
> On Mon, Nov 18, 2013 at 6:32 PM, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
>>
>> This is another drm-intel-collector updated notice:
>> http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=drm-intel-collector
>>
>> Here goes the update list in order for better reviewers assignment:
>>
>> Patch     drm/i915: Asynchronously perform the set-base for a simple modeset - Reviewed by me.
>> Patch     drm/i915: Fix gen3/4 vblank counter wraparound - Reviewer:
>> Patch     drm/i915: Use frame counter for intel_wait_for_vblank() on CTG - Reviewer:
>> Patch     drm/i915: Do hw quiescing first during unload - Reviewer:
>> Patch     drm/i915: print object bindings in debugfs - Reviewer:
>> Patch     drm/i915/vlv: enable HDMI audio for Valleyview2 - Reviewer:
>> Patch     drm/i915: Hold pc8 lock around toggling pc8.gpu_idle - Reviewed by Paulo
>> Patch     drm/i915: Do not enable package C8 on unsupported hardware - Reviewed by Paulo
>> Patch     drm/i915: Enable pipe gamma for sprites - Reviewer:
>>
>> Overall Process:
>>
>> drm-intel-collector - review request
>>  1. Daniel pushs drm-intel-testing (every 2 weeks)
>>  2. I rebase drm-intel-collector onto drm-intel-testing
>>  3. Add Reviewer: tag with voluntered reviewers. If you don't believe you should be assigned on a particular patch please don't get mad just tell you wont review or volunteer someone else.
>>  4. I resubmit remaining patches for review without picking any new (drm-intel-collector - review request)
>>
>> drm-intel-collector - updated
>>  5. One week later I collect all simple (1-2) patches that wasn't yet reviewed and not queued by Daniel from one testing update until another.
>>  6. Request automated QA's PRTS automated i-g-t tests comparing drm-intel-testing x drm-intel-collector
>>  7. If tests are ok I send the update notification or the patches as a series to intel-gfx mailing list for better tracking and to be reviewed. (drm-intel-collector - updated)
>>  8. Let me know volunteers for review new patches and also let me know if I've picked any patch that I shouldn't.
>>
>> There are some reasons that some patches can be left behind:
>> 1. Your patch didn't applied cleanly and I couldn't easily solve the conflicts.
>> 2. Kernel didn't compiled with your patch.
>> 3. I simply missed it. If you believe this is the case please warn me.
>>
>> Please help me to get these patches reviewed and queued by Daniel.
>>
>> Also, please let me know if you have further ideas how to improve this process.
>>
>> Thanks in advance,
>> Rodrigo.
>>
>>
>> Chris Wilson (4):
>>   drm/i915: Asynchronously perform the set-base for a simple modeset
>>   drm/i915: Do hw quiescing first during unload
>>   drm/i915: Hold pc8 lock around toggling pc8.gpu_idle
>>   drm/i915: Do not enable package C8 on unsupported hardware
>>
>> Daniel Vetter (1):
>>   drm/i915: print object bindings in debugfs
>>
>> Mengdong Lin (1):
>>   drm/i915/vlv: enable HDMI audio for Valleyview2
>
> A v4 of this patch was already merged in with a slightly renamed subject:
>
> 9ca2fe731b3f12afbc97cf0050dfa4184bd2234c drm/i915/vlv: enable HDA
> display audio for Valleyview2

Thank you for the warn. I'll remove it.

>
>
> -James
>
>>
>> Ville Syrjälä (3):
>>   drm/i915: Fix gen3/4 vblank counter wraparound
>>   drm/i915: Use frame counter for intel_wait_for_vblank() on CTG
>>   drm/i915: Enable pipe gamma for sprites
>>
>>  drivers/gpu/drm/i915/i915_debugfs.c  |  6 ++++
>>  drivers/gpu/drm/i915/i915_dma.c      | 10 +++---
>>  drivers/gpu/drm/i915/i915_drv.h      |  1 +
>>  drivers/gpu/drm/i915/i915_irq.c      |  2 +-
>>  drivers/gpu/drm/i915/i915_reg.h      | 20 ++++++++++-
>>  drivers/gpu/drm/i915/intel_display.c | 65 ++++++++++++++++++++++++++++--------
>>  drivers/gpu/drm/i915/intel_sprite.c  | 18 ++++++++++
>>  7 files changed, 103 insertions(+), 19 deletions(-)
>>
>> --
>> 1.8.3.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

Re: [PATCH 3/9] drm/i915: Use frame counter for intel_wait_for_vblank() on CTG

[Rodrigo Vivi]

no idea what happened here...
maybe I lost a rebase on my scripts... will rebase or just remove for now

Thanks

On Tue, Nov 19, 2013 at 8:38 AM, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Tue, Nov 19, 2013 at 01:46:55PM +0000, Chris Wilson wrote:
>> On Mon, Nov 18, 2013 at 06:32:32PM -0800, Rodrigo Vivi wrote:
>> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >
>> > Use the same wait_for_vblank code for CTG that we use for ILK+.
>> >
>> > Also fix the name of the frame counter register while at it.
>> >
>> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
>> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
>
> Already merged as 57e22f4add51b, apparently from a previous -collector
> round (sinc it has your sob on it). Rebase gone wrong?
> -Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

Re: [PATCH 5/9] drm/i915: print object bindings in debugfs

[Rodrigo Vivi]

On Tue, Nov 19, 2013 at 5:52 AM, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> On Mon, Nov 18, 2013 at 06:32:34PM -0800, Rodrigo Vivi wrote:
>> From: Daniel Vetter <daniel.vetter@ffwll.ch>
>>
>> This is useful when we only have aliasing ppgtt and want to figure out
>> what exactly is accesssible and what not. Paulo can somehow overwrite
>> the fbcon framebuffer with the blitter on his hsw machine ...
>>
>> v2: Actually make it compile.
>>
>> Cc: Paulo Zanoni <przanoni@gmail.com>
>> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
>
> This is still too ugly.

at least should be the opposite pp before g and complemented with a tt
in the end.

>
> (bindings: )
> (bindings: g)
> (bindings: pp)
> (bindings: gpp)
> -Chris

But what are all real possible options?

nothing, gtt or ppgtt?

>
> --
> Chris Wilson, Intel Open Source Technology Centre



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

Re: [PATCH 9/9] drm/i915: Enable pipe gamma for sprites

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Mon, Nov 18, 2013 at 6:32 PM, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We send the primary and cursor plane data through the gamma unit.
> In order to get matching output from sprites, also send the sprite
> data through the gamma unit.
>
> In the future we should add some properties to control this
> explicitly, and also add properties for the per-sprite gamma ramps
> what have you, but for now this seems like a reasonable thing to do.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h     |  2 +-
>  drivers/gpu/drm/i915/intel_sprite.c | 18 ++++++++++++++++++
>  2 files changed, 19 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8f4916d..7b454d2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3745,7 +3745,7 @@
>
>  #define _SPACNTR               (VLV_DISPLAY_BASE + 0x72180)
>  #define   SP_ENABLE                    (1<<31)
> -#define   SP_GEAMMA_ENABLE             (1<<30)
> +#define   SP_GAMMA_ENABLE              (1<<30)
>  #define   SP_PIXFORMAT_MASK            (0xf<<26)
>  #define   SP_FORMAT_YUV422             (0<<26)
>  #define   SP_FORMAT_BGR565             (5<<26)
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 8afaad6..cb7ffd3 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -104,6 +104,12 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
>                 break;
>         }
>
> +       /*
> +        * Enable gamma to match primary/cursor plane behaviour.
> +        * FIXME should be user controllable via propertiesa.
> +        */
> +       sprctl |= SP_GAMMA_ENABLE;
> +
>         if (obj->tiling_mode != I915_TILING_NONE)
>                 sprctl |= SP_TILED;
>
> @@ -257,6 +263,12 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
>                 BUG();
>         }
>
> +       /*
> +        * Enable gamma to match primary/cursor plane behaviour.
> +        * FIXME should be user controllable via propertiesa.
> +        */
> +       sprctl |= SPRITE_GAMMA_ENABLE;
> +
>         if (obj->tiling_mode != I915_TILING_NONE)
>                 sprctl |= SPRITE_TILED;
>
> @@ -453,6 +465,12 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
>                 BUG();
>         }
>
> +       /*
> +        * Enable gamma to match primary/cursor plane behaviour.
> +        * FIXME should be user controllable via propertiesa.
> +        */
> +       dvscntr |= DVS_GAMMA_ENABLE;
> +
>         if (obj->tiling_mode != I915_TILING_NONE)
>                 dvscntr |= DVS_TILED;
>
> --
> 1.8.3.1
>



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

Re: [PATCH 4/9] drm/i915: Do hw quiescing first during unload

[Rodrigo Vivi]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

On Mon, Nov 18, 2013 at 6:32 PM, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
> From: Chris Wilson <chris@chris-wilson.co.uk>
>
> If we force the hw to idle as our first step during unload, we can abort
> the unload upon failure. Later we can probe whether the hardware remain
> active even after we try to shut it down.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/i915_dma.c | 10 ++++++----
>  1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 0cab2d0..479abc0 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -1704,6 +1704,12 @@ int i915_driver_unload(struct drm_device *dev)
>         struct drm_i915_private *dev_priv = dev->dev_private;
>         int ret;
>
> +       ret = i915_gem_suspend(dev);
> +       if (ret) {
> +               DRM_ERROR("failed to idle hardware: %d\n", ret);
> +               return ret;
> +       }
> +
>         intel_gpu_ips_teardown();
>
>         if (HAS_POWER_WELL(dev)) {
> @@ -1719,10 +1725,6 @@ int i915_driver_unload(struct drm_device *dev)
>         if (dev_priv->mm.inactive_shrinker.scan_objects)
>                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
>
> -       ret = i915_gem_suspend(dev);
> -       if (ret)
> -               DRM_ERROR("failed to idle hardware: %d\n", ret);
> -
>         io_mapping_free(dev_priv->gtt.mappable);
>         arch_phys_wc_del(dev_priv->gtt.mtrr);
>
> --
> 1.8.3.1
>



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

Re: [PATCH 0/9] drm-intel-collector - update

[Rodrigo Vivi]

Hi Daniel, I was missing a rebase on testing.

Anyway, collector is now updated and all patches there are reviewed.
Thanks

On Tue, Nov 19, 2013 at 9:25 AM, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
> On Mon, Nov 18, 2013 at 7:28 PM, Ausmus, James <james.ausmus@intel.com> wrote:
>> On Mon, Nov 18, 2013 at 6:32 PM, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
>>>
>>> This is another drm-intel-collector updated notice:
>>> http://cgit.freedesktop.org/~vivijim/drm-intel/log/?h=drm-intel-collector
>>>
>>> Here goes the update list in order for better reviewers assignment:
>>>
>>> Patch     drm/i915: Asynchronously perform the set-base for a simple modeset - Reviewed by me.
>>> Patch     drm/i915: Fix gen3/4 vblank counter wraparound - Reviewer:
>>> Patch     drm/i915: Use frame counter for intel_wait_for_vblank() on CTG - Reviewer:
>>> Patch     drm/i915: Do hw quiescing first during unload - Reviewer:
>>> Patch     drm/i915: print object bindings in debugfs - Reviewer:
>>> Patch     drm/i915/vlv: enable HDMI audio for Valleyview2 - Reviewer:
>>> Patch     drm/i915: Hold pc8 lock around toggling pc8.gpu_idle - Reviewed by Paulo
>>> Patch     drm/i915: Do not enable package C8 on unsupported hardware - Reviewed by Paulo
>>> Patch     drm/i915: Enable pipe gamma for sprites - Reviewer:
>>>
>>> Overall Process:
>>>
>>> drm-intel-collector - review request
>>>  1. Daniel pushs drm-intel-testing (every 2 weeks)
>>>  2. I rebase drm-intel-collector onto drm-intel-testing
>>>  3. Add Reviewer: tag with voluntered reviewers. If you don't believe you should be assigned on a particular patch please don't get mad just tell you wont review or volunteer someone else.
>>>  4. I resubmit remaining patches for review without picking any new (drm-intel-collector - review request)
>>>
>>> drm-intel-collector - updated
>>>  5. One week later I collect all simple (1-2) patches that wasn't yet reviewed and not queued by Daniel from one testing update until another.
>>>  6. Request automated QA's PRTS automated i-g-t tests comparing drm-intel-testing x drm-intel-collector
>>>  7. If tests are ok I send the update notification or the patches as a series to intel-gfx mailing list for better tracking and to be reviewed. (drm-intel-collector - updated)
>>>  8. Let me know volunteers for review new patches and also let me know if I've picked any patch that I shouldn't.
>>>
>>> There are some reasons that some patches can be left behind:
>>> 1. Your patch didn't applied cleanly and I couldn't easily solve the conflicts.
>>> 2. Kernel didn't compiled with your patch.
>>> 3. I simply missed it. If you believe this is the case please warn me.
>>>
>>> Please help me to get these patches reviewed and queued by Daniel.
>>>
>>> Also, please let me know if you have further ideas how to improve this process.
>>>
>>> Thanks in advance,
>>> Rodrigo.
>>>
>>>
>>> Chris Wilson (4):
>>>   drm/i915: Asynchronously perform the set-base for a simple modeset
>>>   drm/i915: Do hw quiescing first during unload
>>>   drm/i915: Hold pc8 lock around toggling pc8.gpu_idle
>>>   drm/i915: Do not enable package C8 on unsupported hardware
>>>
>>> Daniel Vetter (1):
>>>   drm/i915: print object bindings in debugfs
>>>
>>> Mengdong Lin (1):
>>>   drm/i915/vlv: enable HDMI audio for Valleyview2
>>
>> A v4 of this patch was already merged in with a slightly renamed subject:
>>
>> 9ca2fe731b3f12afbc97cf0050dfa4184bd2234c drm/i915/vlv: enable HDA
>> display audio for Valleyview2
>
> Thank you for the warn. I'll remove it.
>
>>
>>
>> -James
>>
>>>
>>> Ville Syrjälä (3):
>>>   drm/i915: Fix gen3/4 vblank counter wraparound
>>>   drm/i915: Use frame counter for intel_wait_for_vblank() on CTG
>>>   drm/i915: Enable pipe gamma for sprites
>>>
>>>  drivers/gpu/drm/i915/i915_debugfs.c  |  6 ++++
>>>  drivers/gpu/drm/i915/i915_dma.c      | 10 +++---
>>>  drivers/gpu/drm/i915/i915_drv.h      |  1 +
>>>  drivers/gpu/drm/i915/i915_irq.c      |  2 +-
>>>  drivers/gpu/drm/i915/i915_reg.h      | 20 ++++++++++-
>>>  drivers/gpu/drm/i915/intel_display.c | 65 ++++++++++++++++++++++++++++--------
>>>  drivers/gpu/drm/i915/intel_sprite.c  | 18 ++++++++++
>>>  7 files changed, 103 insertions(+), 19 deletions(-)
>>>
>>> --
>>> 1.8.3.1
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
> --
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

Re: [PATCH 5/9] drm/i915: print object bindings in debugfs

[Chris Wilson]

On Tue, Nov 19, 2013 at 09:37:16AM -0800, Rodrigo Vivi wrote:
> On Tue, Nov 19, 2013 at 5:52 AM, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> > On Mon, Nov 18, 2013 at 06:32:34PM -0800, Rodrigo Vivi wrote:
> >> From: Daniel Vetter <daniel.vetter@ffwll.ch>
> >>
> >> This is useful when we only have aliasing ppgtt and want to figure out
> >> what exactly is accesssible and what not. Paulo can somehow overwrite
> >> the fbcon framebuffer with the blitter on his hsw machine ...
> >>
> >> v2: Actually make it compile.
> >>
> >> Cc: Paulo Zanoni <przanoni@gmail.com>
> >> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> >> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
> >
> > This is still too ugly.
> 
> at least should be the opposite pp before g and complemented with a tt
> in the end.
> 
> >
> > (bindings: )
> > (bindings: g)
> > (bindings: pp)
> > (bindings: gpp)
> > -Chris
> 
> But what are all real possible options?
> 
> nothing, gtt or ppgtt?

nothing, gtt, ppggt, both.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre

Re: [PATCH 5/9] drm/i915: print object bindings in debugfs

[Rodrigo Vivi]

On Wed, Nov 20, 2013 at 3:03 AM, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> On Tue, Nov 19, 2013 at 09:37:16AM -0800, Rodrigo Vivi wrote:
>> On Tue, Nov 19, 2013 at 5:52 AM, Chris Wilson <chris@chris-wilson.co.uk> wrote:
>> > On Mon, Nov 18, 2013 at 06:32:34PM -0800, Rodrigo Vivi wrote:
>> >> From: Daniel Vetter <daniel.vetter@ffwll.ch>
>> >>
>> >> This is useful when we only have aliasing ppgtt and want to figure out
>> >> what exactly is accesssible and what not. Paulo can somehow overwrite
>> >> the fbcon framebuffer with the blitter on his hsw machine ...
>> >>
>> >> v2: Actually make it compile.
>> >>
>> >> Cc: Paulo Zanoni <przanoni@gmail.com>
>> >> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>> >> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
>> >
>> > This is still too ugly.
>>
>> at least should be the opposite pp before g and complemented with a tt
>> in the end.
>>
>> >
>> > (bindings: )
>> > (bindings: g)
>> > (bindings: pp)
>> > (bindings: gpp)
>> > -Chris
>>
>> But what are all real possible options?
>>
>> nothing, gtt or ppgtt?
>
> nothing, gtt, ppggt, both.

so, forget what I said...

what about this below?
 seq_printf(m, " (bindings: %s%s)",
                        obj->has_global_gtt_mapping ? "gtt" : "",
                        obj->has_aliasing_ppgtt_mapping ? " ppgtt" : "");

(bindings: )
(bindings: gtt)
(bindings:  ppgtt)
(bindings: gtt ppgtt)


with or without this bikeshed feel free to use:
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

> -Chris
>
> --
> Chris Wilson, Intel Open Source Technology Centre



-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br

Re: [PATCH 9/9] drm/i915: Enable pipe gamma for sprites

[Daniel Vetter]

On Tue, Nov 19, 2013 at 09:42:55AM -0800, Rodrigo Vivi wrote:
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
> 
> On Mon, Nov 18, 2013 at 6:32 PM, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > We send the primary and cursor plane data through the gamma unit.
> > In order to get matching output from sprites, also send the sprite
> > data through the gamma unit.
> >
> > In the future we should add some properties to control this
> > explicitly, and also add properties for the per-sprite gamma ramps
> > what have you, but for now this seems like a reasonable thing to do.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

Eventually we want testcases for this, but I think that's only really
useful once we expose a "bypasss gamma" or similar property. And that is
best done together with exposing all the other csc stuff I'd say. So
merged.
-Daniel

> > ---
> >  drivers/gpu/drm/i915/i915_reg.h     |  2 +-
> >  drivers/gpu/drm/i915/intel_sprite.c | 18 ++++++++++++++++++
> >  2 files changed, 19 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 8f4916d..7b454d2 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3745,7 +3745,7 @@
> >
> >  #define _SPACNTR               (VLV_DISPLAY_BASE + 0x72180)
> >  #define   SP_ENABLE                    (1<<31)
> > -#define   SP_GEAMMA_ENABLE             (1<<30)
> > +#define   SP_GAMMA_ENABLE              (1<<30)
> >  #define   SP_PIXFORMAT_MASK            (0xf<<26)
> >  #define   SP_FORMAT_YUV422             (0<<26)
> >  #define   SP_FORMAT_BGR565             (5<<26)
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> > index 8afaad6..cb7ffd3 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -104,6 +104,12 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
> >                 break;
> >         }
> >
> > +       /*
> > +        * Enable gamma to match primary/cursor plane behaviour.
> > +        * FIXME should be user controllable via propertiesa.
> > +        */
> > +       sprctl |= SP_GAMMA_ENABLE;
> > +
> >         if (obj->tiling_mode != I915_TILING_NONE)
> >                 sprctl |= SP_TILED;
> >
> > @@ -257,6 +263,12 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
> >                 BUG();
> >         }
> >
> > +       /*
> > +        * Enable gamma to match primary/cursor plane behaviour.
> > +        * FIXME should be user controllable via propertiesa.
> > +        */
> > +       sprctl |= SPRITE_GAMMA_ENABLE;
> > +
> >         if (obj->tiling_mode != I915_TILING_NONE)
> >                 sprctl |= SPRITE_TILED;
> >
> > @@ -453,6 +465,12 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
> >                 BUG();
> >         }
> >
> > +       /*
> > +        * Enable gamma to match primary/cursor plane behaviour.
> > +        * FIXME should be user controllable via propertiesa.
> > +        */
> > +       dvscntr |= DVS_GAMMA_ENABLE;
> > +
> >         if (obj->tiling_mode != I915_TILING_NONE)
> >                 dvscntr |= DVS_TILED;
> >
> > --
> > 1.8.3.1
> >
> 
> 
> 
> -- 
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch