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From: Ben Widawsky <ben@bwidawsk.net>
To: "Xiang, Haihao" <haihao.xiang@intel.com>
Cc: Intel GFX <intel-gfx@lists.freedesktop.org>,
	Ben Widawsky <benjamin.widawsky@intel.com>
Subject: Re: [PATCH 1/2] drm/i915/bdw: Force all Data Cache Data Port access to be Non-Coherent
Date: Thu, 12 Dec 2013 17:18:39 -0800	[thread overview]
Message-ID: <20131213011839.GA18545@bwidawsk.net> (raw)
In-Reply-To: <1386897407.18488.56.camel@xhh-ivb32>

On Fri, Dec 13, 2013 at 09:16:47AM +0800, Xiang, Haihao wrote:
> On Thu, 2013-12-12 at 15:28 -0800, Ben Widawsky wrote: 
> > I stumbled on to some unimplemented errata. To be honest, I am not
> > really sure of the impact, just that the docs say to do.
> > 
> > No w/a name for this one.
> > 
> > Cc: Kenneth Graunke <kenneth@whitecape.org>
> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> >  drivers/gpu/drm/i915/intel_pm.c | 7 +++++++
> >  2 files changed, 11 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index e8cc27c..3259e83 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4167,6 +4167,10 @@
> >  #define GEN7_L3SQCREG4				0xb034
> >  #define  L3SQ_URB_READ_CAM_MATCH_DISABLE	(1<<27)
> >  
> > +/* GEN8 chicken */
> > +#define HDC_CHICKEN0				0x7300
> > +#define  HDC_FORCE_NON_COHERENT			(1<<4)
> > +
> >  /* WaCatErrorRejectionIssue */
> >  #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
> >  #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index ac9dd46..7e2a0e9 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -5279,6 +5279,13 @@ static void gen8_init_clock_gating(struct drm_device *dev)
> >  			   I915_READ(CHICKEN_PIPESL_1(i) |
> >  				     DPRS_MASK_VBLANK_SRD));
> >  	}
> > +
> > +	/* Use Force Non-Coherent whenever executing a 3D context. This is a
> > +	 * workaround for for a possible hang in the unlikely event a TLB
> > +	 * invalidation occurs during a PSD flush.
> > +	 */
> > +	I915_WRITE(HDC_FORCE_NON_COHERENT,
> 
> It should be HDC_CHICKEN0 instead of HDC_FORCE_NON_COHERENT
> 
> > +		   I915_READ(HDC_CHICKEN0) | HDC_FORCE_NON_COHERENT);
> 
> It has a mask bit which should be set for writing 
> 
> > }
> >  
> >  static void haswell_init_clock_gating(struct drm_device *dev)
> 
> 

Damn, sorry - I sent the wrong patch. Thanks for catching it.


-- 
Ben Widawsky, Intel Open Source Technology Center

  reply	other threads:[~2013-12-13  1:18 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-12-12 23:28 [PATCH 1/2] drm/i915/bdw: Force all Data Cache Data Port access to be Non-Coherent Ben Widawsky
2013-12-12 23:28 ` [PATCH 2/2] drm/i915/bdw: Implement ff workarounds Ben Widawsky
2013-12-13 11:09   ` Damien Lespiau
2013-12-13 16:56     ` Daniel Vetter
2013-12-13 20:28   ` Kenneth Graunke
2013-12-13  1:16 ` [PATCH 1/2] drm/i915/bdw: Force all Data Cache Data Port access to be Non-Coherent Xiang, Haihao
2013-12-13  1:18   ` Ben Widawsky [this message]
2013-12-13  1:26   ` [PATCH 1/2] [v2] " Ben Widawsky
2013-12-13 10:50     ` Damien Lespiau

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