From: Damien Lespiau <damien.lespiau@intel.com>
To: Ben Widawsky <benjamin.widawsky@intel.com>
Cc: Intel GFX <intel-gfx@lists.freedesktop.org>,
Ben Widawsky <ben@bwidawsk.net>
Subject: Re: [PATCH 1/2] [v2] drm/i915/bdw: Force all Data Cache Data Port access to be Non-Coherent
Date: Fri, 13 Dec 2013 10:50:26 +0000 [thread overview]
Message-ID: <20131213105026.GA809@strange.amr.corp.intel.com> (raw)
In-Reply-To: <1386897963-28188-1-git-send-email-benjamin.widawsky@intel.com>
On Thu, Dec 12, 2013 at 05:26:03PM -0800, Ben Widawsky wrote:
> I stumbled on to some unimplemented errata. To be honest, I am not
> really sure of the impact, just that the docs say to do.
>
> No w/a name for this one.
WaForceEnableNonCoherent looks like a good candidate.
> v2: v1 was a stale thing which should have never seen the light of day.
> (Haihao)
>
> Cc: Kenneth Graunke <kenneth@whitecape.org>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++++
> drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++
> 2 files changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e8cc27c..3259e83 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4167,6 +4167,10 @@
> #define GEN7_L3SQCREG4 0xb034
> #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
>
> +/* GEN8 chicken */
> +#define HDC_CHICKEN0 0x7300
> +#define HDC_FORCE_NON_COHERENT (1<<4)
> +
> /* WaCatErrorRejectionIssue */
> #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
> #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ac9dd46..0665e37 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5279,6 +5279,14 @@ static void gen8_init_clock_gating(struct drm_device *dev)
> I915_READ(CHICKEN_PIPESL_1(i) |
> DPRS_MASK_VBLANK_SRD));
> }
> +
> + /* Use Force Non-Coherent whenever executing a 3D context. This is a
> + * workaround for for a possible hang in the unlikely event a TLB
> + * invalidation occurs during a PSD flush.
> + */
> + I915_WRITE(HDC_CHICKEN0,
> + I915_READ(HDC_CHICKEN0) |
> + _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
> }
>
> static void haswell_init_clock_gating(struct drm_device *dev)
> --
> 1.8.4.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
prev parent reply other threads:[~2013-12-13 10:50 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-12 23:28 [PATCH 1/2] drm/i915/bdw: Force all Data Cache Data Port access to be Non-Coherent Ben Widawsky
2013-12-12 23:28 ` [PATCH 2/2] drm/i915/bdw: Implement ff workarounds Ben Widawsky
2013-12-13 11:09 ` Damien Lespiau
2013-12-13 16:56 ` Daniel Vetter
2013-12-13 20:28 ` Kenneth Graunke
2013-12-13 1:16 ` [PATCH 1/2] drm/i915/bdw: Force all Data Cache Data Port access to be Non-Coherent Xiang, Haihao
2013-12-13 1:18 ` Ben Widawsky
2013-12-13 1:26 ` [PATCH 1/2] [v2] " Ben Widawsky
2013-12-13 10:50 ` Damien Lespiau [this message]
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