From: Daniel Vetter <daniel@ffwll.ch>
To: Damien Lespiau <damien.lespiau@intel.com>
Cc: Intel GFX <intel-gfx@lists.freedesktop.org>,
Ben Widawsky <ben@bwidawsk.net>,
Ben Widawsky <benjamin.widawsky@intel.com>
Subject: Re: [PATCH 2/2] drm/i915/bdw: Implement ff workarounds
Date: Fri, 13 Dec 2013 17:56:54 +0100 [thread overview]
Message-ID: <20131213165654.GW9804@phenom.ffwll.local> (raw)
In-Reply-To: <20131213110958.GC809@strange.amr.corp.intel.com>
On Fri, Dec 13, 2013 at 11:09:58AM +0000, Damien Lespiau wrote:
> On Thu, Dec 12, 2013 at 03:28:04PM -0800, Ben Widawsky wrote:
> > WaVSRefCountFullforceMissDisable and
> > WaDSRefCountFullforceMissDisable
> >
> > VS is a carry-over from HSW, and DS is likely not used by anyone yet.
> >
> > Cc: Kenneth Graunke <kenneth@whitecape.org>
> > Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
>
> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_pm.c | 11 ++++++++---
> > 2 files changed, 9 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 3259e83..f1eece4 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1003,6 +1003,7 @@
> >
> > #define GEN7_FF_THREAD_MODE 0x20a0
> > #define GEN7_FF_SCHED_MASK 0x0077070
> > +#define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
> > #define GEN7_FF_TS_SCHED_HS1 (0x5<<16)
> > #define GEN7_FF_TS_SCHED_HS0 (0x3<<16)
> > #define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16)
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 7e2a0e9..424a9d8 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -5266,14 +5266,14 @@ static void gen8_init_clock_gating(struct drm_device *dev)
> > I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
> > _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE));
> >
> > - /* WaSwitchSolVfFArbitrationPriority */
> > + /* WaSwitchSolVfFArbitrationPriority:bdw */
> > I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
> >
> > - /* WaPsrDPAMaskVBlankInSRD */
> > + /* WaPsrDPAMaskVBlankInSRD:bdw */
> > I915_WRITE(CHICKEN_PAR1_1,
> > I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
> >
> > - /* WaPsrDPRSUnmaskVBlankInSRD */
> > + /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
> > for_each_pipe(i) {
> > I915_WRITE(CHICKEN_PIPESL_1(i),
> > I915_READ(CHICKEN_PIPESL_1(i) |
> > @@ -5286,6 +5286,11 @@ static void gen8_init_clock_gating(struct drm_device *dev)
> > */
> > I915_WRITE(HDC_FORCE_NON_COHERENT,
> > I915_READ(HDC_CHICKEN0) | HDC_FORCE_NON_COHERENT);
> > +
> > + /* WaVSRefCountFullforceMissDisable:bdw */
> > + /* WaDSRefCountFullforceMissDisable:bdw */
> > + I915_WRITE(GEN7_FF_THREAD_MODE,
> > + I915_READ(GEN7_FF_THREAD_MODE) & ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
Even with loads of fugde this is too long. I've broken it. Otherwise both
patches applied, thanks.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
next prev parent reply other threads:[~2013-12-13 16:56 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-12 23:28 [PATCH 1/2] drm/i915/bdw: Force all Data Cache Data Port access to be Non-Coherent Ben Widawsky
2013-12-12 23:28 ` [PATCH 2/2] drm/i915/bdw: Implement ff workarounds Ben Widawsky
2013-12-13 11:09 ` Damien Lespiau
2013-12-13 16:56 ` Daniel Vetter [this message]
2013-12-13 20:28 ` Kenneth Graunke
2013-12-13 1:16 ` [PATCH 1/2] drm/i915/bdw: Force all Data Cache Data Port access to be Non-Coherent Xiang, Haihao
2013-12-13 1:18 ` Ben Widawsky
2013-12-13 1:26 ` [PATCH 1/2] [v2] " Ben Widawsky
2013-12-13 10:50 ` Damien Lespiau
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