From: Ben Widawsky <ben@bwidawsk.net>
To: Daniel Vetter <daniel@ffwll.ch>
Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>,
Mika Kuoppala <mika.kuoppala@intel.com>
Subject: Re: [PATCH] drm/i915: Fail gpu reset if the forcewake fifo hasn't drained
Date: Sat, 8 Mar 2014 12:02:39 -0800 [thread overview]
Message-ID: <20140308200239.GB16546@bwidawsk.net> (raw)
In-Reply-To: <CAKMK7uGwwH64iCxhpXwNVjdDH1VpWZbKV7qKQ6=UzW9HYwnXOg@mail.gmail.com>
On Sat, Mar 08, 2014 at 08:58:24PM +0100, Daniel Vetter wrote:
> On Sat, Mar 8, 2014 at 7:50 PM, Ben Widawsky <ben@bwidawsk.net> wrote:
> > I've seen this too. Though I think the WARN does coincide with what the
> > docs state - it doesn't seem to match reality. So I totally agree this
> > is the right course.
> >
> > However, for my curiosity, Chris, can you elaborate on why you think it
> > doesn't make sense?
>
> Our current fifo code would be broken - we stall for the fifo entries
> to refill if the value drops below NUM_FIFO_ENTRIES_RESERVED. Hence if
> the register value is zero right after reset, something is terribly
> broken.
> -Daniel
Oh that's right. fifo_entries should be MAX, not 0. Wonder if that one
would WARN. Anyway, I'm not actually sure if MAX is always known, so
probably a stupid idea anyway.
--
Ben Widawsky, Intel Open Source Technology Center
prev parent reply other threads:[~2014-03-08 20:02 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-07 20:09 [PATCH] drm/i915: Fail gpu reset if the forcewake fifo hasn't drained Daniel Vetter
2014-03-07 21:35 ` Daniel Vetter
2014-03-08 18:50 ` Ben Widawsky
2014-03-08 19:58 ` Daniel Vetter
2014-03-08 20:02 ` Ben Widawsky [this message]
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