From: Ben Widawsky <ben@bwidawsk.net>
To: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>,
Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: Re: [PATCH] Revert "drm/i915: fix infinite loop at gen6_update_ring_freq"
Date: Thu, 10 Apr 2014 10:52:26 -0700 [thread overview]
Message-ID: <20140410175226.GA8164@bwidawsk.net> (raw)
In-Reply-To: <20140410175043.GB7294@bwidawsk.net>
On Thu, Apr 10, 2014 at 10:50:43AM -0700, Ben Widawsky wrote:
> On Thu, Apr 10, 2014 at 09:04:47AM +0200, Daniel Vetter wrote:
> > This reverts commit 4b28a1f3ef55a3b0b68dbab1fe6dbaf18e186710.
> >
> > This patch duct-tapes over some issue in the current bdw rps patches
> > which must wait with enabling rc6/rps until the very first batch has
> > been submitted by userspace.
> >
> > But those patches aren't merged yet, and for upstream we need to have
> > an in-kernel emission of the very first batch. I shouldn't have
> > merged this patch so let's revert it again.
>
> I said this on the mailing last before you merged the patch.
20140402050338.GB13824@bwidawsk.net
>
> >
> > Also Imre noticed that even when rps is set up normally there's a
> > small window (due to the 1s delay of the async rps init work) where we
> > could runtime suspend already and blow up all over the place. Imre has
> > a proper fix to block runtime pm until the rps init work has
> > successfully completed.
> >
> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Cc: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> > ---
> > drivers/gpu/drm/i915/intel_pm.c | 3 +--
> > 1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 8531cf6e2774..dc7adadbb945 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3522,8 +3522,7 @@ void gen6_update_ring_freq(struct drm_device *dev)
> > * to use for memory access. We do this by specifying the IA frequency
> > * the PCU should use as a reference to determine the ring frequency.
> > */
> > - for (gpu_freq = dev_priv->rps.max_freq_softlimit;
> > - gpu_freq >= dev_priv->rps.min_freq_softlimit && gpu_freq != 0;
> > + for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit;
> > gpu_freq--) {
> > int diff = dev_priv->rps.max_freq_softlimit - gpu_freq;
> > unsigned int ia_freq = 0, ring_freq = 0;
> > --
> > 1.8.5.2
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ben Widawsky, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ben Widawsky, Intel Open Source Technology Center
next prev parent reply other threads:[~2014-04-10 17:52 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-04-10 7:04 [PATCH] Revert "drm/i915: fix infinite loop at gen6_update_ring_freq" Daniel Vetter
2014-04-10 17:50 ` Ben Widawsky
2014-04-10 17:52 ` Ben Widawsky [this message]
2014-04-11 9:02 ` Daniel Vetter
2014-04-22 21:25 ` Paulo Zanoni
2014-04-23 7:05 ` Daniel Vetter
2014-04-28 18:14 ` Paulo Zanoni
2014-04-28 19:23 ` Daniel Vetter
2014-04-28 19:54 ` Imre Deak
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