From: Daniel Vetter <daniel@ffwll.ch>
To: Chris Wilson <chris@chris-wilson.co.uk>,
ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 0/4] drm/i915: Gen2/3 C3 wakeup stuff
Date: Wed, 28 May 2014 14:51:47 +0200 [thread overview]
Message-ID: <20140528125147.GQ14841@phenom.ffwll.local> (raw)
In-Reply-To: <20140528081905.GE18409@nuc-i3427.alporthouse.com>
On Wed, May 28, 2014 at 09:19:05AM +0100, Chris Wilson wrote:
> On Tue, Feb 25, 2014 at 03:13:37PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > I tried to fix the C3 vs. vblank interrupt issues reportd in [1], but
> > it looks like the AGPBUSY# stuff doesn't help there for some reason. I
> > guess either the board isn't wired correctly, or we're missing
> > something else. I doubt the BM wakup mechanism itself would be
> > broken since then I would expect the machine to lock up when someone
> > does DMA while in C3. IIRC I actually had that kind of an issue on
> > some old VIA chipset long ago.
> >
> > Anyways, my 855gm actually supports C3, and on that machine the MI_STATE
> > AGPBUSY# stuff is effective. So I'm going to assume that gen3 behaviour
> > should match, and so I'm just sticking it all into .init_clock_gating()
> > for both gen2 and gen3.
> >
> > I also found another gen3 C3 bit in i915_gem_load(). I think it would
> > be better to collect that into .init_clock_gating() as well. But I left
> > it also in i915_gem_load() for UMS.
> >
> > [1] https://bugs.freedesktop.org/show_bug.cgi?id=30364
> >
> > Ville Syrjälä (4):
> > drm/i915: Set AGPBUSY# bit in init_clock_gating
> > drm/i915: Flip the sense of AGPBUSY_DIS bit
> > drm/i915: Enable interrupt-based AGPBUSY# enable on 85x
> > drm/i915: Move the C3 LP write bit setup to gen3_init_clock_gating()
> > for KMS
>
> They all look sensible, seem to better match the docs than the
> existing code and make the code easier to read (apart from the
> UMS frobbing!), so:
>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Thanks, all merged to dinq.
> The slow vblank delivery issue remains iirc though.
I also wonder whether this could explain the pipe crc issues QA is seeing
on pnv. I'll ping the bug.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
prev parent reply other threads:[~2014-05-28 12:51 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-25 13:13 [PATCH 0/4] drm/i915: Gen2/3 C3 wakeup stuff ville.syrjala
2014-02-25 13:13 ` [PATCH 1/4] drm/i915: Set AGPBUSY# bit in init_clock_gating ville.syrjala
2014-02-25 13:13 ` [PATCH v2 2/4] drm/i915: Flip the sense of AGPBUSY_DIS bit ville.syrjala
2014-02-25 13:13 ` [PATCH 3/4] drm/i915: Enable interrupt-based AGPBUSY# enable on 85x ville.syrjala
2014-02-25 13:13 ` [PATCH 4/4] drm/i915: Move the C3 LP write bit setup to gen3_init_clock_gating() for KMS ville.syrjala
2014-05-28 8:19 ` [PATCH 0/4] drm/i915: Gen2/3 C3 wakeup stuff Chris Wilson
2014-05-28 9:46 ` Ville Syrjälä
2014-05-28 9:59 ` Chris Wilson
2014-05-28 12:51 ` Daniel Vetter [this message]
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