From: Daniel Vetter <daniel@ffwll.ch>
To: Nicolae Badiu <acavano@outlook.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: DevSNB PCI Config Space Registers Reference
Date: Wed, 11 Jun 2014 12:19:44 +0200 [thread overview]
Message-ID: <20140611101944.GG5821@phenom.ffwll.local> (raw)
In-Reply-To: <BLU184-W445B3A73A6FD1878CE107A9280@phx.gbl>
On Tue, Jun 10, 2014 at 03:51:03PM +0000, Nicolae Badiu wrote:
> Hi,
>
> Does anyone have access to the Sandy Bridge 2011 Intel HD Graphics PCI
> Config space register reference? I cannot seem to find it anywhere in
> the PRM docs. There is only a reference to a register called MMAPA at
> office 14h in all DevSNB manuals.
>
> I do see PCI config space documentation for Ivy Bridge and Haswell Intel HD Graphics.
Yeah, this was missed in the snb release.
> Otherwise, pointing me in the right direction w/ regard to the drm-intel source code would also help.
They are sprinkled all over a bit, and we definitely don't have an
exhaustive set of #defines. If you need something specific and
interpolation with ivb/hsw docs doesn't work, please just ping us. Usually
best on irc.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
prev parent reply other threads:[~2014-06-11 10:19 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <BLU184-W32EADC23A6DDF239CE954BA9280@phx.gbl>
2014-06-10 15:51 ` DevSNB PCI Config Space Registers Reference Nicolae Badiu
2014-06-11 10:19 ` Daniel Vetter [this message]
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