* [PATCH] drm/i915/bxt: Set max cdclk frequency properly
@ 2016-04-05 21:37 Matt Roper
2016-04-05 21:55 ` Matt Roper
2016-04-06 8:30 ` ✗ Fi.CI.BAT: failure for " Patchwork
0 siblings, 2 replies; 8+ messages in thread
From: Matt Roper @ 2016-04-05 21:37 UTC (permalink / raw)
To: intel-gfx
intel_update_max_cdclk() doesn't have a switch case for Broxton, so
dev_priv->max_cdclk_freq gets set to whatever clock frequency we're
currently running at (e.g., 144 MHz) rather than the true maximum. This
causes our max dotclock to also be set too low and in turn leads mode
verification to reject perfectly valid modes while loading EDID firmware
blobs.
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index af74cdb..924d851 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5261,6 +5261,8 @@ static void intel_update_max_cdclk(struct drm_device *dev)
dev_priv->max_cdclk_freq = 450000;
else
dev_priv->max_cdclk_freq = 337500;
+ } else if (IS_BROXTON(dev)) {
+ dev_priv->max_cdclk_freq = 624000;
} else if (IS_BROADWELL(dev)) {
/*
* FIXME with extra cooling we can allow
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH] drm/i915/bxt: Set max cdclk frequency properly
2016-04-05 21:37 [PATCH] drm/i915/bxt: Set max cdclk frequency properly Matt Roper
@ 2016-04-05 21:55 ` Matt Roper
2016-04-06 10:28 ` Ville Syrjälä
2016-04-06 17:22 ` Imre Deak
2016-04-06 8:30 ` ✗ Fi.CI.BAT: failure for " Patchwork
1 sibling, 2 replies; 8+ messages in thread
From: Matt Roper @ 2016-04-05 21:55 UTC (permalink / raw)
To: intel-gfx
On Tue, Apr 05, 2016 at 02:37:19PM -0700, Matt Roper wrote:
> intel_update_max_cdclk() doesn't have a switch case for Broxton, so
> dev_priv->max_cdclk_freq gets set to whatever clock frequency we're
> currently running at (e.g., 144 MHz) rather than the true maximum. This
> causes our max dotclock to also be set too low and in turn leads mode
> verification to reject perfectly valid modes while loading EDID firmware
> blobs.
>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
One thing I should have mentioned is that it's unclear to me whether we
should be looking at the cdclk limit bits in the DFSM register like we
do on SKL/KBL. The bspec seems to indicate that the register in general
applies to gen9, including BXT, but the actual meaning of the bits
doesn't match up with the frequencies we have on BXT.
Matt
> drivers/gpu/drm/i915/intel_display.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index af74cdb..924d851 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5261,6 +5261,8 @@ static void intel_update_max_cdclk(struct drm_device *dev)
> dev_priv->max_cdclk_freq = 450000;
> else
> dev_priv->max_cdclk_freq = 337500;
> + } else if (IS_BROXTON(dev)) {
> + dev_priv->max_cdclk_freq = 624000;
> } else if (IS_BROADWELL(dev)) {
> /*
> * FIXME with extra cooling we can allow
> --
> 2.1.4
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH] drm/i915/bxt: Set max cdclk frequency properly
2016-04-05 21:55 ` Matt Roper
@ 2016-04-06 10:28 ` Ville Syrjälä
2016-04-06 14:17 ` Matt Roper
2016-04-06 17:22 ` Imre Deak
1 sibling, 1 reply; 8+ messages in thread
From: Ville Syrjälä @ 2016-04-06 10:28 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On Tue, Apr 05, 2016 at 02:55:51PM -0700, Matt Roper wrote:
> On Tue, Apr 05, 2016 at 02:37:19PM -0700, Matt Roper wrote:
> > intel_update_max_cdclk() doesn't have a switch case for Broxton, so
> > dev_priv->max_cdclk_freq gets set to whatever clock frequency we're
> > currently running at (e.g., 144 MHz) rather than the true maximum. This
> > causes our max dotclock to also be set too low and in turn leads mode
> > verification to reject perfectly valid modes while loading EDID firmware
> > blobs.
> >
> > Cc: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
>
> One thing I should have mentioned is that it's unclear to me whether we
> should be looking at the cdclk limit bits in the DFSM register like we
> do on SKL/KBL. The bspec seems to indicate that the register in general
> applies to gen9, including BXT, but the actual meaning of the bits
> doesn't match up with the frequencies we have on BXT.
It also says
"This field is unused on BXT. Any CD clock frequency limitation must be
done in software."
Anyway the DFSM story is apparently a sad one. See the discussion eg. in
https://lists.freedesktop.org/archives/intel-gfx/2016-February/087510.html
would be nice if someone could pick that up and figure out what we really
want/need to do.
>
>
> Matt
>
> > drivers/gpu/drm/i915/intel_display.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index af74cdb..924d851 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5261,6 +5261,8 @@ static void intel_update_max_cdclk(struct drm_device *dev)
> > dev_priv->max_cdclk_freq = 450000;
> > else
> > dev_priv->max_cdclk_freq = 337500;
> > + } else if (IS_BROXTON(dev)) {
> > + dev_priv->max_cdclk_freq = 624000;
> > } else if (IS_BROADWELL(dev)) {
> > /*
> > * FIXME with extra cooling we can allow
> > --
> > 2.1.4
> >
>
> --
> Matt Roper
> Graphics Software Engineer
> IoTG Platform Enabling & Development
> Intel Corporation
> (916) 356-2795
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH] drm/i915/bxt: Set max cdclk frequency properly
2016-04-06 10:28 ` Ville Syrjälä
@ 2016-04-06 14:17 ` Matt Roper
0 siblings, 0 replies; 8+ messages in thread
From: Matt Roper @ 2016-04-06 14:17 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Wed, Apr 06, 2016 at 01:28:25PM +0300, Ville Syrjälä wrote:
> On Tue, Apr 05, 2016 at 02:55:51PM -0700, Matt Roper wrote:
> > On Tue, Apr 05, 2016 at 02:37:19PM -0700, Matt Roper wrote:
> > > intel_update_max_cdclk() doesn't have a switch case for Broxton, so
> > > dev_priv->max_cdclk_freq gets set to whatever clock frequency we're
> > > currently running at (e.g., 144 MHz) rather than the true maximum. This
> > > causes our max dotclock to also be set too low and in turn leads mode
> > > verification to reject perfectly valid modes while loading EDID firmware
> > > blobs.
> > >
> > > Cc: Imre Deak <imre.deak@intel.com>
> > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > ---
> >
> > One thing I should have mentioned is that it's unclear to me whether we
> > should be looking at the cdclk limit bits in the DFSM register like we
> > do on SKL/KBL. The bspec seems to indicate that the register in general
> > applies to gen9, including BXT, but the actual meaning of the bits
> > doesn't match up with the frequencies we have on BXT.
>
> It also says
> "This field is unused on BXT. Any CD clock frequency limitation must be
> done in software."
>
> Anyway the DFSM story is apparently a sad one. See the discussion eg. in
> https://lists.freedesktop.org/archives/intel-gfx/2016-February/087510.html
> would be nice if someone could pick that up and figure out what we really
> want/need to do.
Oh strange; the note about being unused for BXT gets hidden if you're
filtering the bspec on BXT. I have to remove the filter to see it.
Seems a bit backwards...
Thanks for the confirmation and background.
Matt
>
> >
> >
> > Matt
> >
> > > drivers/gpu/drm/i915/intel_display.c | 2 ++
> > > 1 file changed, 2 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > index af74cdb..924d851 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -5261,6 +5261,8 @@ static void intel_update_max_cdclk(struct drm_device *dev)
> > > dev_priv->max_cdclk_freq = 450000;
> > > else
> > > dev_priv->max_cdclk_freq = 337500;
> > > + } else if (IS_BROXTON(dev)) {
> > > + dev_priv->max_cdclk_freq = 624000;
> > > } else if (IS_BROADWELL(dev)) {
> > > /*
> > > * FIXME with extra cooling we can allow
> > > --
> > > 2.1.4
> > >
> >
> > --
> > Matt Roper
> > Graphics Software Engineer
> > IoTG Platform Enabling & Development
> > Intel Corporation
> > (916) 356-2795
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel OTC
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] drm/i915/bxt: Set max cdclk frequency properly
2016-04-05 21:55 ` Matt Roper
2016-04-06 10:28 ` Ville Syrjälä
@ 2016-04-06 17:22 ` Imre Deak
2016-04-06 18:05 ` Matt Roper
1 sibling, 1 reply; 8+ messages in thread
From: Imre Deak @ 2016-04-06 17:22 UTC (permalink / raw)
To: Matt Roper, intel-gfx
On ti, 2016-04-05 at 14:55 -0700, Matt Roper wrote:
> On Tue, Apr 05, 2016 at 02:37:19PM -0700, Matt Roper wrote:
> > intel_update_max_cdclk() doesn't have a switch case for Broxton, so
> > dev_priv->max_cdclk_freq gets set to whatever clock frequency we're
> > currently running at (e.g., 144 MHz) rather than the true
> > maximum. This
> > causes our max dotclock to also be set too low and in turn leads
> > mode
> > verification to reject perfectly valid modes while loading EDID
> > firmware
> > blobs.
> >
> > Cc: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
>
> One thing I should have mentioned is that it's unclear to me whether we
> should be looking at the cdclk limit bits in the DFSM register like we
> do on SKL/KBL. The bspec seems to indicate that the register in general
> applies to gen9, including BXT, but the actual meaning of the bits
> doesn't match up with the frequencies we have on BXT.
Yes, vendors could restrict the max CDCLK frequency via some method,
but we don't have that mechanism in place anyway and we would use the
hard-coded 624MHz if BIOS didn't enable CDCLK. So this is a correct
fix for now:
Reviewed-by: Imre Deak <imre.deak@intel.com>
>
>
> Matt
>
> > drivers/gpu/drm/i915/intel_display.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index af74cdb..924d851 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5261,6 +5261,8 @@ static void intel_update_max_cdclk(struct
> > drm_device *dev)
> > dev_priv->max_cdclk_freq = 450000;
> > else
> > dev_priv->max_cdclk_freq = 337500;
> > + } else if (IS_BROXTON(dev)) {
> > + dev_priv->max_cdclk_freq = 624000;
> > } else if (IS_BROADWELL(dev)) {
> > /*
> > * FIXME with extra cooling we can allow
> > --
> > 2.1.4
> >
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH] drm/i915/bxt: Set max cdclk frequency properly
2016-04-06 17:22 ` Imre Deak
@ 2016-04-06 18:05 ` Matt Roper
0 siblings, 0 replies; 8+ messages in thread
From: Matt Roper @ 2016-04-06 18:05 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Wed, Apr 06, 2016 at 08:22:56PM +0300, Imre Deak wrote:
> On ti, 2016-04-05 at 14:55 -0700, Matt Roper wrote:
> > On Tue, Apr 05, 2016 at 02:37:19PM -0700, Matt Roper wrote:
> > > intel_update_max_cdclk() doesn't have a switch case for Broxton, so
> > > dev_priv->max_cdclk_freq gets set to whatever clock frequency we're
> > > currently running at (e.g., 144 MHz) rather than the true
> > > maximum. This
> > > causes our max dotclock to also be set too low and in turn leads
> > > mode
> > > verification to reject perfectly valid modes while loading EDID
> > > firmware
> > > blobs.
> > >
> > > Cc: Imre Deak <imre.deak@intel.com>
> > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > ---
> >
> > One thing I should have mentioned is that it's unclear to me whether we
> > should be looking at the cdclk limit bits in the DFSM register like we
> > do on SKL/KBL. The bspec seems to indicate that the register in general
> > applies to gen9, including BXT, but the actual meaning of the bits
> > doesn't match up with the frequencies we have on BXT.
>
> Yes, vendors could restrict the max CDCLK frequency via some method,
> but we don't have that mechanism in place anyway and we would use the
> hard-coded 624MHz if BIOS didn't enable CDCLK. So this is a correct
> fix for now:
>
> Reviewed-by: Imre Deak <imre.deak@intel.com>
Thanks for the review. Pushed to dinq.
Matt
>
> >
> >
> > Matt
> >
> > > drivers/gpu/drm/i915/intel_display.c | 2 ++
> > > 1 file changed, 2 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > b/drivers/gpu/drm/i915/intel_display.c
> > > index af74cdb..924d851 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -5261,6 +5261,8 @@ static void intel_update_max_cdclk(struct
> > > drm_device *dev)
> > > dev_priv->max_cdclk_freq = 450000;
> > > else
> > > dev_priv->max_cdclk_freq = 337500;
> > > + } else if (IS_BROXTON(dev)) {
> > > + dev_priv->max_cdclk_freq = 624000;
> > > } else if (IS_BROADWELL(dev)) {
> > > /*
> > > * FIXME with extra cooling we can allow
> > > --
> > > 2.1.4
> > >
> >
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/bxt: Set max cdclk frequency properly
2016-04-05 21:37 [PATCH] drm/i915/bxt: Set max cdclk frequency properly Matt Roper
2016-04-05 21:55 ` Matt Roper
@ 2016-04-06 8:30 ` Patchwork
2016-04-06 17:58 ` Matt Roper
1 sibling, 1 reply; 8+ messages in thread
From: Patchwork @ 2016-04-06 8:30 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/bxt: Set max cdclk frequency properly
URL : https://patchwork.freedesktop.org/series/5348/
State : failure
== Summary ==
Series 5348v1 drm/i915/bxt: Set max cdclk frequency properly
http://patchwork.freedesktop.org/api/1.0/series/5348/revisions/1/mbox/
Test gem_sync:
Subgroup basic-all:
dmesg-fail -> PASS (bsw-nuc-2)
Test kms_flip:
Subgroup basic-flip-vs-dpms:
dmesg-warn -> PASS (ilk-hp8440p) UNSTABLE
Subgroup basic-flip-vs-wf_vblank:
pass -> FAIL (bsw-nuc-2)
Test kms_force_connector_basic:
Subgroup prune-stale-modes:
skip -> PASS (ivb-t430s)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-c:
dmesg-warn -> PASS (bsw-nuc-2)
bdw-nuci7 total:196 pass:184 dwarn:0 dfail:0 fail:0 skip:12
bdw-ultra total:196 pass:175 dwarn:0 dfail:0 fail:0 skip:21
bsw-nuc-2 total:196 pass:158 dwarn:0 dfail:0 fail:1 skip:37
byt-nuc total:196 pass:161 dwarn:0 dfail:0 fail:0 skip:35
hsw-brixbox total:196 pass:174 dwarn:0 dfail:0 fail:0 skip:22
hsw-gt2 total:196 pass:179 dwarn:0 dfail:0 fail:0 skip:17
ilk-hp8440p total:196 pass:132 dwarn:0 dfail:0 fail:0 skip:64
ivb-t430s total:196 pass:171 dwarn:0 dfail:0 fail:0 skip:25
skl-i7k-2 total:196 pass:173 dwarn:0 dfail:0 fail:0 skip:23
skl-nuci5 total:196 pass:185 dwarn:0 dfail:0 fail:0 skip:11
snb-dellxps total:196 pass:162 dwarn:0 dfail:0 fail:0 skip:34
snb-x220t total:196 pass:162 dwarn:0 dfail:0 fail:1 skip:33
Results at /archive/results/CI_IGT_test/Patchwork_1811/
12899f13b8ee9a4944f167a08e4db0526a3f3855 drm-intel-nightly: 2016y-04m-05d-19h-09m-25s UTC integration manifest
65c53e538f64d2242ed44e62134c4f73d6737590 drm/i915/bxt: Set max cdclk frequency properly
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: ✗ Fi.CI.BAT: failure for drm/i915/bxt: Set max cdclk frequency properly
2016-04-06 8:30 ` ✗ Fi.CI.BAT: failure for " Patchwork
@ 2016-04-06 17:58 ` Matt Roper
0 siblings, 0 replies; 8+ messages in thread
From: Matt Roper @ 2016-04-06 17:58 UTC (permalink / raw)
To: intel-gfx
On Wed, Apr 06, 2016 at 08:30:00AM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/bxt: Set max cdclk frequency properly
> URL : https://patchwork.freedesktop.org/series/5348/
> State : failure
>
> == Summary ==
>
> Series 5348v1 drm/i915/bxt: Set max cdclk frequency properly
> http://patchwork.freedesktop.org/api/1.0/series/5348/revisions/1/mbox/
>
> Test gem_sync:
> Subgroup basic-all:
> dmesg-fail -> PASS (bsw-nuc-2)
> Test kms_flip:
> Subgroup basic-flip-vs-dpms:
> dmesg-warn -> PASS (ilk-hp8440p) UNSTABLE
> Subgroup basic-flip-vs-wf_vblank:
> pass -> FAIL (bsw-nuc-2)
https://bugs.freedesktop.org/show_bug.cgi?id=94294
> Test kms_force_connector_basic:
> Subgroup prune-stale-modes:
> skip -> PASS (ivb-t430s)
> Test kms_pipe_crc_basic:
> Subgroup suspend-read-crc-pipe-c:
> dmesg-warn -> PASS (bsw-nuc-2)
>
> bdw-nuci7 total:196 pass:184 dwarn:0 dfail:0 fail:0 skip:12
> bdw-ultra total:196 pass:175 dwarn:0 dfail:0 fail:0 skip:21
> bsw-nuc-2 total:196 pass:158 dwarn:0 dfail:0 fail:1 skip:37
> byt-nuc total:196 pass:161 dwarn:0 dfail:0 fail:0 skip:35
> hsw-brixbox total:196 pass:174 dwarn:0 dfail:0 fail:0 skip:22
> hsw-gt2 total:196 pass:179 dwarn:0 dfail:0 fail:0 skip:17
> ilk-hp8440p total:196 pass:132 dwarn:0 dfail:0 fail:0 skip:64
> ivb-t430s total:196 pass:171 dwarn:0 dfail:0 fail:0 skip:25
> skl-i7k-2 total:196 pass:173 dwarn:0 dfail:0 fail:0 skip:23
> skl-nuci5 total:196 pass:185 dwarn:0 dfail:0 fail:0 skip:11
> snb-dellxps total:196 pass:162 dwarn:0 dfail:0 fail:0 skip:34
> snb-x220t total:196 pass:162 dwarn:0 dfail:0 fail:1 skip:33
>
> Results at /archive/results/CI_IGT_test/Patchwork_1811/
>
> 12899f13b8ee9a4944f167a08e4db0526a3f3855 drm-intel-nightly: 2016y-04m-05d-19h-09m-25s UTC integration manifest
> 65c53e538f64d2242ed44e62134c4f73d6737590 drm/i915/bxt: Set max cdclk frequency properly
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2016-04-06 18:06 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
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2016-04-05 21:37 [PATCH] drm/i915/bxt: Set max cdclk frequency properly Matt Roper
2016-04-05 21:55 ` Matt Roper
2016-04-06 10:28 ` Ville Syrjälä
2016-04-06 14:17 ` Matt Roper
2016-04-06 17:22 ` Imre Deak
2016-04-06 18:05 ` Matt Roper
2016-04-06 8:30 ` ✗ Fi.CI.BAT: failure for " Patchwork
2016-04-06 17:58 ` Matt Roper
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