* [PATCH v2 1/4] drm/i915/glk: Fix watermark computations for third sprite plane
2017-02-23 7:15 [PATCH v2 0/4] GLK plane/scaling fixes Ander Conselvan de Oliveira
@ 2017-02-23 7:15 ` Ander Conselvan de Oliveira
2017-02-23 10:02 ` Ville Syrjälä
2017-02-23 7:15 ` [PATCH v2 2/4] drm/i915/glk: Fix maximum scaling factor for Geminilake scalers Ander Conselvan de Oliveira
` (3 subsequent siblings)
4 siblings, 1 reply; 14+ messages in thread
From: Ander Conselvan de Oliveira @ 2017-02-23 7:15 UTC (permalink / raw)
To: intel-gfx, Ville Syrjälä
Cc: Daniel Vetter, Ander Conselvan de Oliveira, drm-intel-fixes,
Rodrigo Vivi
Geminilake has a third sprite plane (or fourth universal plane) that is
independent from the cursor. Make sure that for_each_plane_id_on_crtc()
is aware of that extra plane so that the watermark code takes it into
account.
Fixes: e9c9882556fc ("drm/i915/glk: Configure number of sprite planes properly")
Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Cc: <drm-intel-fixes@lists.freedesktop.org>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e346b2d..70892ea 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -293,6 +293,7 @@ enum plane_id {
PLANE_PRIMARY,
PLANE_SPRITE0,
PLANE_SPRITE1,
+ PLANE_SPRITE2,
PLANE_CURSOR,
I915_MAX_PLANES,
};
--
2.9.3
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v2 1/4] drm/i915/glk: Fix watermark computations for third sprite plane
2017-02-23 7:15 ` [PATCH v2 1/4] drm/i915/glk: Fix watermark computations for third sprite plane Ander Conselvan de Oliveira
@ 2017-02-23 10:02 ` Ville Syrjälä
2017-02-23 12:24 ` Ander Conselvan De Oliveira
0 siblings, 1 reply; 14+ messages in thread
From: Ville Syrjälä @ 2017-02-23 10:02 UTC (permalink / raw)
To: Ander Conselvan de Oliveira
Cc: Daniel Vetter, intel-gfx, drm-intel-fixes, Rodrigo Vivi
On Thu, Feb 23, 2017 at 09:15:57AM +0200, Ander Conselvan de Oliveira wrote:
> Geminilake has a third sprite plane (or fourth universal plane) that is
> independent from the cursor. Make sure that for_each_plane_id_on_crtc()
> is aware of that extra plane so that the watermark code takes it into
> account.
I wonder if we still have various pin_count limits and whatnot based on
some hardcoded theoretical max numner of planes...
>
> Fixes: e9c9882556fc ("drm/i915/glk: Configure number of sprite planes properly")
> Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Daniel Vetter <daniel.vetter@intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Cc: <drm-intel-fixes@lists.freedesktop.org>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index e346b2d..70892ea 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -293,6 +293,7 @@ enum plane_id {
> PLANE_PRIMARY,
> PLANE_SPRITE0,
> PLANE_SPRITE1,
> + PLANE_SPRITE2,
> PLANE_CURSOR,
> I915_MAX_PLANES,
> };
> --
> 2.9.3
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v2 1/4] drm/i915/glk: Fix watermark computations for third sprite plane
2017-02-23 10:02 ` Ville Syrjälä
@ 2017-02-23 12:24 ` Ander Conselvan De Oliveira
2017-02-23 13:16 ` Ville Syrjälä
0 siblings, 1 reply; 14+ messages in thread
From: Ander Conselvan De Oliveira @ 2017-02-23 12:24 UTC (permalink / raw)
To: Ville Syrjälä
Cc: Daniel Vetter, intel-gfx, drm-intel-fixes, Rodrigo Vivi
On Thu, 2017-02-23 at 12:02 +0200, Ville Syrjälä wrote:
> On Thu, Feb 23, 2017 at 09:15:57AM +0200, Ander Conselvan de Oliveira wrote:
> > Geminilake has a third sprite plane (or fourth universal plane) that is
> > independent from the cursor. Make sure that for_each_plane_id_on_crtc()
> > is aware of that extra plane so that the watermark code takes it into
> > account.
>
> I wonder if we still have various pin_count limits and whatnot based on
> some hardcoded theoretical max numner of planes...
Where were those before? I can't see anything obvious but I also don't know
where to look for them?
Ander
> > Fixes: e9c9882556fc ("drm/i915/glk: Configure number of sprite planes properly")
> > Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Daniel Vetter <daniel.vetter@intel.com>
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > Cc: intel-gfx@lists.freedesktop.org
> > Cc: <drm-intel-fixes@lists.freedesktop.org>
> > Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> > ---
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index e346b2d..70892ea 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -293,6 +293,7 @@ enum plane_id {
> > PLANE_PRIMARY,
> > PLANE_SPRITE0,
> > PLANE_SPRITE1,
> > + PLANE_SPRITE2,
> > PLANE_CURSOR,
> > I915_MAX_PLANES,
> > };
> > --
> > 2.9.3
>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v2 1/4] drm/i915/glk: Fix watermark computations for third sprite plane
2017-02-23 12:24 ` Ander Conselvan De Oliveira
@ 2017-02-23 13:16 ` Ville Syrjälä
0 siblings, 0 replies; 14+ messages in thread
From: Ville Syrjälä @ 2017-02-23 13:16 UTC (permalink / raw)
To: Ander Conselvan De Oliveira
Cc: Daniel Vetter, intel-gfx, drm-intel-fixes, Rodrigo Vivi
On Thu, Feb 23, 2017 at 02:24:44PM +0200, Ander Conselvan De Oliveira wrote:
> On Thu, 2017-02-23 at 12:02 +0200, Ville Syrjälä wrote:
> > On Thu, Feb 23, 2017 at 09:15:57AM +0200, Ander Conselvan de Oliveira wrote:
> > > Geminilake has a third sprite plane (or fourth universal plane) that is
> > > independent from the cursor. Make sure that for_each_plane_id_on_crtc()
> > > is aware of that extra plane so that the watermark code takes it into
> > > account.
> >
> > I wonder if we still have various pin_count limits and whatnot based on
> > some hardcoded theoretical max numner of planes...
>
> Where were those before? I can't see anything obvious but I also don't know
> where to look for them?
Looks like it's called I915_VMA_PIN_MASK these days. So depending on
how we pin on plane updates I suppose that more or less allows us to
use the same vma with 8 or 16 planes simultanosly, minus all the other
pins of course. So I'm not sure if we're exceeding that limit or not.
Might be nice to have an igt that tries to maximize the number of pins
on the same vma.
>
> Ander
>
> > > Fixes: e9c9882556fc ("drm/i915/glk: Configure number of sprite planes properly")
> > > Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > Cc: Daniel Vetter <daniel.vetter@intel.com>
> > > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > > Cc: intel-gfx@lists.freedesktop.org
> > > Cc: <drm-intel-fixes@lists.freedesktop.org>
> > > Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> >
> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > > ---
> > > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > > 1 file changed, 1 insertion(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > index e346b2d..70892ea 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -293,6 +293,7 @@ enum plane_id {
> > > PLANE_PRIMARY,
> > > PLANE_SPRITE0,
> > > PLANE_SPRITE1,
> > > + PLANE_SPRITE2,
> > > PLANE_CURSOR,
> > > I915_MAX_PLANES,
> > > };
> > > --
> > > 2.9.3
> >
> >
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 2/4] drm/i915/glk: Fix maximum scaling factor for Geminilake scalers
2017-02-23 7:15 [PATCH v2 0/4] GLK plane/scaling fixes Ander Conselvan de Oliveira
2017-02-23 7:15 ` [PATCH v2 1/4] drm/i915/glk: Fix watermark computations for third sprite plane Ander Conselvan de Oliveira
@ 2017-02-23 7:15 ` Ander Conselvan de Oliveira
2017-02-23 10:04 ` Ville Syrjälä
2017-02-23 7:15 ` [PATCH v2 3/4] drm/i915/glk: Pass dev_priv to intel_atomic_setup_scalers() Ander Conselvan de Oliveira
` (2 subsequent siblings)
4 siblings, 1 reply; 14+ messages in thread
From: Ander Conselvan de Oliveira @ 2017-02-23 7:15 UTC (permalink / raw)
To: intel-gfx, Ville Syrjälä
Cc: Ander Conselvan de Oliveira, Rodrigo Vivi
Geminilake can output two pixels per clock, and that affects the maximum
scaling factor for its scalers. Take that into account and avoid the
following warning:
WARNING: CPU: 1 PID: 593 at drivers/gpu/drm/i915/intel_display.c:13223 skl_max_scale.part.129+0x78/0x80 [i915]
WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)
Modules linked in: x86_pkg_temp_thermal i915 coretemp kvm_intel kvm i2c_algo_bit drm_kms_helper irqbypass crct10dif_pclmul prime_numbers crc32_pclmul drm ghash_clmulni_intel shpchp tpm_tis tpm_tis_core tpm nfsd authw
CPU: 1 PID: 593 Comm: kworker/u8:3 Tainted: G W 4.10.0-rc8ander+ #330
Hardware name: Intel Corp. Geminilake/GLK RVP1 DDR4 (05), BIOS GELKRVPA.X64.0035.B33.1702150552 02/15/2017
Workqueue: events_unbound async_run_entry_fn
Call Trace:
dump_stack+0x86/0xc3
__warn+0xcb/0xf0
warn_slowpath_fmt+0x5f/0x80
skl_max_scale.part.129+0x78/0x80 [i915]
intel_check_primary_plane+0xa6/0xc0 [i915]
intel_plane_atomic_check_with_state+0xd1/0x1a0 [i915]
? drm_printk+0xb5/0xc0 [drm]
intel_plane_atomic_check+0x3d/0x80 [i915]
drm_atomic_helper_check_planes+0x7c/0x200 [drm_kms_helper]
intel_atomic_check+0xa5b/0x11a0 [i915]
drm_atomic_check_only+0x353/0x600 [drm]
? drm_atomic_add_affected_connectors+0x10c/0x120 [drm]
drm_atomic_commit+0x18/0x50 [drm]
restore_fbdev_mode+0x14c/0x2a0 [drm_kms_helper]
drm_fb_helper_restore_fbdev_mode_unlocked+0x34/0x80 [drm_kms_helper]
drm_fb_helper_set_par+0x2d/0x60 [drm_kms_helper]
intel_fbdev_set_par+0x1a/0x70 [i915]
fbcon_init+0x582/0x610
visual_init+0xd6/0x130
do_bind_con_driver+0x1da/0x3c0
do_take_over_console+0x116/0x180
do_fbcon_takeover+0x5c/0xb0
fbcon_event_notify+0x772/0x8a0
? __blocking_notifier_call_chain+0x35/0x70
notifier_call_chain+0x4a/0x70
__blocking_notifier_call_chain+0x4d/0x70
blocking_notifier_call_chain+0x16/0x20
fb_notifier_call_chain+0x1b/0x20
register_framebuffer+0x278/0x360
drm_fb_helper_initial_config+0x253/0x440 [drm_kms_helper]
intel_fbdev_initial_config+0x18/0x30 [i915]
async_run_entry_fn+0x39/0x170
process_one_work+0x212/0x670
? process_one_work+0x197/0x670
worker_thread+0x4e/0x490
kthread+0x101/0x140
? process_one_work+0x670/0x670
? kthread_create_on_node+0x60/0x60
ret_from_fork+0x31/0x40
v2: s/max_pixclk/max_dotclk/ (Ville)
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 957c62d..6b65adf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13211,16 +13211,22 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
int
skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
{
+ struct drm_i915_private *dev_priv;
int max_scale;
- int crtc_clock, cdclk;
+ int crtc_clock, max_dotclk;
if (!intel_crtc || !crtc_state->base.enable)
return DRM_PLANE_HELPER_NO_SCALING;
+ dev_priv = to_i915(intel_crtc->base.dev);
+
crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
- cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
+ max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
+
+ if (IS_GEMINILAKE(dev_priv))
+ max_dotclk *= 2;
- if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
+ if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
return DRM_PLANE_HELPER_NO_SCALING;
/*
@@ -13229,7 +13235,8 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state
* or
* cdclk/crtc_clock
*/
- max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
+ max_scale = min((1 << 16) * 3 - 1,
+ (1 << 8) * ((max_dotclk << 8) / crtc_clock));
return max_scale;
}
--
2.9.3
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v2 2/4] drm/i915/glk: Fix maximum scaling factor for Geminilake scalers
2017-02-23 7:15 ` [PATCH v2 2/4] drm/i915/glk: Fix maximum scaling factor for Geminilake scalers Ander Conselvan de Oliveira
@ 2017-02-23 10:04 ` Ville Syrjälä
2017-02-23 12:26 ` Ander Conselvan De Oliveira
0 siblings, 1 reply; 14+ messages in thread
From: Ville Syrjälä @ 2017-02-23 10:04 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx, Rodrigo Vivi
On Thu, Feb 23, 2017 at 09:15:58AM +0200, Ander Conselvan de Oliveira wrote:
> Geminilake can output two pixels per clock, and that affects the maximum
> scaling factor for its scalers. Take that into account and avoid the
> following warning:
>
> WARNING: CPU: 1 PID: 593 at drivers/gpu/drm/i915/intel_display.c:13223 skl_max_scale.part.129+0x78/0x80 [i915]
> WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)
> Modules linked in: x86_pkg_temp_thermal i915 coretemp kvm_intel kvm i2c_algo_bit drm_kms_helper irqbypass crct10dif_pclmul prime_numbers crc32_pclmul drm ghash_clmulni_intel shpchp tpm_tis tpm_tis_core tpm nfsd authw
> CPU: 1 PID: 593 Comm: kworker/u8:3 Tainted: G W 4.10.0-rc8ander+ #330
> Hardware name: Intel Corp. Geminilake/GLK RVP1 DDR4 (05), BIOS GELKRVPA.X64.0035.B33.1702150552 02/15/2017
> Workqueue: events_unbound async_run_entry_fn
> Call Trace:
> dump_stack+0x86/0xc3
> __warn+0xcb/0xf0
> warn_slowpath_fmt+0x5f/0x80
> skl_max_scale.part.129+0x78/0x80 [i915]
> intel_check_primary_plane+0xa6/0xc0 [i915]
> intel_plane_atomic_check_with_state+0xd1/0x1a0 [i915]
> ? drm_printk+0xb5/0xc0 [drm]
> intel_plane_atomic_check+0x3d/0x80 [i915]
> drm_atomic_helper_check_planes+0x7c/0x200 [drm_kms_helper]
> intel_atomic_check+0xa5b/0x11a0 [i915]
> drm_atomic_check_only+0x353/0x600 [drm]
> ? drm_atomic_add_affected_connectors+0x10c/0x120 [drm]
> drm_atomic_commit+0x18/0x50 [drm]
> restore_fbdev_mode+0x14c/0x2a0 [drm_kms_helper]
> drm_fb_helper_restore_fbdev_mode_unlocked+0x34/0x80 [drm_kms_helper]
> drm_fb_helper_set_par+0x2d/0x60 [drm_kms_helper]
> intel_fbdev_set_par+0x1a/0x70 [i915]
> fbcon_init+0x582/0x610
> visual_init+0xd6/0x130
> do_bind_con_driver+0x1da/0x3c0
> do_take_over_console+0x116/0x180
> do_fbcon_takeover+0x5c/0xb0
> fbcon_event_notify+0x772/0x8a0
> ? __blocking_notifier_call_chain+0x35/0x70
> notifier_call_chain+0x4a/0x70
> __blocking_notifier_call_chain+0x4d/0x70
> blocking_notifier_call_chain+0x16/0x20
> fb_notifier_call_chain+0x1b/0x20
> register_framebuffer+0x278/0x360
> drm_fb_helper_initial_config+0x253/0x440 [drm_kms_helper]
> intel_fbdev_initial_config+0x18/0x30 [i915]
> async_run_entry_fn+0x39/0x170
> process_one_work+0x212/0x670
> ? process_one_work+0x197/0x670
> worker_thread+0x4e/0x490
> kthread+0x101/0x140
> ? process_one_work+0x670/0x670
> ? kthread_create_on_node+0x60/0x60
> ret_from_fork+0x31/0x40
>
> v2: s/max_pixclk/max_dotclk/ (Ville)
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++----
> 1 file changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 957c62d..6b65adf 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13211,16 +13211,22 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
> int
> skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
> {
> + struct drm_i915_private *dev_priv;
> int max_scale;
> - int crtc_clock, cdclk;
> + int crtc_clock, max_dotclk;
>
> if (!intel_crtc || !crtc_state->base.enable)
> return DRM_PLANE_HELPER_NO_SCALING;
>
> + dev_priv = to_i915(intel_crtc->base.dev);
> +
> crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
> - cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
> + max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
I actually meant using dev_priv->max_dotclock (or whatever it was
called). But now that I actually read the code I see that it wouldn't
work. So this looks fine
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> +
> + if (IS_GEMINILAKE(dev_priv))
> + max_dotclk *= 2;
>
> - if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
> + if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
> return DRM_PLANE_HELPER_NO_SCALING;
>
> /*
> @@ -13229,7 +13235,8 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state
> * or
> * cdclk/crtc_clock
> */
> - max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
> + max_scale = min((1 << 16) * 3 - 1,
> + (1 << 8) * ((max_dotclk << 8) / crtc_clock));
>
> return max_scale;
> }
> --
> 2.9.3
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH v2 2/4] drm/i915/glk: Fix maximum scaling factor for Geminilake scalers
2017-02-23 10:04 ` Ville Syrjälä
@ 2017-02-23 12:26 ` Ander Conselvan De Oliveira
0 siblings, 0 replies; 14+ messages in thread
From: Ander Conselvan De Oliveira @ 2017-02-23 12:26 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, Rodrigo Vivi
On Thu, 2017-02-23 at 12:04 +0200, Ville Syrjälä wrote:
> On Thu, Feb 23, 2017 at 09:15:58AM +0200, Ander Conselvan de Oliveira wrote:
> > Geminilake can output two pixels per clock, and that affects the maximum
> > scaling factor for its scalers. Take that into account and avoid the
> > following warning:
> >
> > WARNING: CPU: 1 PID: 593 at drivers/gpu/drm/i915/intel_display.c:13223 skl_max_scale.part.129+0x78/0x80 [i915]
> > WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)
> > Modules linked in: x86_pkg_temp_thermal i915 coretemp kvm_intel kvm i2c_algo_bit drm_kms_helper irqbypass crct10dif_pclmul prime_numbers crc32_pclmul drm ghash_clmulni_intel shpchp tpm_tis tpm_tis_core tpm nfsd authw
> > CPU: 1 PID: 593 Comm: kworker/u8:3 Tainted: G W 4.10.0-rc8ander+ #330
> > Hardware name: Intel Corp. Geminilake/GLK RVP1 DDR4 (05), BIOS GELKRVPA.X64.0035.B33.1702150552 02/15/2017
> > Workqueue: events_unbound async_run_entry_fn
> > Call Trace:
> > dump_stack+0x86/0xc3
> > __warn+0xcb/0xf0
> > warn_slowpath_fmt+0x5f/0x80
> > skl_max_scale.part.129+0x78/0x80 [i915]
> > intel_check_primary_plane+0xa6/0xc0 [i915]
> > intel_plane_atomic_check_with_state+0xd1/0x1a0 [i915]
> > ? drm_printk+0xb5/0xc0 [drm]
> > intel_plane_atomic_check+0x3d/0x80 [i915]
> > drm_atomic_helper_check_planes+0x7c/0x200 [drm_kms_helper]
> > intel_atomic_check+0xa5b/0x11a0 [i915]
> > drm_atomic_check_only+0x353/0x600 [drm]
> > ? drm_atomic_add_affected_connectors+0x10c/0x120 [drm]
> > drm_atomic_commit+0x18/0x50 [drm]
> > restore_fbdev_mode+0x14c/0x2a0 [drm_kms_helper]
> > drm_fb_helper_restore_fbdev_mode_unlocked+0x34/0x80 [drm_kms_helper]
> > drm_fb_helper_set_par+0x2d/0x60 [drm_kms_helper]
> > intel_fbdev_set_par+0x1a/0x70 [i915]
> > fbcon_init+0x582/0x610
> > visual_init+0xd6/0x130
> > do_bind_con_driver+0x1da/0x3c0
> > do_take_over_console+0x116/0x180
> > do_fbcon_takeover+0x5c/0xb0
> > fbcon_event_notify+0x772/0x8a0
> > ? __blocking_notifier_call_chain+0x35/0x70
> > notifier_call_chain+0x4a/0x70
> > __blocking_notifier_call_chain+0x4d/0x70
> > blocking_notifier_call_chain+0x16/0x20
> > fb_notifier_call_chain+0x1b/0x20
> > register_framebuffer+0x278/0x360
> > drm_fb_helper_initial_config+0x253/0x440 [drm_kms_helper]
> > intel_fbdev_initial_config+0x18/0x30 [i915]
> > async_run_entry_fn+0x39/0x170
> > process_one_work+0x212/0x670
> > ? process_one_work+0x197/0x670
> > worker_thread+0x4e/0x490
> > kthread+0x101/0x140
> > ? process_one_work+0x670/0x670
> > ? kthread_create_on_node+0x60/0x60
> > ret_from_fork+0x31/0x40
> >
> > v2: s/max_pixclk/max_dotclk/ (Ville)
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 15 +++++++++++----
> > 1 file changed, 11 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 957c62d..6b65adf 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -13211,16 +13211,22 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
> > int
> > skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
> > {
> > + struct drm_i915_private *dev_priv;
> > int max_scale;
> > - int crtc_clock, cdclk;
> > + int crtc_clock, max_dotclk;
> >
> > if (!intel_crtc || !crtc_state->base.enable)
> > return DRM_PLANE_HELPER_NO_SCALING;
> >
> > + dev_priv = to_i915(intel_crtc->base.dev);
> > +
> > crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
> > - cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
> > + max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
>
> I actually meant using dev_priv->max_dotclock (or whatever it was
> called). But now that I actually read the code I see that it wouldn't
> work. So this looks fine
There were a few missing words in that reply. ;-)
We could do a max_dotclock_for_cdclk() kind of thing or just track the max
dotclock with the cdclk, but I'm not sure if it improves the situation much.
Ander
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> > +
> > + if (IS_GEMINILAKE(dev_priv))
> > + max_dotclk *= 2;
> >
> > - if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
> > + if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
> > return DRM_PLANE_HELPER_NO_SCALING;
> >
> > /*
> > @@ -13229,7 +13235,8 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state
> > * or
> > * cdclk/crtc_clock
> > */
> > - max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
> > + max_scale = min((1 << 16) * 3 - 1,
> > + (1 << 8) * ((max_dotclk << 8) / crtc_clock));
> >
> > return max_scale;
> > }
> > --
> > 2.9.3
>
>
_______________________________________________
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 3/4] drm/i915/glk: Pass dev_priv to intel_atomic_setup_scalers()
2017-02-23 7:15 [PATCH v2 0/4] GLK plane/scaling fixes Ander Conselvan de Oliveira
2017-02-23 7:15 ` [PATCH v2 1/4] drm/i915/glk: Fix watermark computations for third sprite plane Ander Conselvan de Oliveira
2017-02-23 7:15 ` [PATCH v2 2/4] drm/i915/glk: Fix maximum scaling factor for Geminilake scalers Ander Conselvan de Oliveira
@ 2017-02-23 7:15 ` Ander Conselvan de Oliveira
2017-02-23 11:24 ` Ville Syrjälä
2017-02-23 7:16 ` [PATCH v2 4/4] drm/i915/glk: Fix Geminilake scalers mode programming Ander Conselvan de Oliveira
2017-02-23 7:52 ` ✓ Fi.CI.BAT: success for GLK plane/scaling fixes (rev2) Patchwork
4 siblings, 1 reply; 14+ messages in thread
From: Ander Conselvan de Oliveira @ 2017-02-23 7:15 UTC (permalink / raw)
To: intel-gfx, Ville Syrjälä; +Cc: Ander Conselvan de Oliveira
Pass dev_priv to intel_atomic_setup_scalers(). The next patch will need
a dev_priv pointer.
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/intel_atomic.c | 10 +++++-----
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 6 +++---
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index aa9160e..58916e3 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -121,7 +121,7 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
/**
* intel_atomic_setup_scalers() - setup scalers for crtc per staged requests
- * @dev: DRM device
+ * @dev_priv: i915 device
* @crtc: intel crtc
* @crtc_state: incoming crtc_state to validate and setup scalers
*
@@ -136,9 +136,9 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
* 0 - scalers were setup succesfully
* error code - otherwise
*/
-int intel_atomic_setup_scalers(struct drm_device *dev,
- struct intel_crtc *intel_crtc,
- struct intel_crtc_state *crtc_state)
+int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
+ struct intel_crtc *intel_crtc,
+ struct intel_crtc_state *crtc_state)
{
struct drm_plane *plane = NULL;
struct intel_plane *intel_plane;
@@ -199,7 +199,7 @@ int intel_atomic_setup_scalers(struct drm_device *dev,
*/
if (!plane) {
struct drm_plane_state *state;
- plane = drm_plane_from_index(dev, i);
+ plane = drm_plane_from_index(&dev_priv->drm, i);
state = drm_atomic_get_plane_state(drm_state, plane);
if (IS_ERR(state)) {
DRM_DEBUG_KMS("Failed to add [PLANE:%d] to drm_state\n",
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6b65adf..606fff5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10959,7 +10959,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
ret = skl_update_scaler_crtc(pipe_config);
if (!ret)
- ret = intel_atomic_setup_scalers(dev, intel_crtc,
+ ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
pipe_config);
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0edc499..d9d96d6 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1910,9 +1910,9 @@ intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
return to_intel_plane_state(plane_state);
}
-int intel_atomic_setup_scalers(struct drm_device *dev,
- struct intel_crtc *intel_crtc,
- struct intel_crtc_state *crtc_state);
+int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
+ struct intel_crtc *intel_crtc,
+ struct intel_crtc_state *crtc_state);
/* intel_atomic_plane.c */
struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
--
2.9.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v2 3/4] drm/i915/glk: Pass dev_priv to intel_atomic_setup_scalers()
2017-02-23 7:15 ` [PATCH v2 3/4] drm/i915/glk: Pass dev_priv to intel_atomic_setup_scalers() Ander Conselvan de Oliveira
@ 2017-02-23 11:24 ` Ville Syrjälä
0 siblings, 0 replies; 14+ messages in thread
From: Ville Syrjälä @ 2017-02-23 11:24 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx
On Thu, Feb 23, 2017 at 09:15:59AM +0200, Ander Conselvan de Oliveira wrote:
> Pass dev_priv to intel_atomic_setup_scalers(). The next patch will need
> a dev_priv pointer.
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_atomic.c | 10 +++++-----
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> drivers/gpu/drm/i915/intel_drv.h | 6 +++---
> 3 files changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
> index aa9160e..58916e3 100644
> --- a/drivers/gpu/drm/i915/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> @@ -121,7 +121,7 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
>
> /**
> * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests
> - * @dev: DRM device
> + * @dev_priv: i915 device
> * @crtc: intel crtc
> * @crtc_state: incoming crtc_state to validate and setup scalers
> *
> @@ -136,9 +136,9 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
> * 0 - scalers were setup succesfully
> * error code - otherwise
> */
> -int intel_atomic_setup_scalers(struct drm_device *dev,
> - struct intel_crtc *intel_crtc,
> - struct intel_crtc_state *crtc_state)
> +int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
> + struct intel_crtc *intel_crtc,
> + struct intel_crtc_state *crtc_state)
> {
> struct drm_plane *plane = NULL;
> struct intel_plane *intel_plane;
> @@ -199,7 +199,7 @@ int intel_atomic_setup_scalers(struct drm_device *dev,
> */
> if (!plane) {
> struct drm_plane_state *state;
> - plane = drm_plane_from_index(dev, i);
> + plane = drm_plane_from_index(&dev_priv->drm, i);
> state = drm_atomic_get_plane_state(drm_state, plane);
> if (IS_ERR(state)) {
> DRM_DEBUG_KMS("Failed to add [PLANE:%d] to drm_state\n",
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 6b65adf..606fff5 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10959,7 +10959,7 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
> ret = skl_update_scaler_crtc(pipe_config);
>
> if (!ret)
> - ret = intel_atomic_setup_scalers(dev, intel_crtc,
> + ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
> pipe_config);
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 0edc499..d9d96d6 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1910,9 +1910,9 @@ intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
> return to_intel_plane_state(plane_state);
> }
>
> -int intel_atomic_setup_scalers(struct drm_device *dev,
> - struct intel_crtc *intel_crtc,
> - struct intel_crtc_state *crtc_state);
> +int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
> + struct intel_crtc *intel_crtc,
> + struct intel_crtc_state *crtc_state);
>
> /* intel_atomic_plane.c */
> struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
> --
> 2.9.3
--
Ville Syrjälä
Intel OTC
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v2 4/4] drm/i915/glk: Fix Geminilake scalers mode programming
2017-02-23 7:15 [PATCH v2 0/4] GLK plane/scaling fixes Ander Conselvan de Oliveira
` (2 preceding siblings ...)
2017-02-23 7:15 ` [PATCH v2 3/4] drm/i915/glk: Pass dev_priv to intel_atomic_setup_scalers() Ander Conselvan de Oliveira
@ 2017-02-23 7:16 ` Ander Conselvan de Oliveira
2017-02-23 11:30 ` Ville Syrjälä
2017-02-23 7:52 ` ✓ Fi.CI.BAT: success for GLK plane/scaling fixes (rev2) Patchwork
4 siblings, 1 reply; 14+ messages in thread
From: Ander Conselvan de Oliveira @ 2017-02-23 7:16 UTC (permalink / raw)
To: intel-gfx, Ville Syrjälä; +Cc: Ander Conselvan de Oliveira
Geminilake scalers can do 7x7 filtering for all supported input sizes,
so it doesn't need the "high quality" mode programming, which was
actually removed from that platform.
v2: Split dev_priv parameter change out. (Ville)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>,
Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
---
drivers/gpu/drm/i915/intel_atomic.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index 58916e3..e65818e 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -247,7 +247,9 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
}
/* set scaler mode */
- if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) {
+ if (IS_GEMINILAKE(dev_priv)) {
+ scaler_state->scalers[*scaler_id].mode = 0;
+ } else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) {
/*
* when only 1 scaler is in use on either pipe A or B,
* scaler 0 operates in high quality (HQ) mode.
--
2.9.3
_______________________________________________
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^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v2 4/4] drm/i915/glk: Fix Geminilake scalers mode programming
2017-02-23 7:16 ` [PATCH v2 4/4] drm/i915/glk: Fix Geminilake scalers mode programming Ander Conselvan de Oliveira
@ 2017-02-23 11:30 ` Ville Syrjälä
0 siblings, 0 replies; 14+ messages in thread
From: Ville Syrjälä @ 2017-02-23 11:30 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx
On Thu, Feb 23, 2017 at 09:16:00AM +0200, Ander Conselvan de Oliveira wrote:
> Geminilake scalers can do 7x7 filtering for all supported input sizes,
> so it doesn't need the "high quality" mode programming, which was
> actually removed from that platform.
>
> v2: Split dev_priv parameter change out. (Ville)
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>,
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_atomic.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
> index 58916e3..e65818e 100644
> --- a/drivers/gpu/drm/i915/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> @@ -247,7 +247,9 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
> }
>
> /* set scaler mode */
> - if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) {
> + if (IS_GEMINILAKE(dev_priv)) {
> + scaler_state->scalers[*scaler_id].mode = 0;
> + } else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) {
> /*
> * when only 1 scaler is in use on either pipe A or B,
> * scaler 0 operates in high quality (HQ) mode.
> --
> 2.9.3
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ Fi.CI.BAT: success for GLK plane/scaling fixes (rev2)
2017-02-23 7:15 [PATCH v2 0/4] GLK plane/scaling fixes Ander Conselvan de Oliveira
` (3 preceding siblings ...)
2017-02-23 7:16 ` [PATCH v2 4/4] drm/i915/glk: Fix Geminilake scalers mode programming Ander Conselvan de Oliveira
@ 2017-02-23 7:52 ` Patchwork
2017-02-23 13:25 ` Ander Conselvan De Oliveira
4 siblings, 1 reply; 14+ messages in thread
From: Patchwork @ 2017-02-23 7:52 UTC (permalink / raw)
To: Ander Conselvan de Oliveira; +Cc: intel-gfx
== Series Details ==
Series: GLK plane/scaling fixes (rev2)
URL : https://patchwork.freedesktop.org/series/20051/
State : success
== Summary ==
Series 20051v2 GLK plane/scaling fixes
https://patchwork.freedesktop.org/api/1.0/series/20051/revisions/2/mbox/
fi-bdw-5557u total:253 pass:242 dwarn:0 dfail:0 fail:0 skip:11
fi-bsw-n3050 total:253 pass:214 dwarn:0 dfail:0 fail:0 skip:39
fi-bxt-j4205 total:253 pass:234 dwarn:0 dfail:0 fail:0 skip:19
fi-bxt-t5700 total:83 pass:70 dwarn:0 dfail:0 fail:0 skip:12
fi-byt-j1900 total:253 pass:226 dwarn:0 dfail:0 fail:0 skip:27
fi-hsw-4770 total:253 pass:237 dwarn:0 dfail:0 fail:0 skip:16
fi-hsw-4770r total:253 pass:237 dwarn:0 dfail:0 fail:0 skip:16
fi-ilk-650 total:253 pass:203 dwarn:0 dfail:0 fail:0 skip:50
fi-ivb-3520m total:253 pass:235 dwarn:0 dfail:0 fail:0 skip:18
fi-ivb-3770 total:253 pass:235 dwarn:0 dfail:0 fail:0 skip:18
fi-kbl-7500u total:253 pass:235 dwarn:0 dfail:0 fail:0 skip:18
fi-skl-6260u total:253 pass:243 dwarn:0 dfail:0 fail:0 skip:10
fi-skl-6700hq total:253 pass:236 dwarn:0 dfail:0 fail:0 skip:17
fi-skl-6700k total:253 pass:231 dwarn:4 dfail:0 fail:0 skip:18
fi-skl-6770hq total:253 pass:243 dwarn:0 dfail:0 fail:0 skip:10
fi-snb-2520m total:253 pass:225 dwarn:0 dfail:0 fail:0 skip:28
fi-snb-2600 total:253 pass:224 dwarn:0 dfail:0 fail:0 skip:29
fi-byt-n2820 failed to collect. IGT log at Patchwork_3941/fi-byt-n2820/igt.log
bf89ec45d0822835b03910371ac0baf46c4efa2d drm-tip: 2017y-02m-22d-14h-30m-04s UTC integration manifest
2ab3ea2 drm/i915/glk: Fix Geminilake scalers mode programming
ec7e6c0 drm/i915/glk: Pass dev_priv to intel_atomic_setup_scalers()
5fe955a drm/i915/glk: Fix maximum scaling factor for Geminilake scalers
9d11448 drm/i915/glk: Fix watermark computations for third sprite plane
== Logs ==
For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3941/
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^ permalink raw reply [flat|nested] 14+ messages in thread* Re: ✓ Fi.CI.BAT: success for GLK plane/scaling fixes (rev2)
2017-02-23 7:52 ` ✓ Fi.CI.BAT: success for GLK plane/scaling fixes (rev2) Patchwork
@ 2017-02-23 13:25 ` Ander Conselvan De Oliveira
0 siblings, 0 replies; 14+ messages in thread
From: Ander Conselvan De Oliveira @ 2017-02-23 13:25 UTC (permalink / raw)
To: intel-gfx, Ville Syrjälä
On Thu, 2017-02-23 at 07:52 +0000, Patchwork wrote:
> == Series Details ==
>
> Series: GLK plane/scaling fixes (rev2)
> URL : https://patchwork.freedesktop.org/series/20051/
> State : success
Pushed. Thanks for reviewing.
Ander
>
> == Summary ==
>
> Series 20051v2 GLK plane/scaling fixes
> https://patchwork.freedesktop.org/api/1.0/series/20051/revisions/2/mbox/
>
> fi-bdw-5557u total:253 pass:242 dwarn:0 dfail:0 fail:0 skip:11
> fi-bsw-n3050 total:253 pass:214 dwarn:0 dfail:0 fail:0 skip:39
> fi-bxt-j4205 total:253 pass:234 dwarn:0 dfail:0 fail:0 skip:19
> fi-bxt-t5700 total:83 pass:70 dwarn:0 dfail:0 fail:0 skip:12
> fi-byt-j1900 total:253 pass:226 dwarn:0 dfail:0 fail:0 skip:27
> fi-hsw-4770 total:253 pass:237 dwarn:0 dfail:0 fail:0 skip:16
> fi-hsw-4770r total:253 pass:237 dwarn:0 dfail:0 fail:0 skip:16
> fi-ilk-650 total:253 pass:203 dwarn:0 dfail:0 fail:0 skip:50
> fi-ivb-3520m total:253 pass:235 dwarn:0 dfail:0 fail:0 skip:18
> fi-ivb-3770 total:253 pass:235 dwarn:0 dfail:0 fail:0 skip:18
> fi-kbl-7500u total:253 pass:235 dwarn:0 dfail:0 fail:0 skip:18
> fi-skl-6260u total:253 pass:243 dwarn:0 dfail:0 fail:0 skip:10
> fi-skl-6700hq total:253 pass:236 dwarn:0 dfail:0 fail:0 skip:17
> fi-skl-6700k total:253 pass:231 dwarn:4 dfail:0 fail:0 skip:18
> fi-skl-6770hq total:253 pass:243 dwarn:0 dfail:0 fail:0 skip:10
> fi-snb-2520m total:253 pass:225 dwarn:0 dfail:0 fail:0 skip:28
> fi-snb-2600 total:253 pass:224 dwarn:0 dfail:0 fail:0 skip:29
> fi-byt-n2820 failed to collect. IGT log at Patchwork_3941/fi-byt-n2820/igt.log
>
> bf89ec45d0822835b03910371ac0baf46c4efa2d drm-tip: 2017y-02m-22d-14h-30m-04s UTC integration manifest
> 2ab3ea2 drm/i915/glk: Fix Geminilake scalers mode programming
> ec7e6c0 drm/i915/glk: Pass dev_priv to intel_atomic_setup_scalers()
> 5fe955a drm/i915/glk: Fix maximum scaling factor for Geminilake scalers
> 9d11448 drm/i915/glk: Fix watermark computations for third sprite plane
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_3941/
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 14+ messages in thread