From: Michel Thierry <michel.thierry@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH v9 14/21] drm/i915/guc: Rename the function that resets the GuC
Date: Thu, 15 Jun 2017 13:18:21 -0700 [thread overview]
Message-ID: <20170615201828.23144-15-michel.thierry@intel.com> (raw)
In-Reply-To: <20170615201828.23144-1-michel.thierry@intel.com>
intel_guc_reset sounds more like the microcontroller is the one performing
a reset, while in this case is the opposite. intel_reset_guc not only
makes it clearer, it follows the other intel_reset functions available.
v2: Print error message in English.
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_uc.c | 4 ++--
drivers/gpu/drm/i915/intel_uncore.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f68cfdf640f3..e657d56120d7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3104,7 +3104,7 @@ extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
extern void i915_reset(struct drm_i915_private *dev_priv);
extern int i915_reset_engine(struct intel_engine_cs *engine);
extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv);
-extern int intel_guc_reset(struct drm_i915_private *dev_priv);
+extern int intel_reset_guc(struct drm_i915_private *dev_priv);
extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 27e072cc96eb..a8930f2feacf 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -46,9 +46,9 @@ static int __intel_uc_reset_hw(struct drm_i915_private *dev_priv)
int ret;
u32 guc_status;
- ret = intel_guc_reset(dev_priv);
+ ret = intel_reset_guc(dev_priv);
if (ret) {
- DRM_ERROR("GuC reset failed, ret = %d\n", ret);
+ DRM_ERROR("Failed to reset GuC, ret = %d\n", ret);
return ret;
}
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index b99b7c69a525..713a88cebf57 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1734,7 +1734,7 @@ bool intel_has_reset_engine(struct drm_i915_private *dev_priv)
i915.reset >= 2);
}
-int intel_guc_reset(struct drm_i915_private *dev_priv)
+int intel_reset_guc(struct drm_i915_private *dev_priv)
{
int ret;
--
2.11.0
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next prev parent reply other threads:[~2017-06-15 20:18 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-15 20:18 [PATCH v9 00/21] Gen8+ engine-reset Michel Thierry
2017-06-15 20:18 ` [PATCH v9 01/21] drm/i915: Look for active requests earlier in the reset path Michel Thierry
2017-06-15 20:18 ` [PATCH v9 02/21] drm/i915: Update i915.reset to handle engine resets Michel Thierry
2017-06-15 20:18 ` [PATCH v9 03/21] drm/i915: Modify error handler for per engine hang recovery Michel Thierry
2017-06-15 20:18 ` [PATCH v9 04/21] drm/i915: Include reset engine information in has_gpu_reset getparam Michel Thierry
2017-06-15 20:18 ` [PATCH v9 05/21] drm/i915: Add support for per engine reset recovery Michel Thierry
2017-06-19 12:31 ` Chris Wilson
2017-06-19 12:46 ` Chris Wilson
2017-06-19 18:42 ` Michel Thierry
2017-06-15 20:18 ` [PATCH v9 06/21] drm/i915: Add engine reset count to error state Michel Thierry
2017-06-15 20:18 ` [PATCH v9 07/21] drm/i915: Export per-engine reset count info to debugfs Michel Thierry
2017-06-15 20:18 ` [PATCH v9 RFC 08/21] drm/i915: Carry on with reset even if hw engine is not ready Michel Thierry
2017-06-15 20:18 ` [PATCH v9 09/21] drm/i915: Enable Engine reset and recovery support Michel Thierry
2017-06-15 20:18 ` [PATCH v9 10/21] drm/i915: Add engine reset count in get-reset-stats ioctl Michel Thierry
2017-06-15 21:14 ` Chris Wilson
2017-06-15 21:23 ` Michel Thierry
2017-06-15 20:18 ` [PATCH v9 11/21] drm/i915/selftests: reset engine self tests Michel Thierry
2017-06-15 20:18 ` [PATCH v9 12/21] drm/i915/guc: fix mmio whitelist mmio_start offset and add reminder Michel Thierry
2017-06-15 20:18 ` [PATCH v9 13/21] drm/i915/guc: Provide register list to be saved/restored during engine reset Michel Thierry
2017-06-15 20:18 ` Michel Thierry [this message]
2017-06-15 20:18 ` [PATCH v9 15/21] drm/i915/guc: Add support for reset engine using GuC commands Michel Thierry
2017-06-15 20:18 ` [PATCH v9 16/21] drm/i915: Watchdog timeout: Pass GuC shared data structure during param load Michel Thierry
2017-06-15 20:18 ` [PATCH v9 17/21] drm/i915: Watchdog timeout: IRQ handler for gen8+ Michel Thierry
2017-06-15 20:18 ` [PATCH v9 18/21] drm/i915: Watchdog timeout: Ringbuffer command emission " Michel Thierry
2017-06-15 20:18 ` [PATCH v9 19/21] drm/i915: Watchdog timeout: DRM kernel interface to set the timeout Michel Thierry
2017-06-15 20:18 ` [PATCH v9 20/21] drm/i915: Watchdog timeout: Include threshold value in error state Michel Thierry
2017-06-15 20:18 ` [PATCH v9 21/21] drm/i915: Watchdog timeout: Export media reset count from GuC to debugfs Michel Thierry
2017-06-15 20:42 ` ✓ Fi.CI.BAT: success for Gen8+ engine-reset (rev13) Patchwork
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