* [PATCH] drm/i915: Avoid setting redundant INIT power domain mask for DC_OFF wells
@ 2017-12-12 21:52 Dhinakaran Pandiyan
2017-12-12 22:20 ` ✓ Fi.CI.BAT: success for " Patchwork
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Dhinakaran Pandiyan @ 2017-12-12 21:52 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan
The POWER_DOMAIN_INIT bit is already set in _POWERWELL_2_POWER_DOMAINS,
which is included in _DC_OFF_POWER_DOMAINS. So, avoid setting that again
in _DC_OFF_POWER_DOMAINS and shuffle the macros a bit to make it easy to
notice relation.
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 20 ++++++++------------
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 96ab74f3d101..eb4b12989c84 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1706,11 +1706,10 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
BIT_ULL(POWER_DOMAIN_MODESET) | \
BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+ SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS)
#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
@@ -1728,12 +1727,6 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_GMBUS) | \
BIT_ULL(POWER_DOMAIN_INIT))
-#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
#define BXT_DPIO_CMN_A_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
BIT_ULL(POWER_DOMAIN_AUX_A) | \
@@ -1744,6 +1737,11 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_AUX_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
+#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)
#define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
@@ -1788,11 +1786,10 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
BIT_ULL(POWER_DOMAIN_AUX_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
BIT_ULL(POWER_DOMAIN_MODESET) | \
BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+ GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS)
#define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
@@ -1836,10 +1833,9 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
BIT_ULL(POWER_DOMAIN_AUX_D) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_MODESET) | \
BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+ CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS)
static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
--
2.11.0
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread* ✓ Fi.CI.BAT: success for drm/i915: Avoid setting redundant INIT power domain mask for DC_OFF wells
2017-12-12 21:52 [PATCH] drm/i915: Avoid setting redundant INIT power domain mask for DC_OFF wells Dhinakaran Pandiyan
@ 2017-12-12 22:20 ` Patchwork
2017-12-12 23:24 ` ✓ Fi.CI.IGT: " Patchwork
2017-12-19 22:01 ` [PATCH] " Rodrigo Vivi
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2017-12-12 22:20 UTC (permalink / raw)
To: Dhinakaran Pandiyan; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Avoid setting redundant INIT power domain mask for DC_OFF wells
URL : https://patchwork.freedesktop.org/series/35252/
State : success
== Summary ==
Series 35252v1 drm/i915: Avoid setting redundant INIT power domain mask for DC_OFF wells
https://patchwork.freedesktop.org/api/1.0/series/35252/revisions/1/mbox/
Test gem_mmap_gtt:
Subgroup basic-small-bo-tiledx:
pass -> FAIL (fi-gdg-551) fdo#102575
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-a:
pass -> DMESG-WARN (fi-kbl-r) fdo#104172 +1
Subgroup suspend-read-crc-pipe-b:
pass -> INCOMPLETE (fi-snb-2520m) fdo#103713
fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575
fdo#104172 https://bugs.freedesktop.org/show_bug.cgi?id=104172
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:439s
fi-bdw-gvtdvm total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:441s
fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:382s
fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:503s
fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:280s
fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:503s
fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:508s
fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:488s
fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:474s
fi-elk-e7500 total:224 pass:163 dwarn:15 dfail:0 fail:0 skip:45
fi-gdg-551 total:288 pass:178 dwarn:1 dfail:0 fail:1 skip:108 time:268s
fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:535s
fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:367s
fi-hsw-4770r total:288 pass:224 dwarn:0 dfail:0 fail:0 skip:64 time:262s
fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:395s
fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:477s
fi-ivb-3770 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:448s
fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:486s
fi-kbl-7560u total:288 pass:269 dwarn:0 dfail:0 fail:0 skip:19 time:526s
fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:471s
fi-kbl-r total:288 pass:260 dwarn:1 dfail:0 fail:0 skip:27 time:530s
fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:588s
fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:456s
fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:538s
fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:563s
fi-skl-6700k total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:518s
fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:495s
fi-skl-gvtdvm total:288 pass:265 dwarn:0 dfail:0 fail:0 skip:23 time:449s
fi-snb-2520m total:245 pass:211 dwarn:0 dfail:0 fail:0 skip:33
fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:409s
Blacklisted hosts:
fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:590s
fi-glk-dsi total:169 pass:155 dwarn:0 dfail:0 fail:0 skip:13
8874c0f95698c533c0daf69c6c41834d837fef87 drm-tip: 2017y-12m-12d-21h-34m-33s UTC integration manifest
14862654fb6a drm/i915: Avoid setting redundant INIT power domain mask for DC_OFF wells
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7476/issues.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread* ✓ Fi.CI.IGT: success for drm/i915: Avoid setting redundant INIT power domain mask for DC_OFF wells
2017-12-12 21:52 [PATCH] drm/i915: Avoid setting redundant INIT power domain mask for DC_OFF wells Dhinakaran Pandiyan
2017-12-12 22:20 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2017-12-12 23:24 ` Patchwork
2017-12-19 22:01 ` [PATCH] " Rodrigo Vivi
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2017-12-12 23:24 UTC (permalink / raw)
To: Dhinakaran Pandiyan; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Avoid setting redundant INIT power domain mask for DC_OFF wells
URL : https://patchwork.freedesktop.org/series/35252/
State : success
== Summary ==
Test kms_frontbuffer_tracking:
Subgroup fbc-1p-offscren-pri-shrfb-draw-render:
pass -> FAIL (shard-snb) fdo#101623
Test pm_rpm:
Subgroup system-suspend:
pass -> SKIP (shard-hsw) fdo#103375
Test gem_tiled_swapping:
Subgroup non-threaded:
pass -> INCOMPLETE (shard-hsw) fdo#104218
Test kms_plane:
Subgroup plane-panning-bottom-right-suspend-pipe-a-planes:
pass -> SKIP (shard-hsw) fdo#103540
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
shard-hsw total:2681 pass:1516 dwarn:1 dfail:0 fail:10 skip:1153 time:9094s
shard-snb total:2681 pass:1290 dwarn:1 dfail:0 fail:12 skip:1377 time:7760s
Blacklisted hosts:
shard-apl total:2712 pass:1688 dwarn:1 dfail:0 fail:22 skip:1001 time:13876s
shard-kbl total:2656 pass:1762 dwarn:10 dfail:0 fail:22 skip:861 time:10793s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7476/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] drm/i915: Avoid setting redundant INIT power domain mask for DC_OFF wells
2017-12-12 21:52 [PATCH] drm/i915: Avoid setting redundant INIT power domain mask for DC_OFF wells Dhinakaran Pandiyan
2017-12-12 22:20 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-12-12 23:24 ` ✓ Fi.CI.IGT: " Patchwork
@ 2017-12-19 22:01 ` Rodrigo Vivi
2017-12-19 23:25 ` Pandiyan, Dhinakaran
2 siblings, 1 reply; 5+ messages in thread
From: Rodrigo Vivi @ 2017-12-19 22:01 UTC (permalink / raw)
To: Dhinakaran Pandiyan; +Cc: intel-gfx
On Tue, Dec 12, 2017 at 09:52:09PM +0000, Dhinakaran Pandiyan wrote:
> The POWER_DOMAIN_INIT bit is already set in _POWERWELL_2_POWER_DOMAINS,
> which is included in _DC_OFF_POWER_DOMAINS. So, avoid setting that again
> in _DC_OFF_POWER_DOMAINS and shuffle the macros a bit to make it easy to
> notice relation.
>
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 20 ++++++++------------
> 1 file changed, 8 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 96ab74f3d101..eb4b12989c84 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -1706,11 +1706,10 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> - SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
> BIT_ULL(POWER_DOMAIN_MODESET) | \
> BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> + SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS)
>
> #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> @@ -1728,12 +1727,6 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> BIT_ULL(POWER_DOMAIN_VGA) | \
> BIT_ULL(POWER_DOMAIN_GMBUS) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> -#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> - BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
> - BIT_ULL(POWER_DOMAIN_MODESET) | \
> - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> #define BXT_DPIO_CMN_A_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
> BIT_ULL(POWER_DOMAIN_AUX_A) | \
> @@ -1744,6 +1737,11 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> BIT_ULL(POWER_DOMAIN_AUX_B) | \
> BIT_ULL(POWER_DOMAIN_AUX_C) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> +#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
> + BIT_ULL(POWER_DOMAIN_MODESET) | \
> + BIT_ULL(POWER_DOMAIN_AUX_A) | \
> + BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)
why did you move the entire block below?
>
> #define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> @@ -1788,11 +1786,10 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> BIT_ULL(POWER_DOMAIN_AUX_C) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> #define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> - GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
> BIT_ULL(POWER_DOMAIN_MODESET) | \
> BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> + GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS)
>
> #define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> @@ -1836,10 +1833,9 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> BIT_ULL(POWER_DOMAIN_AUX_D) | \
> BIT_ULL(POWER_DOMAIN_INIT))
> #define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> - CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> BIT_ULL(POWER_DOMAIN_MODESET) | \
> BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> + CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS)
>
> static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
> .sync_hw = i9xx_power_well_sync_hw_noop,
> --
> 2.11.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] drm/i915: Avoid setting redundant INIT power domain mask for DC_OFF wells
2017-12-19 22:01 ` [PATCH] " Rodrigo Vivi
@ 2017-12-19 23:25 ` Pandiyan, Dhinakaran
0 siblings, 0 replies; 5+ messages in thread
From: Pandiyan, Dhinakaran @ 2017-12-19 23:25 UTC (permalink / raw)
To: Vivi, Rodrigo; +Cc: intel-gfx@lists.freedesktop.org
On Tue, 2017-12-19 at 14:01 -0800, Rodrigo Vivi wrote:
> On Tue, Dec 12, 2017 at 09:52:09PM +0000, Dhinakaran Pandiyan wrote:
> > The POWER_DOMAIN_INIT bit is already set in _POWERWELL_2_POWER_DOMAINS,
> > which is included in _DC_OFF_POWER_DOMAINS. So, avoid setting that again
> > in _DC_OFF_POWER_DOMAINS and shuffle the macros a bit to make it easy to
> > notice relation.
> >
> > Cc: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 20 ++++++++------------
> > 1 file changed, 8 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index 96ab74f3d101..eb4b12989c84 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -1706,11 +1706,10 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> > BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \
> > BIT_ULL(POWER_DOMAIN_INIT))
> > #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> > - SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> > BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
> > BIT_ULL(POWER_DOMAIN_MODESET) | \
> > BIT_ULL(POWER_DOMAIN_AUX_A) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > + SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS)
> >
> > #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> > BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> > @@ -1728,12 +1727,6 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> > BIT_ULL(POWER_DOMAIN_VGA) | \
> > BIT_ULL(POWER_DOMAIN_GMBUS) | \
> > BIT_ULL(POWER_DOMAIN_INIT))
> > -#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> > - BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> > - BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
> > - BIT_ULL(POWER_DOMAIN_MODESET) | \
> > - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > #define BXT_DPIO_CMN_A_POWER_DOMAINS ( \
> > BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
> > BIT_ULL(POWER_DOMAIN_AUX_A) | \
> > @@ -1744,6 +1737,11 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> > BIT_ULL(POWER_DOMAIN_AUX_B) | \
> > BIT_ULL(POWER_DOMAIN_AUX_C) | \
> > BIT_ULL(POWER_DOMAIN_INIT))
> > +#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> > + BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
> > + BIT_ULL(POWER_DOMAIN_MODESET) | \
> > + BIT_ULL(POWER_DOMAIN_AUX_A) | \
> > + BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)
>
> why did you move the entire block below?
>
Because the DC_OFF domain is at the bottom for every other platform :)
> >
> > #define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> > BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> > @@ -1788,11 +1786,10 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> > BIT_ULL(POWER_DOMAIN_AUX_C) | \
> > BIT_ULL(POWER_DOMAIN_INIT))
> > #define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> > - GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> > BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
> > BIT_ULL(POWER_DOMAIN_MODESET) | \
> > BIT_ULL(POWER_DOMAIN_AUX_A) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > + GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS)
> >
> > #define CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> > BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> > @@ -1836,10 +1833,9 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> > BIT_ULL(POWER_DOMAIN_AUX_D) | \
> > BIT_ULL(POWER_DOMAIN_INIT))
> > #define CNL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> > - CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> > BIT_ULL(POWER_DOMAIN_MODESET) | \
> > BIT_ULL(POWER_DOMAIN_AUX_A) | \
> > - BIT_ULL(POWER_DOMAIN_INIT))
> > + CNL_DISPLAY_POWERWELL_2_POWER_DOMAINS)
> >
> > static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
> > .sync_hw = i9xx_power_well_sync_hw_noop,
> > --
> > 2.11.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2017-12-19 23:25 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-12-12 21:52 [PATCH] drm/i915: Avoid setting redundant INIT power domain mask for DC_OFF wells Dhinakaran Pandiyan
2017-12-12 22:20 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-12-12 23:24 ` ✓ Fi.CI.IGT: " Patchwork
2017-12-19 22:01 ` [PATCH] " Rodrigo Vivi
2017-12-19 23:25 ` Pandiyan, Dhinakaran
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