From: Mahesh Kumar <mahesh1.kumar@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 2/3] drm/i915/cnl; Add macro to get PORT_TX register
Date: Thu, 15 Feb 2018 15:26:42 +0530 [thread overview]
Message-ID: <20180215095643.3844-3-mahesh1.kumar@intel.com> (raw)
In-Reply-To: <20180215095643.3844-1-mahesh1.kumar@intel.com>
This patch creates a new macro to get PORT_TX register for any given DW.
This will remove the need of defining register address for each port & DW.
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1412abcb27d4..ef339f21f2a3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1961,6 +1961,34 @@ enum i915_power_well_id {
_CNL_PORT_PCS_DW1_LN0_F)
#define COMMON_KEEPER_EN (1 << 26)
+/* CNL Port TX registers */
+#define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340
+#define _CNL_PORT_TX_B_GRP_OFFSET 0x1623C0
+#define _CNL_PORT_TX_C_GRP_OFFSET 0x162B40
+#define _CNL_PORT_TX_D_GRP_OFFSET 0x162BC0
+#define _CNL_PORT_TX_F_GRP_OFFSET 0x162A40
+#define _CNL_PORT_TX_AE_LN0_OFFSET 0x162440
+#define _CNL_PORT_TX_B_LN0_OFFSET 0x162640
+#define _CNL_PORT_TX_C_LN0_OFFSET 0x162C40
+#define _CNL_PORT_TX_D_LN0_OFFSET 0x162E40
+#define _CNL_PORT_TX_F_LN0_OFFSET 0x162840
+#define CNL_PORT_TX_DW_GRP(port, dw) (_PICK((port), \
+ _CNL_PORT_TX_AE_GRP_OFFSET, \
+ _CNL_PORT_TX_B_GRP_OFFSET, \
+ _CNL_PORT_TX_B_GRP_OFFSET, \
+ _CNL_PORT_TX_D_GRP_OFFSET, \
+ _CNL_PORT_TX_AE_GRP_OFFSET, \
+ _CNL_PORT_TX_F_GRP_OFFSET) + \
+ 4*(dw))
+#define CNL_PORT_TX_DW_LN0(port, dw) (_PICK((port), \
+ _CNL_PORT_TX_AE_LN0_OFFSET, \
+ _CNL_PORT_TX_B_LN0_OFFSET, \
+ _CNL_PORT_TX_B_LN0_OFFSET, \
+ _CNL_PORT_TX_D_LN0_OFFSET, \
+ _CNL_PORT_TX_AE_LN0_OFFSET, \
+ _CNL_PORT_TX_F_LN0_OFFSET) + \
+ 4*(dw))
+
#define _CNL_PORT_TX_DW2_GRP_AE 0x162348
#define _CNL_PORT_TX_DW2_GRP_B 0x1623C8
#define _CNL_PORT_TX_DW2_GRP_C 0x162B48
--
2.14.1
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next prev parent reply other threads:[~2018-02-15 9:56 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-15 9:56 [PATCH 0/3] CNL port refactoring Mahesh Kumar
2018-02-15 9:56 ` [PATCH 1/3] drm/i915/cnl: Fix PORT_TX_DW5/7 register address Mahesh Kumar
2018-02-15 14:02 ` Jani Nikula
2018-02-15 23:43 ` Rodrigo Vivi
2018-02-16 17:57 ` Rodrigo Vivi
2018-02-15 9:56 ` Mahesh Kumar [this message]
2018-02-15 9:56 ` [PATCH 3/3] drm/i915/cnl: Replace PORT_TX register macros with new ones Mahesh Kumar
2018-02-15 10:01 ` ✗ Fi.CI.CHECKPATCH: warning for CNL port refactoring Patchwork
2018-02-15 10:16 ` ✓ Fi.CI.BAT: success " Patchwork
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