[PATCH 00/10] Enabling VDSC in i915 driver for GLK

[PATCH 00/10] Enabling VDSC in i915 driver for GLK

[Gaurav K Singh]

Display  manufacturers are turning to higher-resolution displays
to differentiate their products. The increased pixel counts have
required increased bandwidth over the links that drive these displays.
However, advances in physical layer technology have not kept up 
with the increases in pixel counts.

These factors have created a need for compression on display links.
The Video Electronics Standards Association(VESA),in liaison with the
MIPI Alliance, has developed an industry standard Display Stream Compression(DSC)
for interoperable, visually lossless compression over display links.

These patches enable VDSC in i915 gfx driver for Gen9,Gen10 platforms
and provide basic code for future platforms.

Testing:
Did testing on GLK RVP. By default GLK RVP has non-DSC EDP panel, there was no regression with these patches.

BA Chrome Team (OTC) do not have EDP panel which supports DSC.
Trying to arrrage DSC EDP panel from other teams in BA, hopeful to get it in few weeks.

Dropping the patches to get the review started.

Gaurav K Singh (10):
  drm: i915: Defining Compression Capabilities
  drm: i915: Get DSC capability from DP sink
  drm: i915: Enable/Disable DSC in DP sink
  drm: i915: Compute RC & DSC parameters
  drm: i915: Define Picture Parameter Set
  drm/i915: Populate PPS Secondary Data Pkt for Sink
  drm: i915: Define VDSC regs and DSC params
  drm: i915: Enable VDSC in Source
  drm: i915: Disable VDSC from Source
  drm/i915: Encoder enable/disable seq wrt DSC

 drivers/gpu/drm/i915/Makefile        |    1 +
 drivers/gpu/drm/i915/i915_drv.h      |  589 ++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h      |  451 ++++++++++++
 drivers/gpu/drm/i915/intel_ddi.c     |    4 +
 drivers/gpu/drm/i915/intel_display.c |   20 +
 drivers/gpu/drm/i915/intel_dp.c      |  182 +++++
 drivers/gpu/drm/i915/intel_drv.h     |   64 ++
 drivers/gpu/drm/i915/intel_vdsc.c    | 1243 ++++++++++++++++++++++++++++++++++
 include/drm/drm_dp_helper.h          |    3 +
 9 files changed, 2557 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c

-- 
1.9.1

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[PATCH 01/10] drm: i915: Defining Compression Capabilities

[Gaurav K Singh]

For Vesa Display Stream compression, defining structures for
compression capabilities to be stored in encoder.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h  | 125 +++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h |  62 +++++++++++++++++++
 include/drm/drm_dp_helper.h      |   1 +
 3 files changed, 188 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0d8cb74e7d02..4b1c323c0925 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -780,6 +780,131 @@ struct i915_psr {
 	void (*setup_vsc)(struct intel_dp *, const struct intel_crtc_state *);
 };
 
+/* DSC Configuration structure */
+#define NUM_BUF_RANGES		15
+
+/* Configuration for a single Rate Control model range */
+struct rc_range_parameters {
+	/* Min Quantization Parameters allowed for this range */
+	unsigned long range_min_qp;
+	/* Max Quantization Parameters allowed for this range */
+	unsigned long range_max_qp;
+	/* Bits/group offset to apply to target for this group */
+	unsigned long range_bpg_offset;
+};
+
+struct vdsc_config {
+	/* Bits / component for previous reconstructed line buffer */
+	unsigned long line_buf_depth;
+	/*
+	 * Rate control buffer size (in bits); not in PPS,
+	 * used only in C model for checking overflow
+	 */
+	unsigned long rc_bits;
+	/* Bits per component to code (must be 8, 10, or 12) */
+	unsigned long bits_per_component;
+	/*
+	 * Flag indicating to do RGB - YCoCg conversion
+	 * and back (should be 1 for RGB input)
+	 */
+	bool convert_rgb;
+	unsigned long slice_count;
+	/* Slice Width */
+	unsigned long slice_width;
+	/* Slice Height */
+	unsigned long slice_height;
+	/*
+	 * 4:2:2 enable mode (from PPS, 4:2:2 conversion happens
+	 * outside of DSC encode/decode algorithm)
+	 */
+	bool enable422;
+	/* Picture Width */
+	unsigned long pic_width;
+	/* Picture Height */
+	unsigned long pic_height;
+	/* Offset to bits/group used by RC to determine QP adjustment */
+	unsigned long rc_tgt_offset_high;
+	/* Offset to bits/group used by RC to determine QP adjustment */
+	unsigned long rc_tgt_offset_low;
+	/* Bits/pixel target << 4 (ie., 4 fractional bits) */
+	unsigned long bits_per_pixel;
+	/*
+	 * Factor to determine if an edge is present based
+	 * on the bits produced
+	 */
+	unsigned long rc_edge_factor;
+	/* Slow down incrementing once the range reaches this value */
+	unsigned long rc_quant_incr_limit1;
+	/* Slow down incrementing once the range reaches this value */
+	unsigned long rc_quant_incr_limit0;
+	/* Number of pixels to delay the initial transmission */
+	unsigned long initial_xmit_delay;
+	/* Number of pixels to delay the VLD on the decoder,not including SSM */
+	unsigned long  initial_dec_delay;
+	/* Block prediction range (in pixels) */
+	bool block_pred_enable;
+	/* Bits/group offset to use for first line of the slice */
+	unsigned long first_line_bpg_Ofs;
+	/* Value to use for RC model offset at slice start */
+	unsigned long initial_offset;
+	/* X position in the picture of top-left corner of slice */
+	unsigned long x_start;
+	/* Y position in the picture of top-left corner of slice */
+	unsigned long y_start;
+	/* Thresholds defining each of the buffer ranges */
+	unsigned long rc_buf_thresh[NUM_BUF_RANGES - 1];
+	/* Parameters for each of the RC ranges */
+	struct rc_range_parameters rc_range_params[NUM_BUF_RANGES];
+	/* Total size of RC model */
+	unsigned long rc_model_size;
+	/* Minimum QP where flatness information is sent */
+	unsigned long flatness_minQp;
+	/* Maximum QP where flatness information is sent */
+	unsigned long flatness_maxQp;
+	/*
+	 * MAX-MIN for all components is required to
+	 * be <= this value for flatness to be used
+	 */
+	unsigned long flatness_det_thresh;
+	/* Initial value for scale factor */
+	unsigned long initial_scale_value;
+	/* Decrement scale factor every scale_decrement_interval groups */
+	unsigned long scale_decrement_interval;
+	/* Increment scale factor every scale_increment_interval groups */
+	unsigned long scale_increment_interval;
+	/* Non-first line BPG offset to use */
+	unsigned long nfl_bpg_offset;
+	/* BPG offset used to enforce slice bit */
+	unsigned long slice_bpg_offset;
+	/* Final RC linear transformation offset value */
+	unsigned long final_offset;
+	/* Enable on-off VBR (ie., disable stuffing bits) */
+	bool vbr_enable;
+	/* Mux word size (in bits) for SSM mode */
+	unsigned long mux_word_size;
+	/*
+	 * The (max) size in bytes of the "chunks" that are
+	 * used in slice multiplexing
+	 */
+	unsigned long chunk_size;
+	/* Placeholder for PPS identifier */
+	unsigned long pps_identifier;
+	/* DSC Minor Version */
+	unsigned long dsc_version_minor;
+	/* DSC Major version */
+	unsigned long dsc_version_major;
+	/* Number of VDSC engines */
+	unsigned long num_vdsc_instances;
+};
+
+/* Compression caps stored in encoder */
+struct i915_compression_params {
+	bool compression_support;
+	unsigned long compression_bpp;
+	struct vdsc_config dsc_cfg;
+	unsigned char slice_count;
+};
+
 enum intel_pch {
 	PCH_NONE = 0,	/* No PCH present */
 	PCH_IBX,	/* Ibexpeak PCH */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5853d92a6512..6e1b907990bf 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -954,6 +954,63 @@ struct intel_dp_compliance {
 	u8 test_lane_count;
 };
 
+/* Vesa Display Stream Capability of DP Sink */
+struct dp_sink_dsc_caps {
+	/* Display Stream Compression Support */
+	bool is_dsc_supported;
+	u8 dsc_major_ver;
+	u8 dsc_minor_ver;
+	u16 rcbuffer_blocksize;
+	/* n+1 value */
+	u16 rcbuffer_size_in_blocks;
+	unsigned long rcbuffer_size;
+
+	union {
+		u8 slice_caps;
+		struct {
+			u8 one_slice_per_line_support : 1;
+			u8 two_slice_per_line_support : 1;
+			u8 slice_caps_reserved1 : 1;
+			u8 four_slice_per_line_support : 1;
+			u8 slice_caps_reserved2 : 4;
+		};
+	};
+	/* Decode line buffer bits of precision */
+	unsigned long line_buffer_bit_depth;
+	bool is_block_pred_supported;
+	unsigned long sink_support_max_bpp;
+
+	union {
+		u8 color_format_caps;
+		struct {
+			u8 RGB_support : 1;
+			u8 YCbCr444_support : 1;
+			u8 YCbCr422_support : 1;
+			u8 color_format_caps_reserved : 5;
+		};
+	};
+
+	union {
+		u8 color_depth_caps;
+		struct {
+			u8 color_depth_caps_reserved1 : 1;
+			u8 support_8bpc : 1;
+			u8 support_10bpc : 1;
+			u8 support_12bpc : 1;
+			u8 color_depth_caps_reserved2 : 4;
+		};
+	};
+
+	u16 slice_height;
+	u16 slice_width;
+	/* Y Resolution */
+	u16 pic_height;
+	/* X Resolution */
+	u16 pic_width;
+};
+
+
+
 struct intel_dp {
 	i915_reg_t output_reg;
 	i915_reg_t aux_ch_ctl_reg;
@@ -971,6 +1028,8 @@ struct intel_dp {
 	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 	uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
+	uint8_t dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
+	uint8_t fec_dpcd;
 	/* source rates */
 	int num_source_rates;
 	const int *source_rates;
@@ -1046,6 +1105,9 @@ struct intel_dp {
 
 	/* Displayport compliance testing */
 	struct intel_dp_compliance compliance;
+
+	/* For Vesa Display Stream Compression Support */
+	struct i915_compression_params compr_params;
 };
 
 struct intel_lspcon {
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index da58a428c8d7..05f811c50d28 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -896,6 +896,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
 #define DP_RECEIVER_CAP_SIZE		0xf
 #define EDP_PSR_RECEIVER_CAP_SIZE	2
 #define EDP_DISPLAY_CTL_CAP_SIZE	3
+#define DP_DSC_RECEIVER_CAP_SIZE	0xb
 
 void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
 void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
-- 
1.9.1

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[PATCH 02/10] drm: i915: Get DSC capability from DP sink

[Gaurav K Singh]

Get decompression capabilities from DP sink by doing
DPCD reads of different offsets as per eDP/DP specs.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 167 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 167 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1868f73f730c..f494a851ff89 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5883,6 +5883,149 @@ void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
 	return downclock_mode;
 }
 
+static void intel_dp_sink_get_dsc_capability(struct intel_dp *intel_dp,
+					struct dp_sink_dsc_caps *dp_dsc_caps)
+{
+	u8 rcbuffer_blocksize;
+	u8 fec_dpcd;
+	unsigned long line_buffer_bit_depth, sink_support_max_bpp_msb;
+
+	/* VDSC is supported only for eDp v1.4 or higher, DPCD 0x00700 offset */
+	if (intel_dp->edp_dpcd[0] < 0x03)
+		return;
+
+	/* Read DPCD 0x060 to 0x06a */
+	if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT, intel_dp->dsc_dpcd,
+			     sizeof(intel_dp->dsc_dpcd)) < 0)
+		return;
+
+	dp_dsc_caps->is_dsc_supported = intel_dp->dsc_dpcd[0] &
+					DP_DSC_DECOMPRESSION_IS_SUPPORTED;
+
+	if (!dp_dsc_caps->is_dsc_supported)
+		return;
+
+	drm_dp_dpcd_readb(&intel_dp->aux, 0x090, &fec_dpcd);
+	intel_dp->fec_dpcd = fec_dpcd;
+
+	/* For DP DSC, FEC support is must */
+	if (!(intel_dp->fec_dpcd & 0x1))
+		return;
+
+	/* No VDSC support for less than 8 BPC */
+	if (intel_dp->dsc_dpcd[0xa] < DP_DSC_8_BPC)
+		return;
+
+	if (intel_dp->dsc_dpcd[0xa] & DP_DSC_8_BPC)
+		DRM_INFO("8 Bits per color support\n");
+	if (intel_dp->dsc_dpcd[0xa] & DP_DSC_10_BPC)
+		DRM_INFO("10 Bits per color support\n");
+	if (intel_dp->dsc_dpcd[0xa] & DP_DSC_12_BPC)
+		DRM_INFO("12 Bits per color support\n");
+
+	dp_dsc_caps->dsc_major_ver = intel_dp->dsc_dpcd[1] & DP_DSC_MAJOR_MASK;
+	dp_dsc_caps->dsc_minor_ver = (intel_dp->dsc_dpcd[1] &
+				DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT;
+
+	rcbuffer_blocksize = intel_dp->dsc_dpcd[2] & 0x3;
+
+	switch (rcbuffer_blocksize) {
+	case 0:
+		dp_dsc_caps->rcbuffer_blocksize = 1;
+		break;
+	case 1:
+		dp_dsc_caps->rcbuffer_blocksize = 4;
+		break;
+	case 2:
+		dp_dsc_caps->rcbuffer_blocksize = 16;
+		break;
+	case 3:
+		dp_dsc_caps->rcbuffer_blocksize = 64;
+		break;
+	default:
+		break;
+
+	}
+	dp_dsc_caps->rcbuffer_size_in_blocks = intel_dp->dsc_dpcd[3] + 1;
+
+	dp_dsc_caps->rcbuffer_size =
+			dp_dsc_caps->rcbuffer_size_in_blocks *
+			dp_dsc_caps->rcbuffer_blocksize * 1024 * 8;
+
+	dp_dsc_caps->slice_caps = intel_dp->dsc_dpcd[4];
+	line_buffer_bit_depth = intel_dp->dsc_dpcd[5];
+
+	if (line_buffer_bit_depth == 8)
+		dp_dsc_caps->line_buffer_bit_depth = intel_dp->dsc_dpcd[5];
+	else
+		dp_dsc_caps->line_buffer_bit_depth = intel_dp->dsc_dpcd[5] + 9;
+
+	dp_dsc_caps->is_block_pred_supported = intel_dp->dsc_dpcd[6] &
+					DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
+
+	dp_dsc_caps->sink_support_max_bpp = intel_dp->dsc_dpcd[7];
+	sink_support_max_bpp_msb = (intel_dp->dsc_dpcd[8] & 0x3) << 8;
+	dp_dsc_caps->sink_support_max_bpp |= sink_support_max_bpp_msb;
+
+	dp_dsc_caps->color_format_caps = intel_dp->dsc_dpcd[9];
+	dp_dsc_caps->color_depth_caps = intel_dp->dsc_dpcd[0xa];
+}
+
+static void intel_dp_get_compression_data(struct intel_dp *intel_dp,
+					struct dp_sink_dsc_caps dp_dsc_caps)
+{
+	if (!dp_dsc_caps.is_dsc_supported)
+		return;
+
+	intel_dp->compr_params.compression_support =
+						dp_dsc_caps.is_dsc_supported;
+	intel_dp->compr_params.dsc_cfg.dsc_version_major =
+						dp_dsc_caps.dsc_major_ver;
+	intel_dp->compr_params.dsc_cfg.dsc_version_minor =
+						dp_dsc_caps.dsc_minor_ver;
+
+	/* By default set bpc to 8 */
+	intel_dp->compr_params.dsc_cfg.bits_per_component = 8;
+
+	/* Take the max for Bits per component */
+	if (intel_dp->dsc_dpcd[0xa] & DP_DSC_8_BPC)
+		intel_dp->compr_params.dsc_cfg.bits_per_component = 8;
+	if (intel_dp->dsc_dpcd[0xa] & DP_DSC_10_BPC)
+		intel_dp->compr_params.dsc_cfg.bits_per_component = 10;
+	if (intel_dp->dsc_dpcd[0xa] & DP_DSC_12_BPC)
+		intel_dp->compr_params.dsc_cfg.bits_per_component = 12;
+
+	intel_dp->compr_params.compression_bpp =
+					dp_dsc_caps.sink_support_max_bpp >> 4;
+	intel_dp->compr_params.dsc_cfg.bits_per_pixel =
+					dp_dsc_caps.sink_support_max_bpp;
+	intel_dp->compr_params.dsc_cfg.convert_rgb = dp_dsc_caps.RGB_support;
+	intel_dp->compr_params.dsc_cfg.enable422 = dp_dsc_caps.YCbCr422_support;
+	intel_dp->compr_params.dsc_cfg.block_pred_enable =
+					dp_dsc_caps.is_block_pred_supported;
+
+	/* Always try to enable 2 DSC instances, by default */
+	intel_dp->compr_params.dsc_cfg.num_vdsc_instances = 2;
+
+	if (dp_dsc_caps.four_slice_per_line_support)
+		intel_dp->compr_params.dsc_cfg.slice_count = 4;
+	else if (dp_dsc_caps.two_slice_per_line_support)
+		intel_dp->compr_params.dsc_cfg.slice_count = 2;
+	else if (dp_dsc_caps.one_slice_per_line_support) {
+		/*
+		 * Cannot use 2 DSC engines simultaneously when
+		 * slice per line support is only 1
+		 */
+		intel_dp->compr_params.dsc_cfg.slice_count = 1;
+		intel_dp->compr_params.dsc_cfg.num_vdsc_instances = 1;
+	} else
+		DRM_INFO("Slice count not supported:%d\n",
+							dp_dsc_caps.slice_caps);
+
+	intel_dp->compr_params.dsc_cfg.line_buf_depth =
+					dp_dsc_caps.line_buffer_bit_depth;
+}
+
 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 				     struct intel_connector *intel_connector)
 {
@@ -5892,6 +6035,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 	struct drm_display_mode *fixed_mode = NULL;
 	struct drm_display_mode *alt_fixed_mode = NULL;
 	struct drm_display_mode *downclock_mode = NULL;
+	struct dp_sink_dsc_caps sink_dp_dsc_caps = {0};
 	bool has_dpcd;
 	struct drm_display_mode *scan;
 	struct edid *edid;
@@ -5930,6 +6074,12 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 		goto out_vdd_off;
 	}
 
+	/* Get DSC capability of DP sink */
+	if (INTEL_GEN(dev_priv) >= 9) {
+		intel_dp_sink_get_dsc_capability(intel_dp, &sink_dp_dsc_caps);
+		intel_dp_get_compression_data(intel_dp, sink_dp_dsc_caps);
+	}
+
 	mutex_lock(&dev->mode_config.mutex);
 	edid = drm_get_edid(connector, &intel_dp->aux.ddc);
 	if (edid) {
@@ -5968,6 +6118,23 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 	}
 	mutex_unlock(&dev->mode_config.mutex);
 
+	if (intel_dp->compr_params.compression_support) {
+		intel_dp->compr_params.dsc_cfg.pic_width = fixed_mode->hdisplay;
+		intel_dp->compr_params.dsc_cfg.pic_height =
+							fixed_mode->vdisplay;
+		intel_dp->compr_params.dsc_cfg.slice_width = DIV_ROUND_UP(
+				intel_dp->compr_params.dsc_cfg.pic_width,
+				intel_dp->compr_params.dsc_cfg.slice_count);
+
+		/* slice height data is not available from dpcd */
+		if (intel_dp->compr_params.dsc_cfg.pic_height % 8 == 0)
+			intel_dp->compr_params.dsc_cfg.slice_height = 8;
+		if (intel_dp->compr_params.dsc_cfg.pic_height % 4 == 0)
+			intel_dp->compr_params.dsc_cfg.slice_height = 4;
+		if (intel_dp->compr_params.dsc_cfg.pic_height % 2 == 0)
+			intel_dp->compr_params.dsc_cfg.slice_height = 2;
+	}
+
 	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		intel_dp->edp_notifier.notifier_call = edp_notify_handler;
 		register_reboot_notifier(&intel_dp->edp_notifier);
-- 
1.9.1

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[PATCH 03/10] drm: i915: Enable/Disable DSC in DP sink

[Gaurav K Singh]

Below changes are being taken care in this patch:

1. If there is no DSC support from DPCD offset 0x60, just return
2. If DSC support is there, disable decompression in DPCD offset
0x160 during DP encoder disable sequence.
3. If DSC support is there, enable decompression in DPCD offset
0x160 during DP encoder enable sequence before sending PPS.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c |  4 ++++
 drivers/gpu/drm/i915/intel_dp.c  | 14 ++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h |  2 ++
 include/drm/drm_dp_helper.h      |  2 ++
 4 files changed, 22 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index db92a2691206..693061444d4b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2177,6 +2177,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
 	intel_ddi_init_dp_buf_reg(encoder);
 	if (!is_mst)
 		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+	/* Enable Decompression in DP Sink at DPCD offset 0x00160 offset */
+	intel_dp_sink_set_decompression_state(intel_dp, DECOMPRESSION_ENABLE);
 	intel_dp_start_link_train(intel_dp);
 	if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
 		intel_dp_stop_link_train(intel_dp);
@@ -2480,6 +2482,8 @@ static void intel_disable_ddi_dp(struct intel_encoder *encoder,
 	intel_edp_drrs_disable(intel_dp, old_crtc_state);
 	intel_psr_disable(intel_dp, old_crtc_state);
 	intel_edp_backlight_off(old_conn_state);
+	/* Disable Decompression in DP Sink at DPCD offset 0x00160 offset */
+	intel_dp_sink_set_decompression_state(intel_dp, DECOMPRESSION_DISABLE);
 }
 
 static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index f494a851ff89..c3b48b214e8f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2538,6 +2538,20 @@ static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
 		intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
 }
 
+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
+							int decomp_state)
+{
+	int ret;
+
+	if (!intel_dp->compr_params.compression_support)
+		return;
+
+	ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE, decomp_state);
+	if (ret < 0)
+		DRM_ERROR("DCPD write fail offset:0x%x for decompr state:%d\n",
+						DP_DSC_ENABLE, decomp_state);
+}
+
 /* If the sink supports it, try to set the power state appropriately */
 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
 {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 6e1b907990bf..8d8d4486773a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1595,6 +1595,8 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 void intel_dp_start_link_train(struct intel_dp *intel_dp);
 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
+void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
+							int decomp_state);
 void intel_dp_encoder_reset(struct drm_encoder *encoder);
 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 05f811c50d28..f3f44847c86e 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -445,6 +445,8 @@
 # define DP_AUX_FRAME_SYNC_VALID	    (1 << 0)
 
 #define DP_DSC_ENABLE                       0x160   /* DP 1.4 */
+#define DECOMPRESSION_ENABLE		    (1 << 0)
+#define DECOMPRESSION_DISABLE		    0
 
 #define DP_PSR_EN_CFG			    0x170   /* XXX 1.2? */
 # define DP_PSR_ENABLE			    (1 << 0)
-- 
1.9.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 04/10] drm: i915: Compute RC & DSC parameters

[Gaurav K Singh]

Below changes are there as part of this patch:
1. Adding Rate Control parameters for DSC
2. Compute Rate Control parameters
3. Compute DSC parameters for Picture Parameter Set
4. Adding a new .c file for VDSC operations

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/i915/Makefile     |   1 +
 drivers/gpu/drm/i915/i915_drv.h   |  12 +
 drivers/gpu/drm/i915/intel_dp.c   |   1 +
 drivers/gpu/drm/i915/intel_vdsc.c | 562 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 576 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 838f9b48246b..fee46d41100e 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -114,6 +114,7 @@ i915-y += intel_audio.o \
 	  intel_modes.o \
 	  intel_overlay.o \
 	  intel_psr.o \
+	  intel_vdsc.o \
 	  intel_sideband.o \
 	  intel_sprite.o
 i915-$(CONFIG_ACPI)		+= intel_acpi.o intel_opregion.o
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4b1c323c0925..4720a5ce3e69 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -793,6 +793,17 @@ struct rc_range_parameters {
 	unsigned long range_bpg_offset;
 };
 
+struct rc_parameters {
+	unsigned long initial_xmit_delay;
+	unsigned long first_line_bpg_Ofs;
+	unsigned long initial_offset;
+	unsigned long flatness_minQp;
+	unsigned long flatness_maxQp;
+	unsigned long rc_quant_incr_limit0;
+	unsigned long rc_quant_incr_limit1;
+	struct rc_range_parameters rc_range_params[NUM_BUF_RANGES];
+};
+
 struct vdsc_config {
 	/* Bits / component for previous reconstructed line buffer */
 	unsigned long line_buf_depth;
@@ -3858,6 +3869,7 @@ extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
 extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
 extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
 				  bool enable);
+extern void intel_dp_compute_dsc_parameters(struct intel_dp *dp);
 
 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
 			struct drm_file *file);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index c3b48b214e8f..93d3d6afa711 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -6092,6 +6092,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
 	if (INTEL_GEN(dev_priv) >= 9) {
 		intel_dp_sink_get_dsc_capability(intel_dp, &sink_dp_dsc_caps);
 		intel_dp_get_compression_data(intel_dp, sink_dp_dsc_caps);
+		intel_dp_compute_dsc_parameters(intel_dp);
 	}
 
 	mutex_lock(&dev->mode_config.mutex);
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
new file mode 100644
index 000000000000..5eef551f0d09
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -0,0 +1,562 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Author: Gaurav K Singh <gaurav.k.singh@intel.com>
+ */
+
+#include <drm/drmP.h>
+#include <drm/i915_drm.h>
+#include "i915_drv.h"
+#include "intel_drv.h"
+
+enum ROW_INDEX_BPP {
+	ROW_INDEX_INVALID = 127,
+	ROW_INDEX_6BPP = 0,
+	ROW_INDEX_8BPP,
+	ROW_INDEX_10BPP,
+	ROW_INDEX_12BPP,
+	ROW_INDEX_15BPP,
+	MAX_ROW_INDEX
+};
+
+enum COLUMN_INDEX_BPC {
+	COLUMN_INDEX_INVALID = 127,
+	COLUMN_INDEX_8BPC = 0,
+	COLUMN_INDEX_10BPC,
+	COLUMN_INDEX_12BPC,
+	COLUMN_INDEX_14BPC,
+	COLUMN_INDEX_16BPC,
+	MAX_COLUMN_INDEX
+};
+
+#define TWOS_COMPLEMENT(x) (unsigned char)((~(x) + 1) & 0x3F)
+
+/* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
+static unsigned long rc_buf_thresh[] = {
+	896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
+	7744, 7872, 8000, 8064
+};
+
+/*
+ * From DSC_v1.11 spec
+ * Selected Rate Control Related Parameter Recommended Values
+ */
+static struct rc_parameters rc_params[][MAX_COLUMN_INDEX] = {
+{
+	/* 6BPP/8BPC */
+	{ 768, 15, 6144, 3, 13, 11, 11,
+	{ { 0, 4, 0 }, { 1, 6, TWOS_COMPLEMENT(2) },
+	{ 3, 8, TWOS_COMPLEMENT(2) }, { 4, 8, TWOS_COMPLEMENT(4) },
+	{ 5, 9, TWOS_COMPLEMENT(6) }, { 5, 9, TWOS_COMPLEMENT(6) },
+	{ 6, 9, TWOS_COMPLEMENT(6) }, { 6, 10, TWOS_COMPLEMENT(8) },
+	{ 7, 11, TWOS_COMPLEMENT(8) }, { 8, 12, TWOS_COMPLEMENT(10) },
+	{ 9, 12, TWOS_COMPLEMENT(10) }, { 10, 12, TWOS_COMPLEMENT(12) },
+	{ 10, 12, TWOS_COMPLEMENT(12) }, { 11, 12, TWOS_COMPLEMENT(12) },
+	{ 13, 14, TWOS_COMPLEMENT(12) } } },
+	/* 6BPP/10BPC */
+	{ 768, 15, 6144, 7, 17, 15, 15,
+	{ { 0, 8, 0 }, { 3, 10, TWOS_COMPLEMENT(2) },
+	{ 7, 12, TWOS_COMPLEMENT(2) }, { 8, 12, TWOS_COMPLEMENT(4) },
+	{ 9, 13, TWOS_COMPLEMENT(6) }, { 9, 13, TWOS_COMPLEMENT(6) },
+	{ 10, 13, TWOS_COMPLEMENT(6) }, { 10, 14, TWOS_COMPLEMENT(8) },
+	{ 11, 15, TWOS_COMPLEMENT(8) }, { 12, 16, TWOS_COMPLEMENT(10) },
+	{ 13, 16, TWOS_COMPLEMENT(10) }, { 14, 16, TWOS_COMPLEMENT(12) },
+	{ 14, 16, TWOS_COMPLEMENT(12) }, { 15, 16, TWOS_COMPLEMENT(12) },
+	{ 17, 18, TWOS_COMPLEMENT(12) } } },
+	/* 6BPP/12BPC */
+	{ 768, 15, 6144, 11, 21, 19, 19,
+	{ { 0, 12, 0 }, { 5, 14, TWOS_COMPLEMENT(2) },
+	{ 11, 16, TWOS_COMPLEMENT(2) }, { 12, 16, TWOS_COMPLEMENT(4) },
+	{ 13, 17, TWOS_COMPLEMENT(6) }, { 13, 17, TWOS_COMPLEMENT(6) },
+	{ 14, 17, TWOS_COMPLEMENT(6) }, { 14, 18, TWOS_COMPLEMENT(8) },
+	{ 15, 19, TWOS_COMPLEMENT(8) }, { 16, 20, TWOS_COMPLEMENT(10) },
+	{ 17, 20, TWOS_COMPLEMENT(10) }, { 18, 20, TWOS_COMPLEMENT(12) },
+	{ 18, 20, TWOS_COMPLEMENT(12) }, { 19, 20, TWOS_COMPLEMENT(12) },
+	{ 21, 22, TWOS_COMPLEMENT(12) } } },
+	/* 6BPP/14BPC */
+	{ 768, 15, 6144, 15, 25, 23, 27,
+	{ { 0, 16, 0 }, { 7, 18, TWOS_COMPLEMENT(2) },
+	{ 15, 20, TWOS_COMPLEMENT(2) }, { 16, 20, TWOS_COMPLEMENT(4) },
+	{ 17, 21, TWOS_COMPLEMENT(6) }, { 17, 21, TWOS_COMPLEMENT(6) },
+	{ 18, 21, TWOS_COMPLEMENT(6) }, { 18, 22, TWOS_COMPLEMENT(8) },
+	{ 19, 23, TWOS_COMPLEMENT(8) }, { 20, 24, TWOS_COMPLEMENT(10) },
+	{ 21, 24, TWOS_COMPLEMENT(10) }, { 22, 24, TWOS_COMPLEMENT(12) },
+	{ 22, 24, TWOS_COMPLEMENT(12) }, { 23, 24, TWOS_COMPLEMENT(12) },
+	{ 25, 26, TWOS_COMPLEMENT(12) } } },
+	/* 6BPP/16BPC */
+	{ 768, 15, 6144, 19, 29, 27, 27,
+	{ { 0, 20, 0 }, { 9, 22, TWOS_COMPLEMENT(2) },
+	{ 19, 24, TWOS_COMPLEMENT(2) }, { 20, 24, TWOS_COMPLEMENT(4) },
+	{ 21, 25, TWOS_COMPLEMENT(6) }, { 21, 25, TWOS_COMPLEMENT(6) },
+	{ 22, 25, TWOS_COMPLEMENT(6) }, { 22, 26, TWOS_COMPLEMENT(8) },
+	{ 23, 27, TWOS_COMPLEMENT(8) }, { 24, 28, TWOS_COMPLEMENT(10) },
+	{ 25, 28, TWOS_COMPLEMENT(10) }, { 26, 28, TWOS_COMPLEMENT(12) },
+	{ 26, 28, TWOS_COMPLEMENT(12) }, { 27, 28, TWOS_COMPLEMENT(12) },
+	{ 29, 30, TWOS_COMPLEMENT(12) } } },
+},
+{
+	/* 8BPP/8BPC */
+	{ 512, 12, 6144, 3, 12, 11, 11,
+	{ { 0, 4, 2 }, { 0, 4, 0 }, { 1, 5, 0 }, { 1, 6, TWOS_COMPLEMENT(2) },
+	{ 3, 7, TWOS_COMPLEMENT(4) }, { 3, 7, TWOS_COMPLEMENT(6) },
+	{ 3, 7, TWOS_COMPLEMENT(8) }, { 3, 8, TWOS_COMPLEMENT(8) },
+	{ 3, 9, TWOS_COMPLEMENT(8) }, { 3, 10, TWOS_COMPLEMENT(10) },
+	{ 5, 11, TWOS_COMPLEMENT(10) }, { 5, 12, TWOS_COMPLEMENT(12) },
+	{ 5, 13, TWOS_COMPLEMENT(12) }, { 7, 13, TWOS_COMPLEMENT(12) },
+	{ 13, 15, TWOS_COMPLEMENT(12) } } },
+	/* 8BPP/10BPC */
+	{ 512, 12, 6144, 7, 16, 15, 15,
+	{ { 0, 4, 2 }, { 4, 8, 0 }, { 5, 9, 0 }, { 5, 10, TWOS_COMPLEMENT(2) },
+	{ 7, 11, TWOS_COMPLEMENT(4) }, { 7, 11, TWOS_COMPLEMENT(6) },
+	{ 7, 11, TWOS_COMPLEMENT(8) }, { 7, 12, TWOS_COMPLEMENT(8) },
+	{ 7, 13, TWOS_COMPLEMENT(8) }, { 7, 14, TWOS_COMPLEMENT(10) },
+	{ 9, 15, TWOS_COMPLEMENT(10) }, { 9, 16, TWOS_COMPLEMENT(12) },
+	{ 9, 17, TWOS_COMPLEMENT(12) }, { 11, 17, TWOS_COMPLEMENT(12) },
+	{ 17, 19, TWOS_COMPLEMENT(12) } } },
+	/* 8BPP/12BPC */
+	{ 512, 12, 6144, 11, 20, 19, 19,
+	{ { 0, 12, 2 }, { 4, 12, 0 }, { 9, 13, 0 },
+	{ 9, 14, TWOS_COMPLEMENT(2) }, { 11, 15, TWOS_COMPLEMENT(4) },
+	{ 11, 15, TWOS_COMPLEMENT(6) }, { 11, 15, TWOS_COMPLEMENT(8) },
+	{ 11, 16, TWOS_COMPLEMENT(8) }, { 11, 17, TWOS_COMPLEMENT(8) },
+	{ 11, 18, TWOS_COMPLEMENT(10) }, { 13, 19, TWOS_COMPLEMENT(10) },
+	{ 13, 20, TWOS_COMPLEMENT(12) }, { 13, 21, TWOS_COMPLEMENT(12) },
+	{ 15, 21, TWOS_COMPLEMENT(12) }, { 21, 23, TWOS_COMPLEMENT(12) } } },
+	/* 8BPP/14BPC */
+	{ 512, 12, 6144, 15, 24, 23, 23, { { 0, 12, 0 }, { 5, 13, 0 },
+	{ 11, 15, 0 }, { 12, 17, TWOS_COMPLEMENT(2) },
+	{ 15, 19, TWOS_COMPLEMENT(4) }, { 15, 19, TWOS_COMPLEMENT(6) },
+	{ 15, 19, TWOS_COMPLEMENT(8) }, { 15, 20, TWOS_COMPLEMENT(8) },
+	{ 15, 21, TWOS_COMPLEMENT(8) }, { 15, 22, TWOS_COMPLEMENT(10) },
+	{ 17, 22, TWOS_COMPLEMENT(10) }, { 17, 23, TWOS_COMPLEMENT(12) },
+	{ 17, 23, TWOS_COMPLEMENT(12) }, { 21, 24, TWOS_COMPLEMENT(12) },
+	{ 24, 25, TWOS_COMPLEMENT(12) } } },
+	/* 8BPP/16BPC */
+	{ 512, 12, 6144, 19, 28, 27, 27, { { 0, 12, 2 }, { 6, 14, 0 },
+	{ 13, 17, 0 }, { 15, 20, TWOS_COMPLEMENT(2) },
+	{ 19, 23, TWOS_COMPLEMENT(4) }, { 19, 23, TWOS_COMPLEMENT(6) },
+	{ 19, 23, TWOS_COMPLEMENT(8) }, { 19, 24, TWOS_COMPLEMENT(8) },
+	{ 19, 25, TWOS_COMPLEMENT(8) }, { 19, 26, TWOS_COMPLEMENT(10) },
+	{ 21, 26, TWOS_COMPLEMENT(10) }, { 21, 27, TWOS_COMPLEMENT(12) },
+	{ 21, 27, TWOS_COMPLEMENT(12) }, { 25, 28, TWOS_COMPLEMENT(12) },
+	{ 28, 29, TWOS_COMPLEMENT(12) } } },
+},
+{
+	/* 10BPP/8BPC */
+	{ 410, 15, 5632, 3, 12, 11, 11, { { 0, 3, 2 }, { 0, 4, 0 },
+	{ 1, 5, 0 }, { 2, 6, TWOS_COMPLEMENT(2) }, { 3, 7, TWOS_COMPLEMENT(4) },
+	{ 3, 7, TWOS_COMPLEMENT(6) }, { 3, 7, TWOS_COMPLEMENT(8) },
+	{ 3, 8, TWOS_COMPLEMENT(8) }, { 3, 9, TWOS_COMPLEMENT(8) },
+	{ 3, 9, TWOS_COMPLEMENT(10) }, { 5, 10, TWOS_COMPLEMENT(10) },
+	{ 5, 10, TWOS_COMPLEMENT(10) }, { 5, 11, TWOS_COMPLEMENT(12) },
+	{ 7, 11, TWOS_COMPLEMENT(12) }, { 11, 12, TWOS_COMPLEMENT(12) } } },
+	/* 10BPP/10BPC */
+	{ 410, 15, 5632, 7, 16, 15, 15, { { 0, 7, 2 }, { 4, 8, 0 },
+	{ 5, 9, 0 }, { 6, 10, TWOS_COMPLEMENT(2) },
+	{ 7, 11, TWOS_COMPLEMENT(4) }, { 7, 11, TWOS_COMPLEMENT(6) },
+	{ 7, 11, TWOS_COMPLEMENT(8) }, { 7, 12, TWOS_COMPLEMENT(8) },
+	{ 7, 13, TWOS_COMPLEMENT(8) }, { 7, 13, TWOS_COMPLEMENT(10) },
+	{ 9, 14, TWOS_COMPLEMENT(10) }, { 9, 14, TWOS_COMPLEMENT(10) },
+	{ 9, 15, TWOS_COMPLEMENT(12) }, { 11, 15, TWOS_COMPLEMENT(12) },
+	{ 15, 16, TWOS_COMPLEMENT(12) } } },
+	/* 10BPP/12BPC */
+	{ 410, 15, 5632, 11, 20, 19, 19, { { 0, 11, 2 }, { 4, 12, 0 },
+	{ 9, 13, 0 }, { 10, 14, TWOS_COMPLEMENT(2) },
+	{ 11, 15, TWOS_COMPLEMENT(4) }, { 11, 15, TWOS_COMPLEMENT(6) },
+	{ 11, 15, TWOS_COMPLEMENT(8) }, { 11, 16, TWOS_COMPLEMENT(8) },
+	{ 11, 17, TWOS_COMPLEMENT(8) }, { 11, 17, TWOS_COMPLEMENT(10) },
+	{ 13, 18, TWOS_COMPLEMENT(10) }, { 13, 18, TWOS_COMPLEMENT(10) },
+	{ 13, 19, TWOS_COMPLEMENT(12) }, { 15, 19, TWOS_COMPLEMENT(12) },
+	{ 19, 20, TWOS_COMPLEMENT(12) } } },
+	/* 10BPP/14BPC */
+	{ 410, 15, 5632, 15, 24, 23, 23, { { 0, 11, 2 }, { 5, 13, 0 },
+	{ 11, 15, 0 }, { 13, 18, TWOS_COMPLEMENT(2) },
+	{ 15, 19, TWOS_COMPLEMENT(4) }, { 15, 19, TWOS_COMPLEMENT(6) },
+	{ 15, 19, TWOS_COMPLEMENT(8) }, { 15, 20, TWOS_COMPLEMENT(8) },
+	{ 15, 21, TWOS_COMPLEMENT(8) }, { 15, 21, TWOS_COMPLEMENT(10) },
+	{ 17, 22, TWOS_COMPLEMENT(10) }, { 17, 22, TWOS_COMPLEMENT(10) },
+	{ 17, 23, TWOS_COMPLEMENT(12) }, { 19, 23, TWOS_COMPLEMENT(12) },
+	{ 23, 24, TWOS_COMPLEMENT(12) } } },
+	/* 10BPP/16BPC */
+	{ 410, 15, 5632, 19, 28, 27, 27, { { 0, 11, 2 }, { 6, 14, 0 },
+	{ 13, 17, 0 }, { 16, 20, TWOS_COMPLEMENT(2) },
+	{ 19, 23, TWOS_COMPLEMENT(4) }, { 19, 23, TWOS_COMPLEMENT(6) },
+	{ 19, 23, TWOS_COMPLEMENT(8) }, { 19, 24, TWOS_COMPLEMENT(8) },
+	{ 19, 25, TWOS_COMPLEMENT(8) }, { 19, 25, TWOS_COMPLEMENT(10) },
+	{ 21, 26, TWOS_COMPLEMENT(10) }, { 21, 26, TWOS_COMPLEMENT(10) },
+	{ 21, 27, TWOS_COMPLEMENT(12) }, { 23, 27, TWOS_COMPLEMENT(12) },
+	{ 27, 28, TWOS_COMPLEMENT(12) } } },
+},
+{
+	/* 12BPP/8BPC */
+	{ 341, 15, 2048, 3, 12, 11, 11, { { 0, 2, 2 }, { 0, 4, 0 },
+	{ 1, 5, 0 }, { 1, 6, TWOS_COMPLEMENT(2) }, { 3, 7, TWOS_COMPLEMENT(4) },
+	{ 3, 7, TWOS_COMPLEMENT(6) }, { 3, 7, TWOS_COMPLEMENT(8) },
+	{ 3, 8, TWOS_COMPLEMENT(8) }, { 3, 9, TWOS_COMPLEMENT(8) },
+	{ 3, 10, TWOS_COMPLEMENT(10) }, { 5, 11, TWOS_COMPLEMENT(10) },
+	{ 5, 12, TWOS_COMPLEMENT(12) }, { 5, 13, TWOS_COMPLEMENT(12) },
+	{ 7, 13, TWOS_COMPLEMENT(12) }, { 13, 15, TWOS_COMPLEMENT(12) } } },
+	/* 12BPP/10BPC */
+	{ 341, 15, 2048, 7, 16, 15, 15, { { 0, 2, 2 }, { 2, 5, 0 },
+	{ 3, 7, 0 }, { 4, 8, TWOS_COMPLEMENT(2) }, { 6, 9, TWOS_COMPLEMENT(4) },
+	{ 7, 10, TWOS_COMPLEMENT(6) }, { 7, 11, TWOS_COMPLEMENT(8) },
+	{ 7, 12, TWOS_COMPLEMENT(8) }, { 7, 13, TWOS_COMPLEMENT(8) },
+	{ 7, 14, TWOS_COMPLEMENT(10) }, { 9, 15, TWOS_COMPLEMENT(10) },
+	{ 9, 16, TWOS_COMPLEMENT(12) }, { 9, 17, TWOS_COMPLEMENT(12) },
+	{ 11, 17, TWOS_COMPLEMENT(12) }, { 17, 19, TWOS_COMPLEMENT(12) } } },
+	/* 12BPP/12BPC */
+	{ 341, 15, 2048, 11, 20, 19, 19, { { 0, 6, 2 }, { 4, 9, 0 },
+	{ 7, 11, 0 }, { 8, 12, TWOS_COMPLEMENT(2) },
+	{ 10, 13, TWOS_COMPLEMENT(4) }, { 11, 14, TWOS_COMPLEMENT(6) },
+	{ 11, 15, TWOS_COMPLEMENT(8) }, { 11, 16, TWOS_COMPLEMENT(8) },
+	{ 11, 17, TWOS_COMPLEMENT(8) }, { 11, 18, TWOS_COMPLEMENT(10) },
+	{ 13, 19, TWOS_COMPLEMENT(10) }, { 13, 20, TWOS_COMPLEMENT(12) },
+	{ 13, 21, TWOS_COMPLEMENT(12) }, { 15, 21, TWOS_COMPLEMENT(12) },
+	{ 21, 23, TWOS_COMPLEMENT(12) } } },
+	/* 12BPP/14BPC */
+	{ 341, 15, 2048, 15, 24, 23, 23, { { 0, 6, 2 }, { 7, 10, 0 },
+	{ 9, 13, 0 }, { 11, 16, TWOS_COMPLEMENT(2) },
+	{ 14, 17, TWOS_COMPLEMENT(4) }, { 15, 18, TWOS_COMPLEMENT(6) },
+	{ 15, 19, TWOS_COMPLEMENT(8) }, { 15, 20, TWOS_COMPLEMENT(8) },
+	{ 15, 20, TWOS_COMPLEMENT(8) }, { 15, 21, TWOS_COMPLEMENT(10) },
+	{ 17, 21, TWOS_COMPLEMENT(10) }, { 17, 21, TWOS_COMPLEMENT(12) },
+	{ 17, 21, TWOS_COMPLEMENT(12) }, { 19, 22, TWOS_COMPLEMENT(12) },
+	{ 22, 23, TWOS_COMPLEMENT(12) } } },
+	/* 12BPP/16BPC */
+	{ 341, 15, 2048, 19, 28, 27, 27, { { 0, 6, 2 }, { 6, 11, 0 },
+	{ 11, 15, 0 }, { 14, 18, TWOS_COMPLEMENT(2) },
+	{ 18, 21, TWOS_COMPLEMENT(4) }, { 19, 22, TWOS_COMPLEMENT(6) },
+	{ 19, 23, TWOS_COMPLEMENT(8) }, { 19, 24, TWOS_COMPLEMENT(8) },
+	{ 19, 24, TWOS_COMPLEMENT(8) }, { 19, 25, TWOS_COMPLEMENT(10) },
+	{ 21, 25, TWOS_COMPLEMENT(10) }, { 21, 25, TWOS_COMPLEMENT(12) },
+	{ 21, 25, TWOS_COMPLEMENT(12) }, { 23, 26, TWOS_COMPLEMENT(12) },
+	{ 26, 27, TWOS_COMPLEMENT(12) } } },
+},
+{
+	/* 15BPP/8BPC */
+	{ 273, 15, 2048, 3, 12, 11, 11, { { 0, 0, 10 }, { 0, 1, 8 },
+	{ 0, 1, 6 }, { 0, 2, 4 }, { 1, 2, 2 }, { 1, 3, 0 },
+	{ 1, 3, TWOS_COMPLEMENT(2) }, { 2, 4, TWOS_COMPLEMENT(4) },
+	{ 2, 5, TWOS_COMPLEMENT(6) }, { 3, 5, TWOS_COMPLEMENT(8) },
+	{ 4, 6, TWOS_COMPLEMENT(10) }, { 4, 7, TWOS_COMPLEMENT(10) },
+	{ 5, 7, TWOS_COMPLEMENT(12) }, { 7, 8, TWOS_COMPLEMENT(12) },
+	{ 8, 9, TWOS_COMPLEMENT(12) } } },
+	/* 15BPP/10BPC */
+	{ 273, 15, 2048, 7, 16, 15, 15, { { 0, 2, 10 }, { 2, 5, 8 },
+	{ 3, 5, 6 }, { 4, 6, 4 }, { 5, 6, 2 }, { 5, 7, 0 },
+	{ 5, 7, TWOS_COMPLEMENT(2) }, { 6, 8, TWOS_COMPLEMENT(4) },
+	{ 6, 9, TWOS_COMPLEMENT(6) }, { 7, 9, TWOS_COMPLEMENT(8) },
+	{ 8, 10, TWOS_COMPLEMENT(10) }, { 8, 11, TWOS_COMPLEMENT(10) },
+	{ 9, 11, TWOS_COMPLEMENT(12) }, { 11, 12, TWOS_COMPLEMENT(12) },
+	{ 12, 13, TWOS_COMPLEMENT(12) } } },
+	/* 15BPP/12BPC */
+	{ 273, 15, 2048, 11, 20, 19, 19, { { 0, 4, 10 }, { 2, 7, 8 },
+	{ 4, 9, 6 }, { 6, 11, 4 }, { 9, 11, 2 }, { 9, 11, 0 },
+	{ 9, 12, TWOS_COMPLEMENT(2) }, { 10, 12, TWOS_COMPLEMENT(4) },
+	{ 11, 13, TWOS_COMPLEMENT(6) }, { 11, 13, TWOS_COMPLEMENT(8) },
+	{ 12, 14, TWOS_COMPLEMENT(10) }, { 13, 15, TWOS_COMPLEMENT(10) },
+	{ 13, 15, TWOS_COMPLEMENT(12) }, { 15, 16, TWOS_COMPLEMENT(12) },
+	{ 16, 17, TWOS_COMPLEMENT(12) } } },
+	/* 15BPP/14BPC */
+	{ 273, 15, 2048, 15, 24, 23, 23, { { 0, 4, 10 }, { 3, 8, 8 },
+	{ 6, 11, 6 }, { 9, 14, 4 }, { 13, 15, 2 }, { 13, 15, 0 },
+	{ 13, 16, TWOS_COMPLEMENT(2) }, { 14, 16, TWOS_COMPLEMENT(4) },
+	{ 15, 17, TWOS_COMPLEMENT(6) }, { 15, 17, TWOS_COMPLEMENT(8) },
+	{ 16, 18, TWOS_COMPLEMENT(10) }, { 17, 19, TWOS_COMPLEMENT(10) },
+	{ 17, 19, TWOS_COMPLEMENT(12) }, { 19, 20, TWOS_COMPLEMENT(12) },
+	{ 20, 21, TWOS_COMPLEMENT(12) } } },
+	/* 15BPP/16BPC */
+	{ 273, 15, 2048, 19, 28, 27, 27, { { 0, 4, 10 }, { 4, 9, 8 },
+	{ 8, 13, 6 }, { 12, 17, 4 }, { 17, 19, 2 }, { 17, 20, 0 },
+	{ 17, 20, TWOS_COMPLEMENT(2) }, { 18, 20, TWOS_COMPLEMENT(4) },
+	{ 19, 21, TWOS_COMPLEMENT(6) }, { 19, 21, TWOS_COMPLEMENT(8) },
+	{ 20, 22, TWOS_COMPLEMENT(10) }, { 21, 23, TWOS_COMPLEMENT(10) },
+	{ 21, 23, TWOS_COMPLEMENT(12) }, { 23, 24, TWOS_COMPLEMENT(12) },
+	{ 24, 25, TWOS_COMPLEMENT(12) } } }
+}
+};
+
+static void intel_compute_rc_parameters(struct intel_dp *intel_dp)
+{
+	unsigned long groups_per_line = 0;
+	unsigned long groups_total = 0;
+	unsigned long num_extra_mux_bits = 0;
+	unsigned long slice_bits = 0;
+	unsigned long hrd_delay = 0;
+	unsigned long final_scale = 0;
+	unsigned long rbs_min = 0;
+	struct vdsc_config *vdsc_cfg  =  &(intel_dp->compr_params.dsc_cfg);
+
+	/* Number of groups used to code each line of a slice */
+	groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width, 3);
+
+	/* chunksize = DIV_ROUND_UP(slicewidth*bitsperpixel/8) in Bytes */
+	vdsc_cfg->chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width *
+						vdsc_cfg->bits_per_pixel,
+								(8 * 16));
+
+	if (vdsc_cfg->convert_rgb)
+		num_extra_mux_bits = 3 *
+				(vdsc_cfg->mux_word_size +
+				(4 * vdsc_cfg->bits_per_component + 4) - 2);
+	else
+// YCbCr
+		num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size +
+				(4 * vdsc_cfg->bits_per_component + 4) +
+				2 * (4 * vdsc_cfg->bits_per_component) - 2;
+	/* Number of bits in one Slice */
+	slice_bits = 8 * vdsc_cfg->chunk_size * vdsc_cfg->slice_height;
+
+	while ((num_extra_mux_bits > 0) &&
+		((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size))
+		num_extra_mux_bits--;
+
+	if (groups_per_line < vdsc_cfg->initial_scale_value - 8)
+		vdsc_cfg->initial_scale_value = groups_per_line + 8;
+
+	if (vdsc_cfg->initial_scale_value > 8)
+		vdsc_cfg->scale_decrement_interval = groups_per_line /
+					(vdsc_cfg->initial_scale_value - 8);
+	else
+		vdsc_cfg->scale_decrement_interval = 4095;
+
+	vdsc_cfg->final_offset = vdsc_cfg->rc_model_size -
+				(vdsc_cfg->initial_xmit_delay *
+				vdsc_cfg->bits_per_pixel + 8) / 16 +
+				num_extra_mux_bits;
+
+	if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) {
+		DRM_ERROR("FinalOfs < RcModelSze.Increase InitialXmitDelay\n");
+		return;
+	}
+
+	/* FinalScale, multiply by 8 to preserve 3 fractional bits */
+	final_scale = (8 * vdsc_cfg->rc_model_size) /
+			(vdsc_cfg->rc_model_size - vdsc_cfg->final_offset);
+	if (vdsc_cfg->slice_height > 1)
+		/*
+		 * NflBpgOffset is 16 bit value with 11 fractional bits
+		 * hence we multiply by 2^11 for preserving the
+		 * fractional part
+		 */
+		vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP(
+				(vdsc_cfg->first_line_bpg_Ofs << 11),
+				(vdsc_cfg->slice_height - 1));
+	else
+		vdsc_cfg->nfl_bpg_offset = 0;
+
+	/* 2^16 - 1 */
+	if (vdsc_cfg->nfl_bpg_offset > 65535) {
+		DRM_ERROR("NflBpgOffset is too large for this slice height\n");
+		return;
+	}
+
+	/* Number of groups used to code the entire slice */
+	groups_total = groups_per_line * vdsc_cfg->slice_height;
+
+	/*
+	 * slice_bpg_offset is 16 bit value with 11 fractional bits
+	 * hence we multiply by 2^11 for preserving the fractional part
+	 */
+	vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(
+			((vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
+			num_extra_mux_bits) << 11), groups_total);
+
+	if (final_scale > 9) {
+	/*
+	 * ScaleIncrementInterval =
+	 * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125))
+	 * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value,
+	 * we need divide by 2^11 from pstDscCfg values
+	 * ScaleIncrementInterval =
+	 *finaloffset/((NflBpgOfset + SlicBpgOfset)/2^11*8(finalscale - 1.125))
+	 * ScaleIncrementInterval =
+	 *finaloffset*2^11/((NflBpgOfset + SlicBpgOfset)*8(finalscale - 1.125))
+	 * ScaleIncrementInterval =
+	 * finaloffset*2^11/((NflBpgOffset + SliceBpgOffset)*(8*finalscale - 9))
+	 * as finalscale has 3 fractional bits stored we need to divide by 8.
+	 * ScaleIncrementInterval =
+	 *finaloffset*2^11/((NflBpgOffset + SliceBpgOffset)*(finalscale - 9))
+	 */
+		vdsc_cfg->scale_increment_interval =
+				(vdsc_cfg->final_offset * (1 << 11)) /
+						((vdsc_cfg->nfl_bpg_offset +
+						vdsc_cfg->slice_bpg_offset)*
+						(final_scale - 9));
+	} else {
+	/*
+	 * If finalScaleValue is less than or equal to 9, a value of 0 should
+	 * be used to disable the scale increment at the end of the slice
+	 */
+		vdsc_cfg->scale_increment_interval = 0;
+	}
+
+	if (vdsc_cfg->scale_increment_interval > 65535) {
+		DRM_ERROR("ScaleIncrementInterval is large for slice height\n");
+		return;
+	}
+	rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset +
+		(vdsc_cfg->initial_xmit_delay * vdsc_cfg->bits_per_pixel) /
+		16 + groups_per_line * vdsc_cfg->first_line_bpg_Ofs;
+
+	hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel);
+	vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16;
+	vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay;
+}
+
+void intel_dp_compute_dsc_parameters(struct intel_dp *intel_dp)
+{
+	struct vdsc_config *vdsc_cfg  =  &(intel_dp->compr_params.dsc_cfg);
+	unsigned long bits_per_pixel = 0;
+	unsigned char i = 0;
+	unsigned char row_index = 0;
+	unsigned char column_index = 0;
+
+	bits_per_pixel = vdsc_cfg->bits_per_pixel;
+
+	/*
+	 * rc_parameter_set  syntax elements typically
+	 * constant across operating modes
+	 */
+	vdsc_cfg->rc_model_size = 8192;
+	vdsc_cfg->rc_edge_factor = 6;
+	vdsc_cfg->rc_tgt_offset_high = 3;
+	vdsc_cfg->rc_tgt_offset_low = 3;
+
+	for (i = 0; i < NUM_BUF_RANGES - 1; i++) {
+		/*
+		 * six 0s are appended to the lsb of each threshold value
+		 * internally in h/w.
+		 * Only 8 bits are allowed for programming RcBufThreshold,
+		 * so we divide RcBufThreshold by 2^6
+		 */
+		vdsc_cfg->rc_buf_thresh[i] = rc_buf_thresh[i] / 64;
+	}
+
+	/* For 6bpp, RC Buffer threshold 12 and 13 need a different value. */
+	if (bits_per_pixel == 6) {
+		vdsc_cfg->rc_buf_thresh[12] = 0x7C;
+		vdsc_cfg->rc_buf_thresh[13] = 0x7D;
+	}
+
+	switch (bits_per_pixel) {
+	case 6:
+		row_index = ROW_INDEX_6BPP;
+		break;
+	case 8:
+		row_index = ROW_INDEX_8BPP;
+		break;
+	case 10:
+		row_index = ROW_INDEX_10BPP;
+		break;
+	case 12:
+		row_index = ROW_INDEX_12BPP;
+		break;
+	case 15:
+		row_index = ROW_INDEX_15BPP;
+		break;
+	default:
+		row_index = ROW_INDEX_INVALID;
+		break;
+	}
+
+	if (row_index == ROW_INDEX_INVALID) {
+		DRM_ERROR("Function:%s Unsupported BPP\n", __func__);
+		return;
+	}
+
+	switch (vdsc_cfg->bits_per_component) {
+	case 8:
+		column_index = COLUMN_INDEX_8BPC;
+		break;
+	case 10:
+		column_index = COLUMN_INDEX_10BPC;
+		break;
+	case 12:
+		column_index = COLUMN_INDEX_12BPC;
+		break;
+	case 14:
+		column_index = COLUMN_INDEX_14BPC;
+		break;
+	case 16:
+		column_index = COLUMN_INDEX_16BPC;
+		break;
+	default:
+		column_index = COLUMN_INDEX_INVALID;
+		break;
+	}
+
+	if (column_index == COLUMN_INDEX_INVALID) {
+		DRM_ERROR("Function:%s Unsupported BPC\n", __func__);
+		return;
+	}
+
+	vdsc_cfg->first_line_bpg_Ofs =
+			rc_params[row_index][column_index].first_line_bpg_Ofs;
+	vdsc_cfg->initial_xmit_delay =
+			rc_params[row_index][column_index].initial_xmit_delay;
+	vdsc_cfg->initial_offset =
+			rc_params[row_index][column_index].initial_offset;
+	vdsc_cfg->flatness_minQp =
+			rc_params[row_index][column_index].flatness_minQp;
+	vdsc_cfg->flatness_maxQp =
+			rc_params[row_index][column_index].flatness_maxQp;
+	vdsc_cfg->rc_quant_incr_limit0 =
+			rc_params[row_index][column_index].rc_quant_incr_limit0;
+	vdsc_cfg->rc_quant_incr_limit1 =
+			rc_params[row_index][column_index].rc_quant_incr_limit1;
+
+	for (i = 0; i < NUM_BUF_RANGES; i++) {
+		vdsc_cfg->rc_range_params[i].range_min_qp =
+	rc_params[row_index][column_index].rc_range_params[i].range_min_qp;
+		vdsc_cfg->rc_range_params[i].range_max_qp =
+	rc_params[row_index][column_index].rc_range_params[i].range_max_qp;
+		vdsc_cfg->rc_range_params[i].range_bpg_offset =
+	rc_params[row_index][column_index].rc_range_params[i].range_bpg_offset;
+	}
+
+	if (vdsc_cfg->initial_offset >= vdsc_cfg->rc_model_size) {
+		DRM_ERROR("Initial Offset is greater than RC Model Size\n");
+		return;
+	}
+
+	/*
+	 * BitsPerComponent value determines mux_word_size:
+	 * When BitsPerComponent is 12bpc, muxWordSize will be equal to 64 bits
+	 * When BitsPerComponent is 8 or 10bpc, muxWordSize will be equal to
+	 * 48 bits
+	 */
+	if (vdsc_cfg->bits_per_component <= 10)
+		vdsc_cfg->mux_word_size = 48;
+	else
+		vdsc_cfg->mux_word_size = 64;
+
+	/*
+	 * InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3)
+	 * In order to preserve the fractional part multiply numerator by 2^3
+	 */
+	vdsc_cfg->initial_scale_value = (8 * vdsc_cfg->rc_model_size) /
+			(vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
+
+	intel_compute_rc_parameters(intel_dp);
+
+}
-- 
1.9.1

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[PATCH 05/10] drm: i915: Define Picture Parameter Set

[Gaurav K Singh]

Vesa Display Stream Compression defines Picture Parameter Set(PPS),
which encoders must communicate to decoders. PPS is encapsulated
in 128 bytes(PS0 through PS127). PPS specifies the syntax for DSC
bitstreams.Correct decoding also requires that an identical PPS be
used at the encoder and decoder. The PPS contains parameters that
the decoder needs to correctly decode pictures.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 389 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 389 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4720a5ce3e69..760b97ec89ff 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -780,6 +780,395 @@ struct i915_psr {
 	void (*setup_vsc)(struct intel_dp *, const struct intel_crtc_state *);
 };
 
+struct picture_parameters_set {
+	union {
+		/* PPS0 */
+		unsigned char dsc_version;
+		struct {
+			/* Bit 0-3 Major version no */
+			unsigned char minor : 4;
+			/* Bit 4-7 Minor version no */
+			unsigned char major : 4;
+		};
+	};
+
+	union {
+		/* PPS 1 ,2 */
+		unsigned short picture_params_set_identifier;
+		struct {
+			/*
+			 * Bit 0-7 Application-specific identifier that can be
+			 * used to differentiate  between  different PPS table
+			 */
+			unsigned short pps_identifier : 8;
+			/* Bit 8-15 Reserved */
+			unsigned short pps2_reserved :8;
+		};
+	};
+
+	union {
+		/* PPS 3 */
+		unsigned char bpc_and_lbd;
+		struct {
+			/*
+			 * Bit  0-3 [1000 = 8 bits, 1001 = 9 bits,
+			 * 1010 = 10 bits, 1011 = 11 bits, 1100 = 12bits}
+			 */
+			unsigned char line_buffer_depth : 4;
+			/*
+			 * Bits 4-7 [1000 = 8 bits per component,1010 = 10 bits
+			 * per component,1100 = 12 bits per component]
+			 */
+			unsigned char bits_per_component : 4;
+		};
+	};
+
+	union {
+		/* PPS 4,5 */
+		unsigned short general_pps_params;
+		struct {
+			/*
+			 * Bits 0-1 The target bits/pixel (bpp) rate that is
+			 * used by the encoder, in steps of 1/16 of a
+			 * bit per pixel
+			 */
+			unsigned short bpp_low : 2;
+			/*
+			 * Bit 2 [0 = VBR mode is disabled,
+			 * 1 = VBR mode is enabled
+			 */
+			unsigned short vbr_mode : 1;
+			/* Bit 3 [0 = 4:4:4 sampling, 1 = 4:2:2 sampling] */
+			unsigned short enable422 : 1;
+			/*
+			 * Bit 4 [ 0 =  no conversion required,
+			 * 1 =  need conversion from RGB to YCoCg-R during
+			 * encoding]
+			 */
+			unsigned short convert_RGB : 1;
+			/*
+			 * Bit 5 [0 =  If block prediction is not supported
+			 * on the receiver, 1 =  If block prediction is
+			 * supported on the receiver]
+			 */
+			unsigned short block_prediction_enable : 1;
+			/* Bit 6-7 reserved */
+			unsigned short pps4_reserved :2;
+			/*
+			 * Bits 8-15  The target bits/pixel (bpp) rate that is
+			 * used by the encoder, in steps of 1/16 of a bit per
+			 * pixel
+			 */
+			unsigned short bpp_high : 8;
+		};
+	};
+
+	/* PPS 6,7 [2 bytes for pic height] */
+	unsigned short picture_height;
+	/* PPS 8,9 [2 bytes for pic width] */
+	unsigned short picture_width;
+	/* PPS 10,11 [2 bytes for slice height] */
+	unsigned short slice_height;
+	/* PPS 12,13 [2 bytes for slice width] */
+	unsigned short slice_width;
+
+	/*  PPS 14, 15 [2 bytes for Chunk size] */
+	unsigned short chunk_size;
+
+	union {
+		/* PPS 16,17 */
+		unsigned short initial_transmission_delay;
+		struct {
+			/*
+			 * Bit 0-1 Application-specific  identifier that can be
+			 * used to differentiate  between  different PPS table
+			 */
+			unsigned short transmission_delay_low : 2;
+			/* Bit 2-7 Reserved */
+			unsigned short pps16_reserved :6;
+			/*
+			 * Bit 8-15 Application-specific  identifier that can
+			 * be used to differentiate  between  different
+			 * PPS table
+			 */
+			unsigned short transmission_delay_high : 8;
+		};
+	};
+
+	/*
+	 * PPS 18,19 2 bytes for Decode delay.Specifies the number of pixel
+	 * times that the decoder accumulates data in its rate buffer before
+	 * starting to decode and output pixels.
+	 */
+	unsigned short initial_decode_delay;
+	union {
+		/* PPS 20, 21 */
+		unsigned short initial_scale_value;
+		struct {
+			/* Bit 0-7 Reserved */
+			unsigned short pps20_reserved :8;
+			/*
+			 * Bit 8-13 Specifies the initial rcXformScale factor
+			 * value used at the beginning of a slice
+			 */
+			unsigned short  initial_scale : 6;
+			/* Bit 14-15 Reserved */
+			unsigned short pps21_reserved :2;
+		};
+	};
+
+	/*
+	 * PPS 22, 23 Specifies the number of group times between incrementing
+	 * the rcXformScale factor at the end of a slice
+	 */
+	unsigned short scale_increment_interval;
+
+	union {
+		/* PPS 24, 25 */
+		unsigned short scale_decrement_interval;
+		struct {
+			/*
+			 * Bit  0-3 Specifies the number of group times between
+			 * decrementing the rcXformScale factor at the beginning
+			 * of a slice
+			 */
+			unsigned short scale_decrement_low : 4;
+			/* Bit 4-7 Reserved */
+			unsigned short pps24_reserved :4;
+			/*
+			 * Bit 8-15 Specifies the number of group times between
+			 * decrementing the rcXformScale factor at the beginning
+			 * of a slice
+			 */
+			unsigned short scale_decrement_high : 8;
+		};
+	};
+
+	union {
+		/* PPS 26, 27 */
+		unsigned short first_line_bpg_offset;
+		struct {
+			/* Bit 0-7 Reserved */
+			unsigned short pps26_reserved :8;
+			/*
+			 * Bit 8-12 Specifies the number of additional bits that
+			 * are allocated for each group on the first line
+			 * of a slice
+			 */
+			unsigned short bpg_offset : 5;
+			/* Bit 13-15 Reserved */
+			unsigned short pps27_reserved:3;
+		};
+	};
+
+	/*
+	 * PPS 28, 29 Specifies the number of bits (including fractional bits)
+	 * that are de-allocated for each group, for groups after the first line
+	 * of a slice. If the first line has an additional bit budget,
+	 * the additional bits that are allocated must come out of the budget
+	 * for coding the remainder of the slice
+	 */
+	unsigned short nfl_bpg_offset;
+
+	/*
+	 * PPS 30, 31 Specifies the number of bits (including fractional bits)
+	 * that are de-allocated for each group to enforce the slice constraint,
+	 * while allowing a programmable initial_offset.
+	 */
+	unsigned short slice_bpg_offset;
+	/* PPS 32, 33 */
+	unsigned short initial_offset;
+	/* PPS 34, 35 */
+	unsigned short final_offset;
+
+	union {
+		/* PPS 36 */
+		unsigned char flatness_min_qp;
+		struct {
+			/* Bit 0-5 Major version no */
+			unsigned char min_qp : 5;
+			/* Bit 0-3 Reserved */
+			unsigned char pps36_reserved :3;
+		};
+	};
+
+	union {
+		/* PPS 37 */
+		unsigned char flatness_max_qp;
+		struct {
+			/* Bit 0-5 Major version no */
+			unsigned char max_qp : 5;
+			/* Bit 0-3 Reserved */
+			unsigned char pps37_reserved :3;
+		};
+	};
+
+	/* PPS 38, 39 Specifies the number of bits within the“RC model,” */
+	unsigned short rc_model_size;
+
+	union {
+		/* PPS 40 */
+		unsigned char rc_edge_factor;
+		struct {
+			/* Bit 0-5 Major version no */
+			unsigned char edge_factor : 4;
+			/* Bit 0-3 Reserved */
+			unsigned char pps40_reserved :4;
+		};
+	};
+	union {
+		/* PPS 41 */
+		unsigned char rc_quan_incr_limit0;
+		struct {
+			/* Bit 0-5 Major version no */
+			unsigned char incr_limit0 : 5;
+			/* Bit 0-3 Reserved */
+			unsigned char pps41_reserved :3;
+		};
+	};
+
+	union {
+		/* PPS 42 */
+		unsigned char rc_quan_incr_limit1;
+		struct {
+			/* Bit 0-5 Major version no */
+			unsigned char incr_limit1 : 5;
+			/* Bit 0-3 Reserved */
+			unsigned char pps42_reserved :3;
+		};
+	};
+
+	union {
+		/* PPS 43 */
+		unsigned char rc_target_offset;
+		struct {
+			unsigned char low : 4;
+			unsigned char high : 4;
+		};
+	};
+
+	/* PPS 44 */
+	unsigned char rc_buffer_threshold0;
+	/* PPS 45 */
+	unsigned char rc_buffer_threshold1;
+	/* PPS 46 */
+	unsigned char rc_buffer_threshold2;
+	/* PPS 47 */
+	unsigned char rc_buffer_threshold3;
+	/* PPS 48 */
+	unsigned char rc_buffer_threshold4;
+	/* PPS 49 */
+	unsigned char rc_buffer_threshold5;
+	/* PPS 50 */
+	unsigned char rc_buffer_threshold6;
+	/* PPS 51 */
+	unsigned char rc_buffer_threshold7;
+	/* PPS 52 */
+	unsigned char rc_buffer_threshold8;
+	/* PPS 53 */
+	unsigned char rc_buffer_threshold9;
+	/* PPS 54 */
+	unsigned char rc_buffer_threshold10;
+	/* PPS 55 */
+	unsigned char rc_buffer_threshold11;
+	/* PPS 56 */
+	unsigned char rc_buffer_threshold12;
+	/* PPS 57 */
+	unsigned char rc_buffer_threshold13;
+
+	union {
+		/* PPS 58, 59,60, 61 */
+		unsigned long rc_range_parameter_block1;
+		struct {
+			unsigned long rc_range_parameter0 : 16;
+			unsigned long rc_range_parameter1 : 16;
+		};
+	};
+
+	union {
+		/* PPS 62, 63, 64, 65 */
+		unsigned long rc_range_parameter_block2;
+		struct {
+			unsigned long rc_range_parameter2 : 16;
+			unsigned long rc_range_parameter3 : 16;
+		};
+	};
+
+	union {
+		/* PPS 66 ,67,  68, 69 */
+		unsigned long rc_range_parameter_block3;
+		struct {
+			unsigned long rc_range_parameter4 : 16;
+			unsigned long rc_range_parameter5 : 16;
+		};
+	};
+
+	union {
+		/* PPS  70, 71, 72 ,73 */
+		unsigned long rc_range_parameter_block4;
+		struct {
+			unsigned long rc_range_parameter6 : 16;
+			unsigned long rc_range_parameter7 : 16;
+		};
+	};
+	union {
+		/* PPS  74, 75, 76, 77 */
+		unsigned long rc_range_parameter_block5;
+		struct {
+			unsigned long rc_range_parameter8 : 16;
+			unsigned long rc_range_parameter9 : 16;
+		};
+	};
+
+	union {
+		/* PPS 78, 79, 80, 81 */
+		unsigned long rc_range_parameter_block6;
+		struct {
+			unsigned long rc_range_parameter10 : 16;
+			unsigned long rc_range_parameter11 : 16;
+		};
+	};
+
+	union {
+		/* PPS 82, 83, 84, 85 */
+		unsigned long rc_range_parameter_block7;
+		struct {
+			unsigned long rc_range_parameter12 : 16;
+			unsigned long rc_range_parameter13 : 16;
+		};
+	};
+
+	union {
+		/* PPS 86,87,88,89 */
+		unsigned long rc_range_parameter_block8;
+		struct {
+			unsigned long rc_range_parameter14 : 16;
+			unsigned long pps_88_89_reserved : 16;
+		};
+	};
+
+	/* PPS 90, 91 */
+	unsigned short pps_short_90_reserved;
+	/* PPS 92, 93, 94, 95 */
+	unsigned long pps_long_92_reserved;
+	/* PPS 96, 97, 98, 99 */
+	unsigned long pps_long_96_reserved;
+	/* PPS 100, 101, 102 , 103 */
+	unsigned long pps_long_100_reserved;
+	/* PPS 104, 105, 106 , 107 */
+	unsigned long pps_long_104_reserved;
+	/* PPS 108, 109, 110 , 111 */
+	unsigned long pps_long_108_reserved;
+	/* PPS 112, 113, 114 , 115 */
+	unsigned long pps_long_112_reserved;
+	/* PPS 116, 117, 118 , 119 */
+	unsigned long pps_long_116_reserved;
+	/* PPS 120, 121, 122 , 123 */
+	unsigned long pps_long_120_reserved;
+	/* PPS 124, 125, 126 , 127 */
+	unsigned long pps_long_124_reserved;
+};
+
 /* DSC Configuration structure */
 #define NUM_BUF_RANGES		15
 
-- 
1.9.1

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[PATCH 06/10] drm/i915: Populate PPS Secondary Data Pkt for Sink

[Gaurav K Singh]

Vesa Display Stream Compression defines Picture Parameter Set(PPS),
which encoders must communicate to decoders. PPS is encapsulated
in 128 bytes(PS0 through PS127). The PPS contains parameters that
the decoder needs to correctly decode pictures. Correct decoding
requires that an identical PPS be used at the encoder(@Source)
and decoder(@Sink).

The PPS is not considered to be part of any picture or slice budget
within the DSC coding algorithm. This patch populates PPS parameters
that needs to be transmitted to the Sink device.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/i915/intel_vdsc.c | 207 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 207 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
index 5eef551f0d09..536f417624cb 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -48,6 +48,9 @@ enum COLUMN_INDEX_BPC {
 	MAX_COLUMN_INDEX
 };
 
+#define SWAP_TWO_BYTES(x) (unsigned short)(((x >> 8) & 0xFF) | \
+						((x << 8) & 0xFF00))
+
 #define TWOS_COMPLEMENT(x) (unsigned char)((~(x) + 1) & 0x3F)
 
 /* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
@@ -560,3 +563,207 @@ void intel_dp_compute_dsc_parameters(struct intel_dp *intel_dp)
 	intel_compute_rc_parameters(intel_dp);
 
 }
+
+void populate_pps_sdp_for_sink(struct intel_encoder *encoder,
+				struct intel_crtc_state *crtc_state,
+				struct picture_parameters_set *pps_params)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+	struct vdsc_config *vdsc_cfg  =  &(intel_dp->compr_params.dsc_cfg);
+	unsigned long rc_range_parameters[NUM_BUF_RANGES];
+	unsigned char i = 0;
+
+	/* PPS0 */
+	pps_params->major = (unsigned char)vdsc_cfg->dsc_version_major;
+	pps_params->minor = (unsigned char)vdsc_cfg->dsc_version_minor;
+
+	/* PPS1, PPS2 */
+	pps_params->picture_params_set_identifier = 0;
+
+	/* PPS3 */
+	pps_params->line_buffer_depth = (unsigned char)vdsc_cfg->line_buf_depth;
+	pps_params->bits_per_component =
+				(unsigned char)vdsc_cfg->bits_per_component;
+
+	/* PPS4,5 */
+	pps_params->block_prediction_enable =
+				(unsigned short)vdsc_cfg->block_pred_enable;
+	pps_params->convert_RGB = (unsigned short)vdsc_cfg->convert_rgb;
+	pps_params->enable422 = (unsigned short)vdsc_cfg->enable422;
+	pps_params->vbr_mode = (unsigned short)vdsc_cfg->vbr_enable;
+	pps_params->bpp_low = (unsigned short)(
+				(vdsc_cfg->bits_per_pixel >> 8) & 0x3);
+	pps_params->bpp_high = (unsigned short)(vdsc_cfg->bits_per_pixel &
+									0xFF);
+
+	/* The PPS structure is stored as per our hardware registers which
+	 * are in little endian. When a value is assigned to a variable,
+	 * Intel systems stores data in little endian.
+	 * For e.g UINT16 a = 0x1234;
+	 * 0x34 is stored at lower address followed by 0x12.
+	 * Though, PPS packet to the panel must have big endian format for
+	 * data spanning 2 bytes. According to that logic, swap the
+	 * fields of the PPS packets that span more than one byte.
+	 */
+
+	/* PPS6,7 */
+	pps_params->picture_height = SWAP_TWO_BYTES(vdsc_cfg->pic_height);
+
+	/* PPS8,9 */
+	pps_params->picture_width = SWAP_TWO_BYTES(vdsc_cfg->pic_width);
+
+	/* PPS10,11 */
+	pps_params->slice_height = SWAP_TWO_BYTES(vdsc_cfg->slice_height);
+
+	/* PPS12,13 */
+	pps_params->slice_width = SWAP_TWO_BYTES(vdsc_cfg->slice_width);
+
+	/* PPS14,15 */
+	pps_params->chunk_size = SWAP_TWO_BYTES(vdsc_cfg->chunk_size);
+
+	/* PPS15,16 */
+	pps_params->transmission_delay_low = (unsigned short)
+					((vdsc_cfg->initial_xmit_delay >> 8) &
+					0x3); //[9:8]
+	pps_params->transmission_delay_high = (unsigned short)
+					(vdsc_cfg->initial_xmit_delay & 0xFF);
+
+	/* PPS18,19 */
+	pps_params->initial_decode_delay =
+			SWAP_TWO_BYTES(vdsc_cfg->initial_dec_delay);
+
+	/* PPS20,21 */
+	pps_params->initial_scale =
+				(unsigned short)vdsc_cfg->initial_scale_value;
+
+	/* PPS22,23 */
+	pps_params->scale_increment_interval =
+			SWAP_TWO_BYTES(vdsc_cfg->scale_increment_interval);
+
+	/* PPS24,25 */
+	pps_params->scale_decrement_low = (unsigned short)(
+			(vdsc_cfg->scale_decrement_interval >> 8) & 0xF);
+	pps_params->scale_decrement_high = (unsigned short)(
+				vdsc_cfg->scale_decrement_interval & 0xFF);
+
+	/* PPS26,27 */
+	pps_params->bpg_offset = (unsigned short)vdsc_cfg->first_line_bpg_Ofs;
+
+	/* PPS28,29 */
+	pps_params->nfl_bpg_offset = SWAP_TWO_BYTES(vdsc_cfg->nfl_bpg_offset);
+
+	/* PPS30,31 */
+	pps_params->slice_bpg_offset =
+				SWAP_TWO_BYTES(vdsc_cfg->slice_bpg_offset);
+
+	/* PPS32,33 */
+	pps_params->initial_offset = SWAP_TWO_BYTES(vdsc_cfg->initial_offset);
+
+	/* PPS34,35 */
+	pps_params->final_offset = SWAP_TWO_BYTES(vdsc_cfg->final_offset);
+
+	/* PPS36 */
+	pps_params->flatness_min_qp = (unsigned char)vdsc_cfg->flatness_minQp;
+
+	/* PPS37 */
+	pps_params->flatness_max_qp = (unsigned char)vdsc_cfg->flatness_maxQp;
+
+	/* PPS38,39 */
+	pps_params->rc_model_size = SWAP_TWO_BYTES(vdsc_cfg->rc_model_size);
+
+	/* PPS40 */
+	pps_params->edge_factor = (unsigned char)vdsc_cfg->rc_edge_factor;
+
+	/* PPS41 */
+	pps_params->incr_limit0 = (unsigned char)vdsc_cfg->rc_quant_incr_limit0;
+
+	/* PPS42 */
+	pps_params->incr_limit1 = (unsigned char)vdsc_cfg->rc_quant_incr_limit1;
+
+	/* PPS43 */
+	pps_params->low = (unsigned char)vdsc_cfg->rc_tgt_offset_low;
+	pps_params->high = (unsigned char)vdsc_cfg->rc_tgt_offset_high;
+
+	/* PPS44 to PPS57 */
+	pps_params->rc_buffer_threshold0 =
+				(unsigned char)vdsc_cfg->rc_buf_thresh[0];
+	pps_params->rc_buffer_threshold1 =
+				(unsigned char)vdsc_cfg->rc_buf_thresh[1];
+	pps_params->rc_buffer_threshold2 =
+				(unsigned char)vdsc_cfg->rc_buf_thresh[2];
+	pps_params->rc_buffer_threshold3 =
+				(unsigned char)vdsc_cfg->rc_buf_thresh[3];
+	pps_params->rc_buffer_threshold4 =
+				(unsigned char)vdsc_cfg->rc_buf_thresh[4];
+	pps_params->rc_buffer_threshold5 =
+				(unsigned char)vdsc_cfg->rc_buf_thresh[5];
+	pps_params->rc_buffer_threshold6 =
+				(unsigned char)vdsc_cfg->rc_buf_thresh[6];
+	pps_params->rc_buffer_threshold7 =
+				(unsigned char)vdsc_cfg->rc_buf_thresh[7];
+	pps_params->rc_buffer_threshold8 =
+				(unsigned char)vdsc_cfg->rc_buf_thresh[8];
+	pps_params->rc_buffer_threshold9 =
+				(unsigned char)vdsc_cfg->rc_buf_thresh[9];
+	pps_params->rc_buffer_threshold10 =
+				(unsigned char)vdsc_cfg->rc_buf_thresh[10];
+	pps_params->rc_buffer_threshold11 =
+				(unsigned char)vdsc_cfg->rc_buf_thresh[11];
+	pps_params->rc_buffer_threshold12 =
+				(unsigned char)vdsc_cfg->rc_buf_thresh[12];
+	pps_params->rc_buffer_threshold13 =
+				(unsigned char)vdsc_cfg->rc_buf_thresh[13];
+
+	/*
+	 * For each RC range parameter, we need to do below steps:
+	 * For source programming the order is
+	 * ((offset << 10) | (max << 5) | min))
+	 * For sink programming the order is
+	 * ((min << 11) | (max << 6) | offset))
+	 */
+	for (i = 0; i < NUM_BUF_RANGES; i++) {
+		rc_range_parameters[i] = (unsigned short)(
+		(vdsc_cfg->rc_range_params[i].range_min_qp << 11) |
+		(vdsc_cfg->rc_range_params[i].range_max_qp << 6) |
+		(vdsc_cfg->rc_range_params[i].range_bpg_offset));
+	}
+
+	/*
+	 * Also while sending to the sink, we need to send in big endian order
+	 * So, swap the two bytes of data after above operations.
+	 * NOTE: The order of the min,max and offset field is not explicitly
+	 * called out in DSC spec yet. We are following this order based on
+	 * the VESA C Model implementation and the expectations from panel
+	 * and Pipe 2D model.
+	 */
+	pps_params->rc_range_parameter0 =
+					SWAP_TWO_BYTES(rc_range_parameters[0]);
+	pps_params->rc_range_parameter1 =
+					SWAP_TWO_BYTES(rc_range_parameters[1]);
+	pps_params->rc_range_parameter2 =
+					SWAP_TWO_BYTES(rc_range_parameters[2]);
+	pps_params->rc_range_parameter3 =
+					SWAP_TWO_BYTES(rc_range_parameters[3]);
+	pps_params->rc_range_parameter4 =
+					SWAP_TWO_BYTES(rc_range_parameters[4]);
+	pps_params->rc_range_parameter5 =
+					SWAP_TWO_BYTES(rc_range_parameters[5]);
+	pps_params->rc_range_parameter6 =
+					SWAP_TWO_BYTES(rc_range_parameters[6]);
+	pps_params->rc_range_parameter7 =
+					SWAP_TWO_BYTES(rc_range_parameters[7]);
+	pps_params->rc_range_parameter8 =
+					SWAP_TWO_BYTES(rc_range_parameters[8]);
+	pps_params->rc_range_parameter9 =
+					SWAP_TWO_BYTES(rc_range_parameters[9]);
+	pps_params->rc_range_parameter10 =
+					SWAP_TWO_BYTES(rc_range_parameters[10]);
+	pps_params->rc_range_parameter11 =
+					SWAP_TWO_BYTES(rc_range_parameters[11]);
+	pps_params->rc_range_parameter12 =
+					SWAP_TWO_BYTES(rc_range_parameters[12]);
+	pps_params->rc_range_parameter13 =
+					SWAP_TWO_BYTES(rc_range_parameters[13]);
+	pps_params->rc_range_parameter14 =
+					SWAP_TWO_BYTES(rc_range_parameters[14]);
+}
-- 
1.9.1

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[PATCH 07/10] drm: i915: Define VDSC regs and DSC params

[Gaurav K Singh]

Defining all mmio regs from Gen9 onwards to be used
for VDSC programming.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h |  58 ++++++
 drivers/gpu/drm/i915/i915_reg.h | 448 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 506 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 760b97ec89ff..4073c98a267f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1169,8 +1169,66 @@ struct picture_parameters_set {
 	unsigned long pps_long_124_reserved;
 };
 
+/* Secondary Data Packet Header */
+struct sdp_header {
+	/* SDP ID */
+	unsigned char sdp_id;
+	/* SDP Type */
+	unsigned char sdp_type;
+	union {
+		unsigned char sdp_byte1;
+		struct {
+			unsigned char revision_no :5;
+			unsigned char reserved1 :3;
+		};
+	};
+
+	union {
+		unsigned char sdp_byte2;
+		struct {
+			unsigned char num_of_valid_data_bytes : 5;
+			unsigned char reserved2 : 3;
+		};
+	};
+};
+
+union pps_sdp {
+	struct {
+		/* VS header data */
+		struct sdp_header secondary_data_packet_header;
+		/* PPS Payload */
+		struct picture_parameters_set pps_payload;
+	};
+};
+
+/* There are two instances of VDSC engines */
+#define DSC0		0
+#define DSC1		1
+
+/* Dislay Compression Units */
+enum dsc_types {
+	/*  DSC_0 engine for eDP/MIPIDSI */
+	DSC_A = 0,
+	/* DSC_1 engine for eDP/MIPI DSI */
+	DSC_C = 1,
+	/* Applicable from Gen11.5 */
+	PIPEA_DSC_0 = 2,
+	PIPEA_DSC_1 = 3,
+	PIPEB_DSC_0 = 4,
+	PIPEB_DSC_1 = 5,
+	PIPEC_DSC_0 = 6,
+	PIPEC_DSC_1 = 7,
+	PIPED_DSC_0 = 8,
+	PIPED_DSC_1 = 9,
+	MAX_DSC_TYPES,
+	DSC_UNDEFINED = 127
+};
+
 /* DSC Configuration structure */
 #define NUM_BUF_RANGES		15
+/* Size in Bytes */
+#define SDP_HEADER_SIZE		4
+#define PPS_PAYLOAD_SIZE	128
 
 /* Configuration for a single Rate Control model range */
 struct rc_range_parameters {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0fc24ab3a8ca..7d0574cf6e94 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9672,4 +9672,452 @@ enum skl_power_gate {
 						 _ICL_PHY_MISC_B)
 #define  ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN	(1 << 23)
 
+/* VDSC  regs */
+
+#define DSS_CONTROL1				_MMIO(0x67400)
+#define JOINER_ENABLE				(1 << 30)
+#define SPLITTER_ENABLE				(1 << 31)
+
+#define DSS_CONTROL2				_MMIO(0x67404)
+#define LEFT_BRANCH_VDSC_ENABLE			(1 << 31)
+#define RIGHT_BRANCH_VDSC_ENABLE		(1 << 15)
+
+#define PIPE_DSS_CTL1_PB			_MMIO(0x78200)
+#define PIPE_DSS_CTL2_PB			_MMIO(0x78204)
+#define PIPE_DSS_CTL1_PC			_MMIO(0x78400)
+#define PIPE_DSS_CTL2_PC			_MMIO(0x78404)
+
+#define DSCA_PICTURE_PARAMETER_SET_0		_MMIO(0x6B200)
+#define DSCA_PICTURE_PARAMETER_SET_1		_MMIO(0x6B204)
+#define DSCA_PICTURE_PARAMETER_SET_2		_MMIO(0x6B208)
+#define DSCA_PICTURE_PARAMETER_SET_3		_MMIO(0x6B20C)
+#define DSCA_PICTURE_PARAMETER_SET_4		_MMIO(0x6B210)
+#define DSCA_PICTURE_PARAMETER_SET_5		_MMIO(0x6B214)
+#define DSCA_PICTURE_PARAMETER_SET_6		_MMIO(0x6B218)
+#define DSCA_PICTURE_PARAMETER_SET_7		_MMIO(0x6B21C)
+#define DSCA_PICTURE_PARAMETER_SET_8		_MMIO(0x6B220)
+#define DSCA_PICTURE_PARAMETER_SET_9		_MMIO(0x6B224)
+#define DSCA_PICTURE_PARAMETER_SET_10		_MMIO(0x6B228)
+#define DSCA_PICTURE_PARAMETER_SET_11		_MMIO(0x6B22C)
+#define DSCA_PICTURE_PARAMETER_SET_12		_MMIO(0x6B260)
+#define DSCA_PICTURE_PARAMETER_SET_13		_MMIO(0x6B264)
+#define DSCA_PICTURE_PARAMETER_SET_14		_MMIO(0x6B268)
+#define DSCA_PICTURE_PARAMETER_SET_15		_MMIO(0x6B26C)
+#define DSCA_PICTURE_PARAMETER_SET_16		_MMIO(0x6B270)
+
+#define DSCC_PICTURE_PARAMETER_SET_0		_MMIO(0x6BA00)
+#define DSCC_PICTURE_PARAMETER_SET_1		_MMIO(0x6BA04)
+#define DSCC_PICTURE_PARAMETER_SET_2		_MMIO(0x6BA08)
+#define DSCC_PICTURE_PARAMETER_SET_3		_MMIO(0x6BA0C)
+#define DSCC_PICTURE_PARAMETER_SET_4		_MMIO(0x6BA10)
+#define DSCC_PICTURE_PARAMETER_SET_5		_MMIO(0x6BA14)
+#define DSCC_PICTURE_PARAMETER_SET_6		_MMIO(0x6BA18)
+#define DSCC_PICTURE_PARAMETER_SET_7		_MMIO(0x6BA1C)
+#define DSCC_PICTURE_PARAMETER_SET_8		_MMIO(0x6BA20)
+#define DSCC_PICTURE_PARAMETER_SET_9		_MMIO(0x6BA24)
+#define DSCC_PICTURE_PARAMETER_SET_10		_MMIO(0x6BA28)
+#define DSCC_PICTURE_PARAMETER_SET_11		_MMIO(0x6BA2C)
+#define DSCC_PICTURE_PARAMETER_SET_12		_MMIO(0x6BA60)
+#define DSCC_PICTURE_PARAMETER_SET_13		_MMIO(0x6BA64)
+#define DSCC_PICTURE_PARAMETER_SET_14		_MMIO(0x6BA68)
+#define DSCC_PICTURE_PARAMETER_SET_15		_MMIO(0x6BA6C)
+#define DSCC_PICTURE_PARAMETER_SET_16		_MMIO(0x6BA70)
+
+#define DSC0_PICTURE_PARAMETER_SET_0_PB		_MMIO(0x78270)
+#define DSC0_PICTURE_PARAMETER_SET_1_PB		_MMIO(0x78274)
+#define DSC0_PICTURE_PARAMETER_SET_2_PB		_MMIO(0x78278)
+#define DSC0_PICTURE_PARAMETER_SET_3_PB		_MMIO(0x7827C)
+#define DSC0_PICTURE_PARAMETER_SET_4_PB		_MMIO(0x78280)
+#define DSC0_PICTURE_PARAMETER_SET_5_PB		_MMIO(0x78284)
+#define DSC0_PICTURE_PARAMETER_SET_6_PB		_MMIO(0x78288)
+#define DSC0_PICTURE_PARAMETER_SET_7_PB		_MMIO(0x7828C)
+#define DSC0_PICTURE_PARAMETER_SET_8_PB		_MMIO(0x78290)
+#define DSC0_PICTURE_PARAMETER_SET_9_PB		_MMIO(0x78294)
+#define DSC0_PICTURE_PARAMETER_SET_10_PB	_MMIO(0x78298)
+#define DSC0_PICTURE_PARAMETER_SET_11_PB	_MMIO(0x7829C)
+#define DSC0_PICTURE_PARAMETER_SET_12_PB	_MMIO(0x782A0)
+#define DSC0_PICTURE_PARAMETER_SET_13_PB	_MMIO(0x782A4)
+#define DSC0_PICTURE_PARAMETER_SET_14_PB	_MMIO(0x782A8)
+#define DSC0_PICTURE_PARAMETER_SET_15_PB	_MMIO(0x782AC)
+#define DSC0_PICTURE_PARAMETER_SET_16_PB	_MMIO(0x782B0)
+
+#define DSC1_PICTURE_PARAMETER_SET_0_PB		_MMIO(0x78370)
+#define DSC1_PICTURE_PARAMETER_SET_1_PB		_MMIO(0x78374)
+#define DSC1_PICTURE_PARAMETER_SET_2_PB		_MMIO(0x78378)
+#define DSC1_PICTURE_PARAMETER_SET_3_PB		_MMIO(0x7837C)
+#define DSC1_PICTURE_PARAMETER_SET_4_PB		_MMIO(0x78380)
+#define DSC1_PICTURE_PARAMETER_SET_5_PB		_MMIO(0x78384)
+#define DSC1_PICTURE_PARAMETER_SET_6_PB		_MMIO(0x78388)
+#define DSC1_PICTURE_PARAMETER_SET_7_PB		_MMIO(0x7838C)
+#define DSC1_PICTURE_PARAMETER_SET_8_PB		_MMIO(0x78390)
+#define DSC1_PICTURE_PARAMETER_SET_9_PB		_MMIO(0x78394)
+#define DSC1_PICTURE_PARAMETER_SET_10_PB	_MMIO(0x78398)
+#define DSC1_PICTURE_PARAMETER_SET_11_PB	_MMIO(0x7839C)
+#define DSC1_PICTURE_PARAMETER_SET_12_PB	_MMIO(0x783A0)
+#define DSC1_PICTURE_PARAMETER_SET_13_PB	_MMIO(0x783A4)
+#define DSC1_PICTURE_PARAMETER_SET_14_PB	_MMIO(0x783A8)
+#define DSC1_PICTURE_PARAMETER_SET_15_PB	_MMIO(0x783AC)
+#define DSC1_PICTURE_PARAMETER_SET_16_PB	_MMIO(0x783B0)
+
+#define DSC0_PICTURE_PARAMETER_SET_0_PC		_MMIO(0x78470)
+#define DSC0_PICTURE_PARAMETER_SET_1_PC		_MMIO(0x78474)
+#define DSC0_PICTURE_PARAMETER_SET_2_PC		_MMIO(0x78478)
+#define DSC0_PICTURE_PARAMETER_SET_3_PC		_MMIO(0x7847C)
+#define DSC0_PICTURE_PARAMETER_SET_4_PC		_MMIO(0x78480)
+#define DSC0_PICTURE_PARAMETER_SET_5_PC		_MMIO(0x78484)
+#define DSC0_PICTURE_PARAMETER_SET_6_PC		_MMIO(0x78488)
+#define DSC0_PICTURE_PARAMETER_SET_7_PC		_MMIO(0x7848C)
+#define DSC0_PICTURE_PARAMETER_SET_8_PC		_MMIO(0x78490)
+#define DSC0_PICTURE_PARAMETER_SET_9_PC		_MMIO(0x78494)
+#define DSC0_PICTURE_PARAMETER_SET_10_PC	_MMIO(0x78498)
+#define DSC0_PICTURE_PARAMETER_SET_11_PC	_MMIO(0x7849C)
+#define DSC0_PICTURE_PARAMETER_SET_12_PC	_MMIO(0x784A0)
+#define DSC0_PICTURE_PARAMETER_SET_13_PC	_MMIO(0x784A4)
+#define DSC0_PICTURE_PARAMETER_SET_14_PC	_MMIO(0x784A8)
+#define DSC0_PICTURE_PARAMETER_SET_15_PC	_MMIO(0x784AC)
+#define DSC0_PICTURE_PARAMETER_SET_16_PC	_MMIO(0x784B0)
+
+#define DSC1_PICTURE_PARAMETER_SET_0_PC		_MMIO(0x78570)
+#define DSC1_PICTURE_PARAMETER_SET_1_PC		_MMIO(0x78574)
+#define DSC1_PICTURE_PARAMETER_SET_2_PC		_MMIO(0x78578)
+#define DSC1_PICTURE_PARAMETER_SET_3_PC		_MMIO(0x7857C)
+#define DSC1_PICTURE_PARAMETER_SET_4_PC		_MMIO(0x78580)
+#define DSC1_PICTURE_PARAMETER_SET_5_PC		_MMIO(0x78584)
+#define DSC1_PICTURE_PARAMETER_SET_6_PC		_MMIO(0x78588)
+#define DSC1_PICTURE_PARAMETER_SET_7_PC		_MMIO(0x7858C)
+#define DSC1_PICTURE_PARAMETER_SET_8_PC		_MMIO(0x78590)
+#define DSC1_PICTURE_PARAMETER_SET_9_PC		_MMIO(0x78594)
+#define DSC1_PICTURE_PARAMETER_SET_10_PC	_MMIO(0x78598)
+#define DSC1_PICTURE_PARAMETER_SET_11_PC	_MMIO(0x7859C)
+#define DSC1_PICTURE_PARAMETER_SET_12_PC	_MMIO(0x785A0)
+#define DSC1_PICTURE_PARAMETER_SET_13_PC	_MMIO(0x785A4)
+#define DSC1_PICTURE_PARAMETER_SET_14_PC	_MMIO(0x785A8)
+#define DSC1_PICTURE_PARAMETER_SET_15_PC	_MMIO(0x785AC)
+#define DSC1_PICTURE_PARAMETER_SET_16_PC	_MMIO(0x785B0)
+
+#define DSCA_RC_BUF_THRESH_0_0			_MMIO(0x6B230)
+#define DSCA_RC_BUF_THRESH_0_1			_MMIO(0x6B234)
+#define DSCA_RC_BUF_THRESH_1_0			_MMIO(0x6B238)
+#define DSCA_RC_BUF_THRESH_1_1			_MMIO(0x6B23C)
+
+#define DSCC_RC_BUF_THRESH_0_0			_MMIO(0x6BA30)
+#define DSCC_RC_BUF_THRESH_0_1			_MMIO(0x6BA34)
+#define DSCC_RC_BUF_THRESH_1_0			_MMIO(0x6BA38)
+#define DSCC_RC_BUF_THRESH_1_1			_MMIO(0x6BA3C)
+
+#define DSC0_RC_BUF_THRESH_0_0_PB		_MMIO(0x78254)
+#define DSC0_RC_BUF_THRESH_0_1_PB		_MMIO(0x78258)
+#define DSC1_RC_BUF_THRESH_0_0_PB		_MMIO(0x78354)
+#define DSC1_RC_BUF_THRESH_0_1_PB		_MMIO(0x78358)
+#define DSC0_RC_BUF_THRESH_0_0_PC		_MMIO(0x78454)
+#define DSC0_RC_BUF_THRESH_0_1_PC		_MMIO(0x78458)
+#define DSC1_RC_BUF_THRESH_0_0_PC		_MMIO(0x78554)
+#define DSC1_RC_BUF_THRESH_0_1_PC		_MMIO(0x78558)
+
+#define DSC0_RC_BUF_THRESH_1_0_PB		_MMIO(0x7825C)
+#define DSC0_RC_BUF_THRESH_1_1_PB		_MMIO(0x78260)
+#define DSC1_RC_BUF_THRESH_1_0_PB		_MMIO(0x7835C)
+#define DSC1_RC_BUF_THRESH_1_1_PB		_MMIO(0x78360)
+#define DSC0_RC_BUF_THRESH_1_0_PC		_MMIO(0x7845C)
+#define DSC0_RC_BUF_THRESH_1_1_PC		_MMIO(0x78460)
+#define DSC1_RC_BUF_THRESH_1_0_PC		_MMIO(0x7855C)
+#define DSC1_RC_BUF_THRESH_1_1_PC		_MMIO(0x78560)
+
+#define DSCA_RC_RANGE_PARAMETERS_0_0		_MMIO(0x6B240)
+#define DSCA_RC_RANGE_PARAMETERS_0_1		_MMIO(0x6B244)
+#define DSCA_RC_RANGE_PARAMETERS_1_0		_MMIO(0x6B248)
+#define DSCA_RC_RANGE_PARAMETERS_1_1		_MMIO(0x6B24C)
+#define DSCA_RC_RANGE_PARAMETERS_2_0		_MMIO(0x6B250)
+#define DSCA_RC_RANGE_PARAMETERS_2_1		_MMIO(0x6B254)
+#define DSCA_RC_RANGE_PARAMETERS_3_0		_MMIO(0x6B258)
+#define DSCA_RC_RANGE_PARAMETERS_3_1		_MMIO(0x6B25C)
+
+#define DSCC_RC_RANGE_PARAMETERS_0_0		_MMIO(0x6BA40)
+#define DSCC_RC_RANGE_PARAMETERS_0_1		_MMIO(0x6BA44)
+#define DSCC_RC_RANGE_PARAMETERS_1_0		_MMIO(0x6BA48)
+#define DSCC_RC_RANGE_PARAMETERS_1_1		_MMIO(0x6BA4C)
+#define DSCC_RC_RANGE_PARAMETERS_2_0		_MMIO(0x6BA50)
+#define DSCC_RC_RANGE_PARAMETERS_2_1		_MMIO(0x6BA54)
+#define DSCC_RC_RANGE_PARAMETERS_3_0		_MMIO(0x6BA58)
+#define DSCC_RC_RANGE_PARAMETERS_3_1		_MMIO(0x6BA5C)
+
+#define VIDEO_DIP_CTL_A				_MMIO(0x60200)
+#define VIDEO_DIP_CTL_B				_MMIO(0x61200)
+#define VIDEO_DIP_CTL_C				_MMIO(0x62200)
+#define VIDEO_DIP_CTL_EDP			_MMIO(0x6F200)
+#define VDIP_ENABLE_VSC				(1 << 20)
+#define VDIP_ENABLE_PPS				(1 << 24)
+#define VIDEO_DIP_PPS_DATA_EDP_REG		0x6F350
+
+// HDMI Video-related Data Island Packet Data
+#define VIDEO_DIP_DRM_DATA_TRANSA_REG		0x60440
+#define VIDEO_DIP_DRM_DATA_TRANSB_REG		0x61440
+#define VIDEO_DIP_DRM_DATA_TRANSC_REG		0x62440
+
+// VDSC PPS data
+#define VIDEO_DIP_DATA_PPS_TRANSEDP_REG		0x6F350
+
+#define DSC_CHICKEN_1_A				_MMIO(0x6B280)
+#define DSC_CHICKEN_1_C				_MMIO(0x6BA80)
+
+struct intel_dsc_regs {
+	i915_reg_t dsc_picture_params0;
+	i915_reg_t dsc_picture_params1;
+	i915_reg_t dsc_picture_params2;
+	i915_reg_t dsc_picture_params3;
+	i915_reg_t dsc_picture_params4;
+	i915_reg_t dsc_picture_params5;
+	i915_reg_t dsc_picture_params6;
+	i915_reg_t dsc_picture_params7;
+	i915_reg_t dsc_picture_params8;
+	i915_reg_t dsc_picture_params9;
+	i915_reg_t dsc_picture_params10;
+	i915_reg_t dsc_picture_params11;
+	i915_reg_t dsc_picture_params12;
+	i915_reg_t dsc_picture_params13;
+	i915_reg_t dsc_picture_params14;
+	i915_reg_t dsc_picture_params15;
+	i915_reg_t dsc_picture_params16;
+	i915_reg_t dsc_rc_buff_thresh0_0;
+	i915_reg_t dsc_rc_buff_thresh0_1;
+	i915_reg_t dsc_rc_buff_thresh1_0;
+	i915_reg_t dsc_rc_buff_thresh1_1;
+	i915_reg_t dsc_rc_range0_0;
+	i915_reg_t dsc_rc_range0_1;
+	i915_reg_t dsc_rc_range1_0;
+	i915_reg_t dsc_rc_range1_1;
+	i915_reg_t dsc_rc_range2_0;
+	i915_reg_t dsc_rc_range2_1;
+	i915_reg_t dsc_rc_range3_0;
+	i915_reg_t dsc_rc_range3_1;
+	i915_reg_t dss_ctrl1_reg;
+	i915_reg_t dss_ctrl2_reg;
+	i915_reg_t dip_ctrl_reg;
+	unsigned int dip_pps_data_ctrl_reg;
+};
+
+union DSC_PICTURE_PARAMETER_SET_0_BXT {
+	struct {
+		unsigned int dsc_version_major : 4;
+		unsigned int dsc_version_minor : 4;
+		unsigned int bits_per_component : 4;
+		unsigned int line_buf_depth : 4;
+		unsigned int block_pred_enable : 1;
+		unsigned int convert_rgb : 1;
+		unsigned int enable_422  : 1;
+		unsigned int vbr_enable  : 1;
+		unsigned int allow_double_buffer_update_disable : 1;
+		unsigned int reserved: 11;
+	};
+	unsigned int value;
+};
+
+union DSC_PICTURE_PARAMETER_SET_1_BXT {
+	struct {
+		unsigned int bits_per_pixel : 10;
+		unsigned int reserved: 22;
+	};
+	unsigned int value;
+};
+
+union DSC_PICTURE_PARAMETER_SET_2_BXT {
+	struct {
+		unsigned int pic_height : 16;
+		unsigned int pic_width  : 16;
+	};
+	unsigned int value;
+};
+
+union DSC_PICTURE_PARAMETER_SET_3_BXT {
+	struct {
+
+	/* This defines the height of the slice in number of pixels. */
+	unsigned int slice_height : 16;
+
+	/* This defines the width of the slice in number of pixels. */
+	unsigned int slice_width  : 16;
+	};
+	unsigned int value;
+};
+
+union DSC_PICTURE_PARAMETER_SET_4_BXT {
+	struct {
+		unsigned int initial_xmit_delay : 10;
+		unsigned int reserved : 6;
+		unsigned int initial_dec_delay : 16;
+	};
+	unsigned int value;
+};
+
+union DSC_PICTURE_PARAMETER_SET_5_BXT {
+	struct {
+		unsigned int scale_increment_interval : 16;
+		unsigned int scale_decrement_interval   : 12;
+		unsigned int reserved: 4;
+	};
+	unsigned int value;
+};
+
+union DSC_PICTURE_PARAMETER_SET_6_BXT {
+	struct {
+		unsigned int initial_scale_value : 6;
+		unsigned int reserved_1 : 2;
+		unsigned int first_line_bpg_offset : 5;
+		unsigned int reserved_2: 3;
+		unsigned int flatness_min_qp : 5;
+		unsigned int reserved_3 : 3;
+		unsigned int flatness_max_qp : 5;
+		unsigned int reserved: 3;
+	};
+	unsigned int value;
+};
+
+union DSC_PICTURE_PARAMETER_SET_7_BXT {
+	struct {
+		unsigned int slice_bpg_offset : 16;
+		unsigned int nfl_bpg_offset : 16;
+	};
+	unsigned int value;
+};
+
+union DSC_PICTURE_PARAMETER_SET_8_BXT {
+	struct {
+		unsigned int final_offset : 16;
+		unsigned int initial_offset : 16;
+	};
+	unsigned int value;
+};
+
+union DSC_PICTURE_PARAMETER_SET_9_BXT {
+	struct {
+		unsigned int rc_model_size : 16;
+		unsigned int rc_edge_factor  : 4;
+		unsigned int reserved : 12;
+	};
+	unsigned int value;
+};
+
+union DSC_PICTURE_PARAMETER_SET_10_BXT {
+	struct {
+		unsigned int rc_quant_incr_limit0 : 5;
+		unsigned int reserved_1 : 3;
+		unsigned int rc_quant_incr_limit1 : 5;
+		unsigned int reserved_2 : 3;
+		unsigned int rc_tgt_offset_hi : 4;
+		unsigned int rc_tgt_offset_lo : 4;
+		unsigned int reserved_3 : 8;
+	};
+	unsigned int value;
+};
+
+union DSC_PICTURE_PARAMETER_SET_16_BXT {
+	struct {
+		unsigned int slice_chunk_size : 16;
+		unsigned int slice_per_line : 3;
+		unsigned int reserved : 1;
+		unsigned int slice_row_per_frame : 12;
+	};
+	unsigned int value;
+};
+
+
+union DSC_RC_BUF_THRESH_0_BXT {
+	struct {
+		unsigned int rc_buf_thresh_0 : 8;
+		unsigned int rc_buf_thresh_1 : 8;
+		unsigned int rc_buf_thresh_2 : 8;
+		unsigned int rc_buf_thresh_3 : 8;
+		unsigned int rc_buf_thresh_4 : 8;
+		unsigned int rc_buf_thresh_5 : 8;
+		unsigned int rc_buf_thresh_6 : 8;
+		unsigned int rc_buf_thresh_7 : 8;
+	};
+	unsigned int value[2];
+};
+
+union DSC_RC_BUF_THRESH_1_BXT {
+	struct {
+		unsigned int rc_buf_thresh_8 : 8;
+		unsigned int rc_buf_thresh_9 : 8;
+		unsigned int rc_buf_thresh_10 : 8;
+		unsigned int rc_buf_thresh_11 : 8;
+		unsigned int rc_buf_thresh_12 : 8;
+		unsigned int rc_buf_thresh_13 : 8;
+		unsigned int reserved : 16;
+	};
+	unsigned int value[2];
+};
+
+union DSC_RC_RANGE_PARAMETERS_0_BXT {
+	struct {
+		unsigned int rc_min_qp_0 : 5;
+		unsigned int rc_max_qp_0 : 5;
+		unsigned int rc_bpg_offset_0 : 6;
+		unsigned int rc_min_qp_1 : 5;
+		unsigned int rc_max_qp_1 : 5;
+		unsigned int rc_bpg_offset_1 : 6;
+		unsigned int rc_min_qp_2 : 5;
+		unsigned int rc_max_qp_2 : 5;
+		unsigned int rc_bpg_offset_2 : 6;
+		unsigned int rc_min_qp_3 : 5;
+		unsigned int rc_max_qp_3 : 5;
+		unsigned int rc_bpg_offset_3 : 6;
+	};
+	unsigned int value[2];
+};
+
+union DSC_RC_RANGE_PARAMETERS_1_BXT {
+	struct {
+		unsigned int rc_min_qp_4 : 5;
+		unsigned int rc_max_qp_4 : 5;
+		unsigned int rc_bpg_offset_4 : 6;
+		unsigned int rc_min_qp_5 : 5;
+		unsigned int rc_max_qp_5 : 5;
+		unsigned int rc_bpg_offset_5 : 6;
+		unsigned int rc_min_qp_6 : 5;
+		unsigned int rc_max_qp_6 : 5;
+		unsigned int rc_bpg_offset_6 : 6;
+		unsigned int rc_min_qp_7 : 5;
+		unsigned int rc_max_qp_7 : 5;
+		unsigned int rc_bpg_offset_7 : 6;
+	};
+	unsigned int value[2];
+};
+
+union DSC_RC_RANGE_PARAMETERS_2_BXT {
+	struct {
+		unsigned int rc_min_qp_8 : 5;
+		unsigned int rc_max_qp_8 : 5;
+		unsigned int rc_bpg_offset_8 : 6;
+		unsigned int rc_min_qp_9 : 5;
+		unsigned int rc_max_qp_9 : 5;
+		unsigned int rc_bpg_offset_9 : 6;
+		unsigned int rc_min_qp_10 : 5;
+		unsigned int rc_max_qp_10 : 5;
+		unsigned int rc_bpg_offset_10 : 6;
+		unsigned int rc_min_qp_11 : 5;
+		unsigned int rc_max_qp_11 : 5;
+		unsigned int rc_bpg_offset_11 : 6;
+	};
+	unsigned int value[2];
+};
+
+union DSC_RC_RANGE_PARAMETERS_3_BXT {
+	struct {
+		unsigned int rc_min_qp_12 : 5;
+		unsigned int rc_max_qp_12 : 5;
+		unsigned int rc_bpg_offset_12 : 6;
+		unsigned int rc_min_qp_13 : 5;
+		unsigned int rc_max_qp_13 : 5;
+		unsigned int rc_bpg_offset_13 : 6;
+		unsigned int rc_min_qp_14 : 5;
+		unsigned int rc_max_qp_14 : 5;
+		unsigned int rc_bpg_offset_14 : 6;
+		unsigned int reserved_1 : 5;
+		unsigned int reserved_2 : 5;
+		unsigned int reserved_3 : 6;
+	};
+	unsigned int value[2];
+};
+
 #endif /* _I915_REG_H_ */
-- 
1.9.1

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Intel-gfx@lists.freedesktop.org
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[PATCH 08/10] drm: i915: Enable VDSC in Source

[Gaurav K Singh]

Below are the things being taken care as part of this patch:

1. Program Picture Parameter Set(PPS) MMIO regs and Rate Control
params regs in DSC Controller.
Depending on the no of VDSC engines, program the above regs.
2. Populate PPS Secondary Data Packet for Sink device
3. Data is send only to Sink device once DIP PPS is enabled in DIP
ctrl reg
4. DSC is only enabled only after Gen9 onwards
5. DSC capability should be supported from Sink side before programming
the source side.

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/i915/intel_vdsc.c | 425 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 424 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
index 536f417624cb..16f84044f47b 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -596,7 +596,8 @@ void populate_pps_sdp_for_sink(struct intel_encoder *encoder,
 	pps_params->bpp_high = (unsigned short)(vdsc_cfg->bits_per_pixel &
 									0xFF);
 
-	/* The PPS structure is stored as per our hardware registers which
+	/*
+	 * The PPS structure is stored as per our hardware registers which
 	 * are in little endian. When a value is assigned to a variable,
 	 * Intel systems stores data in little endian.
 	 * For e.g UINT16 a = 0x1234;
@@ -767,3 +768,425 @@ void populate_pps_sdp_for_sink(struct intel_encoder *encoder,
 	pps_params->rc_range_parameter14 =
 					SWAP_TWO_BYTES(rc_range_parameters[14]);
 }
+
+void intel_dsc_regs_init(struct intel_encoder *encoder,
+				struct intel_dsc_regs *dsc_regs, int dsc_type)
+{
+	switch (dsc_type) {
+	case DSC_A:
+		dsc_regs->dsc_picture_params0 = DSCA_PICTURE_PARAMETER_SET_0;
+		dsc_regs->dsc_picture_params1 = DSCA_PICTURE_PARAMETER_SET_1;
+		dsc_regs->dsc_picture_params2 = DSCA_PICTURE_PARAMETER_SET_2;
+		dsc_regs->dsc_picture_params3 = DSCA_PICTURE_PARAMETER_SET_3;
+		dsc_regs->dsc_picture_params4 = DSCA_PICTURE_PARAMETER_SET_4;
+		dsc_regs->dsc_picture_params5 = DSCA_PICTURE_PARAMETER_SET_5;
+		dsc_regs->dsc_picture_params6 = DSCA_PICTURE_PARAMETER_SET_6;
+		dsc_regs->dsc_picture_params7 = DSCA_PICTURE_PARAMETER_SET_7;
+		dsc_regs->dsc_picture_params8 = DSCA_PICTURE_PARAMETER_SET_8;
+		dsc_regs->dsc_picture_params9 = DSCA_PICTURE_PARAMETER_SET_9;
+		dsc_regs->dsc_picture_params10 = DSCA_PICTURE_PARAMETER_SET_10;
+		dsc_regs->dsc_picture_params16 = DSCA_PICTURE_PARAMETER_SET_16;
+		dsc_regs->dsc_rc_buff_thresh0_0 = DSCA_RC_BUF_THRESH_0_0;
+		dsc_regs->dsc_rc_buff_thresh0_1 = DSCA_RC_BUF_THRESH_0_1;
+		dsc_regs->dsc_rc_buff_thresh1_0 = DSCA_RC_BUF_THRESH_1_0;
+		dsc_regs->dsc_rc_buff_thresh1_1 = DSCA_RC_BUF_THRESH_1_1;
+		dsc_regs->dsc_rc_range0_0 = DSCA_RC_RANGE_PARAMETERS_0_0;
+		dsc_regs->dsc_rc_range0_1 = DSCA_RC_RANGE_PARAMETERS_0_1;
+		dsc_regs->dsc_rc_range1_0 = DSCA_RC_RANGE_PARAMETERS_1_0;
+		dsc_regs->dsc_rc_range1_1 = DSCA_RC_RANGE_PARAMETERS_1_1;
+		dsc_regs->dsc_rc_range2_0 = DSCA_RC_RANGE_PARAMETERS_2_0;
+		dsc_regs->dsc_rc_range2_1 = DSCA_RC_RANGE_PARAMETERS_2_1;
+		dsc_regs->dsc_rc_range3_0 = DSCA_RC_RANGE_PARAMETERS_3_0;
+		dsc_regs->dsc_rc_range3_1 = DSCA_RC_RANGE_PARAMETERS_3_1;
+		break;
+	case DSC_C:
+		dsc_regs->dsc_picture_params0 = DSCC_PICTURE_PARAMETER_SET_0;
+		dsc_regs->dsc_picture_params1 = DSCC_PICTURE_PARAMETER_SET_1;
+		dsc_regs->dsc_picture_params2 = DSCC_PICTURE_PARAMETER_SET_2;
+		dsc_regs->dsc_picture_params3 = DSCC_PICTURE_PARAMETER_SET_3;
+		dsc_regs->dsc_picture_params4 = DSCC_PICTURE_PARAMETER_SET_4;
+		dsc_regs->dsc_picture_params5 = DSCC_PICTURE_PARAMETER_SET_5;
+		dsc_regs->dsc_picture_params6 = DSCC_PICTURE_PARAMETER_SET_6;
+		dsc_regs->dsc_picture_params7 = DSCC_PICTURE_PARAMETER_SET_7;
+		dsc_regs->dsc_picture_params8 = DSCC_PICTURE_PARAMETER_SET_8;
+		dsc_regs->dsc_picture_params9 = DSCC_PICTURE_PARAMETER_SET_9;
+		dsc_regs->dsc_picture_params10 = DSCC_PICTURE_PARAMETER_SET_10;
+		dsc_regs->dsc_picture_params16 = DSCC_PICTURE_PARAMETER_SET_16;
+		dsc_regs->dsc_rc_buff_thresh0_0 = DSCC_RC_BUF_THRESH_0_0;
+		dsc_regs->dsc_rc_buff_thresh0_1 = DSCC_RC_BUF_THRESH_0_1;
+		dsc_regs->dsc_rc_buff_thresh1_0 = DSCC_RC_BUF_THRESH_1_0;
+		dsc_regs->dsc_rc_buff_thresh1_1 = DSCC_RC_BUF_THRESH_1_1;
+		dsc_regs->dsc_rc_range0_0 = DSCC_RC_RANGE_PARAMETERS_0_0;
+		dsc_regs->dsc_rc_range0_1 = DSCC_RC_RANGE_PARAMETERS_0_1;
+		dsc_regs->dsc_rc_range1_0 = DSCC_RC_RANGE_PARAMETERS_1_0;
+		dsc_regs->dsc_rc_range1_1 = DSCC_RC_RANGE_PARAMETERS_1_1;
+		dsc_regs->dsc_rc_range2_0 = DSCC_RC_RANGE_PARAMETERS_2_0;
+		dsc_regs->dsc_rc_range2_1 = DSCC_RC_RANGE_PARAMETERS_2_1;
+		dsc_regs->dsc_rc_range3_0 = DSCC_RC_RANGE_PARAMETERS_3_0;
+		dsc_regs->dsc_rc_range3_1 = DSCC_RC_RANGE_PARAMETERS_3_1;
+		break;
+	};
+}
+
+void configure_dsc_params_for_dsc_controller(struct intel_encoder *encoder,
+					struct intel_crtc_state *crtc_state,
+					struct intel_dsc_regs *dsc_regs,
+					int dsc_type)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dp *intel_dp = NULL;
+	struct vdsc_config *vdsc_cfg  = NULL;
+	unsigned long rc_range_parameters[NUM_BUF_RANGES];
+	unsigned long chicken_bit_value = 0;
+	unsigned int i = 0;
+	int port_type = encoder->type;
+
+	union DSC_PICTURE_PARAMETER_SET_0_BXT pps0;
+	union DSC_PICTURE_PARAMETER_SET_1_BXT pps1;
+	union DSC_PICTURE_PARAMETER_SET_2_BXT pps2;
+	union DSC_PICTURE_PARAMETER_SET_3_BXT pps3;
+	union DSC_PICTURE_PARAMETER_SET_4_BXT pps4;
+	union DSC_PICTURE_PARAMETER_SET_5_BXT pps5;
+	union DSC_PICTURE_PARAMETER_SET_6_BXT pps6;
+	union DSC_PICTURE_PARAMETER_SET_7_BXT pps7;
+	union DSC_PICTURE_PARAMETER_SET_8_BXT pps8;
+	union DSC_PICTURE_PARAMETER_SET_9_BXT pps9;
+	union DSC_PICTURE_PARAMETER_SET_10_BXT pps10;
+	union DSC_PICTURE_PARAMETER_SET_16_BXT pps16;
+	union DSC_RC_BUF_THRESH_0_BXT rc_buffer0;
+	union DSC_RC_BUF_THRESH_1_BXT rc_buffer1;
+	union DSC_RC_RANGE_PARAMETERS_0_BXT rc_range0;
+	union DSC_RC_RANGE_PARAMETERS_1_BXT rc_range1;
+	union DSC_RC_RANGE_PARAMETERS_2_BXT rc_range2;
+	union DSC_RC_RANGE_PARAMETERS_3_BXT rc_range3;
+
+	if (port_type == INTEL_OUTPUT_EDP) {
+
+		intel_dp = enc_to_intel_dp(&encoder->base);
+		vdsc_cfg = &(intel_dp->compr_params.dsc_cfg);
+
+		/* Configure VDSC engine */
+		/* PPS0 */
+		pps0.dsc_version_major = vdsc_cfg->dsc_version_major;
+		pps0.dsc_version_minor = vdsc_cfg->dsc_version_minor;
+		pps0.bits_per_component = vdsc_cfg->bits_per_component;
+		pps0.line_buf_depth = vdsc_cfg->line_buf_depth;
+		pps0.block_pred_enable = vdsc_cfg->block_pred_enable;
+		pps0.convert_rgb = vdsc_cfg->convert_rgb;
+		pps0.enable_422 = vdsc_cfg->enable422;
+		/* Since platform itself does not support VBR Enable */
+		pps0.vbr_enable = 0;
+		I915_WRITE(dsc_regs->dsc_picture_params0, pps0.value);
+
+		/* PPS1 */
+		pps1.bits_per_pixel = vdsc_cfg->bits_per_pixel;
+		I915_WRITE(dsc_regs->dsc_picture_params1, pps1.value);
+
+		/* PPS2 */
+		pps2.pic_height = vdsc_cfg->pic_height;
+		pps2.pic_width = vdsc_cfg->pic_width /
+						vdsc_cfg->num_vdsc_instances;
+		I915_WRITE(dsc_regs->dsc_picture_params2, pps2.value);
+
+		/* PPS3 */
+		pps3.slice_height = vdsc_cfg->slice_height;
+		pps3.slice_width = vdsc_cfg->slice_width;
+		I915_WRITE(dsc_regs->dsc_picture_params3, pps3.value);
+
+		/* PPS4 */
+		pps4.initial_xmit_delay = vdsc_cfg->initial_xmit_delay;
+		pps4.initial_dec_delay = vdsc_cfg->initial_dec_delay;
+		I915_WRITE(dsc_regs->dsc_picture_params4, pps4.value);
+
+		/* PPS5 */
+		pps5.scale_increment_interval =
+					vdsc_cfg->scale_increment_interval;
+		pps5.scale_decrement_interval =
+					vdsc_cfg->scale_decrement_interval;
+		I915_WRITE(dsc_regs->dsc_picture_params5, pps5.value);
+
+		/* PPS6 */
+		pps6.initial_scale_value = vdsc_cfg->initial_scale_value;
+		pps6.first_line_bpg_offset = vdsc_cfg->first_line_bpg_Ofs;
+		pps6.flatness_min_qp = vdsc_cfg->flatness_minQp;
+		pps6.flatness_max_qp = vdsc_cfg->flatness_maxQp;
+		I915_WRITE(dsc_regs->dsc_picture_params6, pps6.value);
+
+		/* PPS7 */
+		pps7.slice_bpg_offset = vdsc_cfg->slice_bpg_offset;
+		pps7.nfl_bpg_offset = vdsc_cfg->nfl_bpg_offset;
+		I915_WRITE(dsc_regs->dsc_picture_params7, pps7.value);
+
+		/* PPS8 */
+		pps8.initial_offset = vdsc_cfg->initial_offset;
+		pps8.final_offset = vdsc_cfg->final_offset;
+		I915_WRITE(dsc_regs->dsc_picture_params8, pps8.value);
+
+		/* PPS9 */
+		pps9.rc_edge_factor = vdsc_cfg->rc_edge_factor;
+		pps9.rc_model_size = vdsc_cfg->rc_model_size;
+		I915_WRITE(dsc_regs->dsc_picture_params9, pps9.value);
+
+		/* PPS10 */
+		pps10.rc_quant_incr_limit0 = vdsc_cfg->rc_quant_incr_limit0;
+		pps10.rc_quant_incr_limit1 = vdsc_cfg->rc_quant_incr_limit1;
+		pps10.rc_tgt_offset_hi = vdsc_cfg->rc_tgt_offset_high;
+		pps10.rc_tgt_offset_lo = vdsc_cfg->rc_tgt_offset_low;
+		I915_WRITE(dsc_regs->dsc_picture_params10, pps10.value);
+
+		/* RC_Buffer 0 */
+		rc_buffer0.rc_buf_thresh_0 = vdsc_cfg->rc_buf_thresh[0];
+		rc_buffer0.rc_buf_thresh_1 = vdsc_cfg->rc_buf_thresh[1];
+		rc_buffer0.rc_buf_thresh_2 = vdsc_cfg->rc_buf_thresh[2];
+		rc_buffer0.rc_buf_thresh_3 = vdsc_cfg->rc_buf_thresh[3];
+		rc_buffer0.rc_buf_thresh_4 = vdsc_cfg->rc_buf_thresh[4];
+		rc_buffer0.rc_buf_thresh_5 = vdsc_cfg->rc_buf_thresh[5];
+		rc_buffer0.rc_buf_thresh_6 = vdsc_cfg->rc_buf_thresh[6];
+		rc_buffer0.rc_buf_thresh_7 = vdsc_cfg->rc_buf_thresh[7];
+		I915_WRITE(dsc_regs->dsc_rc_buff_thresh0_0,
+							rc_buffer0.value[0]);
+		I915_WRITE(dsc_regs->dsc_rc_buff_thresh0_1,
+							rc_buffer0.value[1]);
+
+		/* RC_Buffer 0 */
+		rc_buffer1.rc_buf_thresh_8 = vdsc_cfg->rc_buf_thresh[8];
+		rc_buffer1.rc_buf_thresh_9 = vdsc_cfg->rc_buf_thresh[9];
+		rc_buffer1.rc_buf_thresh_10 = vdsc_cfg->rc_buf_thresh[10];
+		rc_buffer1.rc_buf_thresh_11 = vdsc_cfg->rc_buf_thresh[11];
+		rc_buffer1.rc_buf_thresh_12 = vdsc_cfg->rc_buf_thresh[12];
+		rc_buffer1.rc_buf_thresh_13 = vdsc_cfg->rc_buf_thresh[13];
+		I915_WRITE(dsc_regs->dsc_rc_buff_thresh1_0,
+							rc_buffer1.value[0]);
+		I915_WRITE(dsc_regs->dsc_rc_buff_thresh1_1,
+							rc_buffer1.value[1]);
+
+		for (i = 0; i < NUM_BUF_RANGES; i++) {
+			rc_range_parameters[i] = (unsigned short)(
+			(vdsc_cfg->rc_range_params[i].range_bpg_offset << 10) |
+			(vdsc_cfg->rc_range_params[i].range_max_qp << 5) |
+			(vdsc_cfg->rc_range_params[i].range_min_qp));
+		}
+
+		/* RC Range1 */
+		rc_range0.value[0] = ((rc_range_parameters[1] << 16) |
+						(rc_range_parameters[0]));
+		rc_range0.value[1] = ((rc_range_parameters[3] << 16) |
+						(rc_range_parameters[2]));
+		I915_WRITE(dsc_regs->dsc_rc_range0_0, rc_range0.value[0]);
+		I915_WRITE(dsc_regs->dsc_rc_range0_1, rc_range0.value[1]);
+
+		/* RC Range2 */
+		rc_range1.value[0] = ((rc_range_parameters[5] << 16) |
+						(rc_range_parameters[4]));
+		rc_range1.value[1] = ((rc_range_parameters[7] << 16) |
+						(rc_range_parameters[6]));
+		I915_WRITE(dsc_regs->dsc_rc_range1_0, rc_range1.value[0]);
+		I915_WRITE(dsc_regs->dsc_rc_range1_1, rc_range1.value[1]);
+
+		/* RC Range3 */
+		rc_range2.value[0] = ((rc_range_parameters[9] << 16) |
+						(rc_range_parameters[8]));
+		rc_range2.value[1] = ((rc_range_parameters[11] << 16) |
+						(rc_range_parameters[10]));
+		I915_WRITE(dsc_regs->dsc_rc_range2_0, rc_range2.value[0]);
+		I915_WRITE(dsc_regs->dsc_rc_range2_1, rc_range2.value[1]);
+
+		/* RC Range4 */
+		rc_range3.value[0] = ((rc_range_parameters[13] << 16) |
+						(rc_range_parameters[12]));
+		rc_range3.value[1] = rc_range_parameters[14];
+		I915_WRITE(dsc_regs->dsc_rc_range3_0, rc_range3.value[0]);
+		I915_WRITE(dsc_regs->dsc_rc_range3_1, rc_range3.value[1]);
+
+		/* PPS16 */
+		pps16.slice_chunk_size = vdsc_cfg->chunk_size;
+		pps16.slice_per_line =
+			(vdsc_cfg->pic_width / vdsc_cfg->num_vdsc_instances) /
+							vdsc_cfg->slice_width;
+		pps16.slice_row_per_frame =
+				vdsc_cfg->pic_height / vdsc_cfg->slice_height;
+		I915_WRITE(dsc_regs->dsc_picture_params16, pps16.value);
+
+		chicken_bit_value = I915_READ(DSC_CHICKEN_1_A);
+		I915_WRITE(DSC_CHICKEN_1_A, 0x80000000);
+	}
+}
+
+void enable_pps_dip(struct intel_encoder *encoder,
+					struct intel_dsc_regs *dsc_regs)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	int type = encoder->port;
+	i915_reg_t dip_ctrl_reg;
+	unsigned int value = 0;
+
+	if (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP) {
+		dip_ctrl_reg = dsc_regs->dip_ctrl_reg;
+		value = I915_READ(dip_ctrl_reg);
+		value |= VDIP_ENABLE_PPS;
+		I915_WRITE(dip_ctrl_reg, value);
+	}
+}
+
+void write_dip(struct intel_encoder *encoder, unsigned char *dip_data,
+						unsigned char dip_size,
+						struct intel_dsc_regs *dsc_regs)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	unsigned int max_offset;
+	unsigned char count = 0;
+	unsigned char i = 0;
+	unsigned char data_to_write = 0;
+	unsigned char offset = 0;
+	unsigned long remaining_buffer = 0;
+	unsigned int video_dip_pps_data = 0;
+	unsigned int payload_data_reg;
+
+	/*
+	 * 33*4 = 132
+	 * 4 byte SDP header + 128 byte PPS data
+	 */
+	max_offset = 33;
+	payload_data_reg = dsc_regs->dip_pps_data_ctrl_reg;
+
+	if (dip_data) {
+		remaining_buffer = max_offset * 4;
+		data_to_write = dip_size;
+
+		while (remaining_buffer > 0 && offset < max_offset) {
+			if (data_to_write >= 4) {
+				video_dip_pps_data = (dip_data[count] |
+						(dip_data[count + 1] << 8) |
+						(dip_data[count + 2] << 16) |
+						(dip_data[count + 3] << 24));
+				data_to_write -= 4;
+				count += 4;
+				I915_WRITE(_MMIO(payload_data_reg),
+							video_dip_pps_data);
+			} else {
+				unsigned char buffer[4];
+
+				memset(&buffer[0], 0,
+						4 * sizeof(unsigned char));
+				for (i = 0; i < data_to_write; i++)
+					buffer[i] = dip_data[count++];
+				video_dip_pps_data = (buffer[0] |
+					(buffer[1] << 8) |
+					(buffer[2] << 16) | (buffer[3] << 24));
+				data_to_write = 0;
+				I915_WRITE(_MMIO(payload_data_reg),
+							video_dip_pps_data);
+			}
+			payload_data_reg += 0x4;
+			remaining_buffer -= 4;
+			offset++;
+		}
+	}
+}
+
+void send_pps_sdp_to_sink(struct intel_encoder *encoder, int pipe,
+			struct picture_parameters_set *pps_params,
+			struct intel_dsc_regs *dsc_regs)
+{
+	union pps_sdp sdp;
+	unsigned char payload_size = 0;
+
+	sdp.secondary_data_packet_header.sdp_id = 0;
+	sdp.secondary_data_packet_header.sdp_type = 0x10;
+	sdp.secondary_data_packet_header.sdp_byte1 = 0x7F;
+	sdp.secondary_data_packet_header.sdp_byte2 = 0x0;
+	sdp.pps_payload = *pps_params;
+
+	payload_size = SDP_HEADER_SIZE + PPS_PAYLOAD_SIZE;
+	write_dip(encoder, (unsigned char *)&sdp, payload_size, dsc_regs);
+}
+
+void intel_dsc_enable(struct intel_encoder *encoder,
+				struct intel_crtc_state *pipe_config)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct picture_parameters_set pps_params;
+	struct intel_dsc_regs dsc_regs;
+	struct drm_crtc *crtc = pipe_config->base.crtc;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int pipe = intel_crtc->pipe;
+	int dsc_type1;
+	int dsc_type2;
+	int type = encoder->type;
+	unsigned int dss_ctrl1_value = 0;
+	unsigned int dss_ctrl2_value = 0;
+
+	if ((INTEL_GEN(dev_priv) < 9) ||
+				!intel_dp->compr_params.compression_support)
+		return;
+	/* TO DO: configure DSC params and program source regs */
+
+	if (type == INTEL_OUTPUT_EDP) {
+		dsc_regs.dss_ctrl1_reg = DSS_CONTROL1;
+		dsc_regs.dss_ctrl2_reg = DSS_CONTROL2;
+		dsc_regs.dip_ctrl_reg = VIDEO_DIP_CTL_EDP;
+		dsc_regs.dip_pps_data_ctrl_reg = VIDEO_DIP_PPS_DATA_EDP_REG;
+		dsc_type1 = DSC_A;
+		dsc_type2 = DSC_C;
+	} else if (type == INTEL_OUTPUT_DP) {
+		switch (pipe) {
+		case PIPE_A:
+			dsc_regs.dss_ctrl1_reg = PIPE_DSS_CTL1_PB;
+			dsc_regs.dss_ctrl2_reg = PIPE_DSS_CTL2_PB;
+			dsc_regs.dip_ctrl_reg = VIDEO_DIP_CTL_A;
+			dsc_regs.dip_pps_data_ctrl_reg =
+						VIDEO_DIP_DRM_DATA_TRANSA_REG;
+			dsc_type1 = PIPEA_DSC_0;
+			dsc_type2 = PIPEA_DSC_1;
+			break;
+		case PIPE_B:
+			dsc_regs.dss_ctrl1_reg = PIPE_DSS_CTL1_PC;
+			dsc_regs.dss_ctrl2_reg = PIPE_DSS_CTL2_PC;
+			dsc_regs.dip_ctrl_reg = VIDEO_DIP_CTL_B;
+			dsc_regs.dip_pps_data_ctrl_reg =
+						VIDEO_DIP_DRM_DATA_TRANSB_REG;
+			dsc_type1 = PIPEB_DSC_0;
+			dsc_type2 = PIPEB_DSC_1;
+			break;
+		default:
+			return;
+		}
+	} else {
+		DRM_ERROR("Func:%s Unsupported port:%d\n", __func__, type);
+	}
+
+	intel_dsc_regs_init(encoder, &dsc_regs, dsc_type1);
+	configure_dsc_params_for_dsc_controller(encoder, pipe_config,
+							&dsc_regs, dsc_type1);
+	if (intel_dp->compr_params.dsc_cfg.num_vdsc_instances != 1) {
+		intel_dsc_regs_init(encoder, &dsc_regs, dsc_type2);
+		configure_dsc_params_for_dsc_controller(encoder, pipe_config,
+							&dsc_regs, dsc_type2);
+	}
+	populate_pps_sdp_for_sink(encoder, pipe_config, &pps_params);
+
+	send_pps_sdp_to_sink(encoder, pipe, &pps_params, &dsc_regs);
+
+	enable_pps_dip(encoder, &dsc_regs);
+
+	dss_ctrl1_value = I915_READ(dsc_regs.dss_ctrl1_reg);
+	dss_ctrl2_value = I915_READ(dsc_regs.dss_ctrl2_reg);
+	if (type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP) {
+		 /*
+		  * Enable joiner only if we are using both the VDSC engines
+		  * To check if splitters gets enabled by default in HW
+		  * if joiner is enabled
+		  */
+		if (intel_dp->compr_params.dsc_cfg.num_vdsc_instances != 1)
+			dss_ctrl1_value |= JOINER_ENABLE | SPLITTER_ENABLE;
+
+		I915_WRITE(dsc_regs.dss_ctrl1_reg, dss_ctrl1_value);
+
+		dss_ctrl2_value |= LEFT_BRANCH_VDSC_ENABLE;
+		if (intel_dp->compr_params.dsc_cfg.num_vdsc_instances != 1)
+			dss_ctrl2_value |= RIGHT_BRANCH_VDSC_ENABLE;
+
+		I915_WRITE(dsc_regs.dss_ctrl2_reg, dss_ctrl2_value);
+	}
+}
-- 
1.9.1

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[PATCH 09/10] drm: i915: Disable VDSC from Source

[Gaurav K Singh]

1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   |  3 +++
 drivers/gpu/drm/i915/intel_vdsc.c | 51 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 54 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7d0574cf6e94..bd2c0832a4dc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9676,11 +9676,14 @@ enum skl_power_gate {
 
 #define DSS_CONTROL1				_MMIO(0x67400)
 #define JOINER_ENABLE				(1 << 30)
+#define JOINER_DISABLE				(0 << 30)
 #define SPLITTER_ENABLE				(1 << 31)
 
 #define DSS_CONTROL2				_MMIO(0x67404)
 #define LEFT_BRANCH_VDSC_ENABLE			(1 << 31)
+#define LEFT_BRANCH_VDSC_DISABLE		(0 << 31)
 #define RIGHT_BRANCH_VDSC_ENABLE		(1 << 15)
+#define RIGHT_BRANCH_VDSC_DISABLE		(0 << 15)
 
 #define PIPE_DSS_CTL1_PB			_MMIO(0x78200)
 #define PIPE_DSS_CTL2_PB			_MMIO(0x78204)
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c
index 16f84044f47b..86b2d17df3a8 100644
--- a/drivers/gpu/drm/i915/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/intel_vdsc.c
@@ -1190,3 +1190,54 @@ void intel_dsc_enable(struct intel_encoder *encoder,
 		I915_WRITE(dsc_regs.dss_ctrl2_reg, dss_ctrl2_value);
 	}
 }
+
+void intel_dsc_disable(struct intel_encoder *encoder,
+				struct intel_crtc_state *pipe_config)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_dsc_regs dsc_regs;
+	struct drm_crtc *crtc = pipe_config->base.crtc;
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	int pipe = intel_crtc->pipe;
+	int type = encoder->type;
+	unsigned int dss_ctrl1_value = 0;
+	unsigned int dss_ctrl2_value = 0;
+
+	if ((INTEL_GEN(dev_priv) < 9) ||
+				!intel_dp->compr_params.compression_support)
+		return;
+
+	if (type == INTEL_OUTPUT_EDP) {
+		dsc_regs.dss_ctrl1_reg = DSS_CONTROL1;
+		dsc_regs.dss_ctrl2_reg = DSS_CONTROL2;
+	} else if (type == INTEL_OUTPUT_DP) {
+		switch (pipe) {
+		case PIPE_A:
+			dsc_regs.dss_ctrl1_reg = PIPE_DSS_CTL1_PB;
+			dsc_regs.dss_ctrl2_reg = PIPE_DSS_CTL2_PB;
+			break;
+		case PIPE_B:
+			dsc_regs.dss_ctrl1_reg = PIPE_DSS_CTL1_PC;
+			dsc_regs.dss_ctrl2_reg = PIPE_DSS_CTL2_PC;
+			break;
+		default:
+			return;
+		}
+	} else {
+		DRM_ERROR("Func:%s Unsupported port:%d\n", __func__, type);
+	}
+
+	dss_ctrl1_value = I915_READ(dsc_regs.dss_ctrl1_reg);
+	dss_ctrl2_value = I915_READ(dsc_regs.dss_ctrl2_reg);
+
+	if ((dss_ctrl2_value & LEFT_BRANCH_VDSC_ENABLE) ||
+		(dss_ctrl2_value & RIGHT_BRANCH_VDSC_ENABLE))
+		dss_ctrl2_value &= LEFT_BRANCH_VDSC_DISABLE &
+						RIGHT_BRANCH_VDSC_DISABLE;
+	I915_WRITE(dsc_regs.dss_ctrl2_reg, dss_ctrl2_value);
+
+	if (dss_ctrl1_value & JOINER_ENABLE)
+		dss_ctrl1_value &= JOINER_DISABLE;
+	I915_WRITE(dsc_regs.dss_ctrl1_reg, dss_ctrl1_value);
+}
-- 
1.9.1

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[PATCH 10/10] drm/i915: Encoder enable/disable seq wrt DSC

[Gaurav K Singh]

1. Send PPS and enable DSC after decompression is enabled in DP sink
2. Enable DSC in Source before enabling pipe
3. Disabling compression after disabling pipe, but before disabling port

Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      |  5 +++++
 drivers/gpu/drm/i915/intel_display.c | 20 ++++++++++++++++++++
 2 files changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4073c98a267f..0e0034f7ad67 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -4318,6 +4318,11 @@ extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
 				  bool enable);
 extern void intel_dp_compute_dsc_parameters(struct intel_dp *dp);
 
+extern void intel_dsc_enable(struct intel_encoder *encoder,
+					struct intel_crtc_state *crtc_state);
+extern void intel_dsc_disable(struct intel_encoder *encoder,
+					struct intel_crtc_state *crtc_state);
+
 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
 			struct drm_file *file);
 
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3c479e3fd553..812dcf8a15c4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5226,6 +5226,11 @@ static void intel_encoders_pre_enable(struct drm_crtc *crtc,
 
 		if (encoder->pre_enable)
 			encoder->pre_enable(encoder, crtc_state, conn_state);
+		/*
+		 * Send PPS and Enable DSC after decompression is
+		 * enabled in DP sink
+		 */
+		intel_dsc_enable(encoder, crtc_state);
 	}
 }
 
@@ -5623,7 +5628,10 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
 	struct drm_crtc *crtc = old_crtc_state->base.crtc;
 	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	struct drm_connector_state *conn_state;
+	struct drm_connector *conn;
 	enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
+	int i;
 
 	intel_encoders_disable(crtc, old_crtc_state, old_state);
 
@@ -5640,6 +5648,18 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
 	if (!transcoder_is_dsi(cpu_transcoder))
 		intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
 
+	/* Invoke intel_dsc_disable */
+	for_each_new_connector_in_state(old_state, conn, conn_state, i) {
+		struct intel_encoder *encoder =
+			to_intel_encoder(conn_state->best_encoder);
+
+		if (conn_state->crtc != crtc)
+			continue;
+
+		/* Disable DSC if supported by platform and panel */
+		intel_dsc_disable(encoder, old_crtc_state);
+	}
+
 	if (INTEL_GEN(dev_priv) >= 9)
 		skylake_scaler_disable(intel_crtc);
 	else
-- 
1.9.1

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✗ Fi.CI.BAT: failure for Enabling VDSC in i915 driver for GLK

[Patchwork]

== Series Details ==

Series: Enabling VDSC in i915 driver for GLK
URL   : https://patchwork.freedesktop.org/series/38874/
State : failure

== Summary ==

  CHK     include/config/kernel.release
  CHK     include/generated/uapi/linux/version.h
  CHK     include/generated/utsrelease.h
  CHK     include/generated/bounds.h
  CHK     include/generated/timeconst.h
  CHK     include/generated/asm-offsets.h
  CALL    scripts/checksyscalls.sh
  DESCEND  objtool
  CHK     scripts/mod/devicetable-offsets.h
  CHK     include/generated/compile.h
  CHK     kernel/config_data.h
  CC [M]  drivers/gpu/drm/i915/intel_vdsc.o
drivers/gpu/drm/i915/intel_vdsc.c: In function ‘intel_dsc_enable’:
drivers/gpu/drm/i915/intel_vdsc.c:1164:3: error: ‘dsc_type2’ may be used uninitialized in this function [-Werror=maybe-uninitialized]
   configure_dsc_params_for_dsc_controller(encoder, pipe_config,
   ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
        &dsc_regs, dsc_type2);
        ~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_vdsc.c:1160:2: error: ‘dsc_type1’ may be used uninitialized in this function [-Werror=maybe-uninitialized]
  configure_dsc_params_for_dsc_controller(encoder, pipe_config,
  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
        &dsc_regs, dsc_type1);
        ~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
scripts/Makefile.build:316: recipe for target 'drivers/gpu/drm/i915/intel_vdsc.o' failed
make[4]: *** [drivers/gpu/drm/i915/intel_vdsc.o] Error 1
scripts/Makefile.build:575: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:575: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:575: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1048: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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Re: [PATCH 00/10] Enabling VDSC in i915 driver for GLK

[Manasi Navare]

Thanks for the patches. I am working on the DSC support on i915 for eDP/DP
as well. Looking at the patches below, this is specific to VDSC enabling for eDP
panels and not for the external DP.
So please mention that specifically in the cover letter as well.

On Fri, Feb 23, 2018 at 09:25:43PM +0530, Gaurav K Singh wrote:
> Display  manufacturers are turning to higher-resolution displays
> to differentiate their products. The increased pixel counts have
> required increased bandwidth over the links that drive these displays.
> However, advances in physical layer technology have not kept up 
> with the increases in pixel counts.
> 
> These factors have created a need for compression on display links.
> The Video Electronics Standards Association(VESA),in liaison with the
> MIPI Alliance, has developed an industry standard Display Stream Compression(DSC)
> for interoperable, visually lossless compression over display links.
> 
> These patches enable VDSC in i915 gfx driver for Gen9,Gen10 platforms

Please specify that this enables VDSC for eDp in i915 gfx driver.

> and provide basic code for future platforms.
> 
> Testing:
> Did testing on GLK RVP. By default GLK RVP has non-DSC EDP panel, there was no regression with these patches.
> 
> BA Chrome Team (OTC) do not have EDP panel which supports DSC.
> Trying to arrrage DSC EDP panel from other teams in BA, hopeful to get it in few weeks.
>

I do have a DSC eDP panel here in Oregon and can volunteer for testing your patches with that on GLK RVP.

Manasi
 
> Dropping the patches to get the review started.
> 
> Gaurav K Singh (10):
>   drm: i915: Defining Compression Capabilities
>   drm: i915: Get DSC capability from DP sink
>   drm: i915: Enable/Disable DSC in DP sink
>   drm: i915: Compute RC & DSC parameters
>   drm: i915: Define Picture Parameter Set
>   drm/i915: Populate PPS Secondary Data Pkt for Sink
>   drm: i915: Define VDSC regs and DSC params
>   drm: i915: Enable VDSC in Source
>   drm: i915: Disable VDSC from Source
>   drm/i915: Encoder enable/disable seq wrt DSC
> 
>  drivers/gpu/drm/i915/Makefile        |    1 +
>  drivers/gpu/drm/i915/i915_drv.h      |  589 ++++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h      |  451 ++++++++++++
>  drivers/gpu/drm/i915/intel_ddi.c     |    4 +
>  drivers/gpu/drm/i915/intel_display.c |   20 +
>  drivers/gpu/drm/i915/intel_dp.c      |  182 +++++
>  drivers/gpu/drm/i915/intel_drv.h     |   64 ++
>  drivers/gpu/drm/i915/intel_vdsc.c    | 1243 ++++++++++++++++++++++++++++++++++
>  include/drm/drm_dp_helper.h          |    3 +
>  9 files changed, 2557 insertions(+)
>  create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c
> 
> -- 
> 1.9.1
> 
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH 01/10] drm: i915: Defining Compression Capabilities

[Manasi Navare]

On Fri, Feb 23, 2018 at 09:25:44PM +0530, Gaurav K Singh wrote:
> For Vesa Display Stream compression, defining structures for
> compression capabilities to be stored in encoder.
> 
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h  | 125 +++++++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_drv.h |  62 +++++++++++++++++++
>  include/drm/drm_dp_helper.h      |   1 +
>  3 files changed, 188 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 0d8cb74e7d02..4b1c323c0925 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -780,6 +780,131 @@ struct i915_psr {
>  	void (*setup_vsc)(struct intel_dp *, const struct intel_crtc_state *);
>  };
>  
> +/* DSC Configuration structure */
> +#define NUM_BUF_RANGES		15
> +
> +/* Configuration for a single Rate Control model range */
> +struct rc_range_parameters {
> +	/* Min Quantization Parameters allowed for this range */
> +	unsigned long range_min_qp;

Its only a 5 bit value, so uint_8 should be good, why have a unsigned long.
Same for max_qp which is 5 bits and bpg_offset which is 6 bits.
Please consider these for the parameters below.

> +	/* Max Quantization Parameters allowed for this range */
> +	unsigned long range_max_qp;
> +	/* Bits/group offset to apply to target for this group */
> +	unsigned long range_bpg_offset;
> +};
> +
> +struct vdsc_config {
> +	/* Bits / component for previous reconstructed line buffer */
> +	unsigned long line_buf_depth;
> +	/*
> +	 * Rate control buffer size (in bits); not in PPS,
> +	 * used only in C model for checking overflow
> +	 */
> +	unsigned long rc_bits;
> +	/* Bits per component to code (must be 8, 10, or 12) */
> +	unsigned long bits_per_component;
> +	/*
> +	 * Flag indicating to do RGB - YCoCg conversion
> +	 * and back (should be 1 for RGB input)
> +	 */
> +	bool convert_rgb;
> +	unsigned long slice_count;

For eDP, it can be max 4, why unsigned long?

> +	/* Slice Width */
> +	unsigned long slice_width;
> +	/* Slice Height */
> +	unsigned long slice_height;
> +	/*
> +	 * 4:2:2 enable mode (from PPS, 4:2:2 conversion happens
> +	 * outside of DSC encode/decode algorithm)
> +	 */
> +	bool enable422;
> +	/* Picture Width */
> +	unsigned long pic_width;
> +	/* Picture Height */
> +	unsigned long pic_height;
> +	/* Offset to bits/group used by RC to determine QP adjustment */
> +	unsigned long rc_tgt_offset_high;
> +	/* Offset to bits/group used by RC to determine QP adjustment */
> +	unsigned long rc_tgt_offset_low;
> +	/* Bits/pixel target << 4 (ie., 4 fractional bits) */
> +	unsigned long bits_per_pixel;
> +	/*
> +	 * Factor to determine if an edge is present based
> +	 * on the bits produced
> +	 */
> +	unsigned long rc_edge_factor;
> +	/* Slow down incrementing once the range reaches this value */
> +	unsigned long rc_quant_incr_limit1;
> +	/* Slow down incrementing once the range reaches this value */
> +	unsigned long rc_quant_incr_limit0;
> +	/* Number of pixels to delay the initial transmission */
> +	unsigned long initial_xmit_delay;
> +	/* Number of pixels to delay the VLD on the decoder,not including SSM */
> +	unsigned long  initial_dec_delay;
> +	/* Block prediction range (in pixels) */
> +	bool block_pred_enable;
> +	/* Bits/group offset to use for first line of the slice */
> +	unsigned long first_line_bpg_Ofs;
> +	/* Value to use for RC model offset at slice start */
> +	unsigned long initial_offset;
> +	/* X position in the picture of top-left corner of slice */
> +	unsigned long x_start;
> +	/* Y position in the picture of top-left corner of slice */
> +	unsigned long y_start;
> +	/* Thresholds defining each of the buffer ranges */
> +	unsigned long rc_buf_thresh[NUM_BUF_RANGES - 1];
> +	/* Parameters for each of the RC ranges */
> +	struct rc_range_parameters rc_range_params[NUM_BUF_RANGES];
> +	/* Total size of RC model */
> +	unsigned long rc_model_size;
> +	/* Minimum QP where flatness information is sent */
> +	unsigned long flatness_minQp;
> +	/* Maximum QP where flatness information is sent */
> +	unsigned long flatness_maxQp;
> +	/*
> +	 * MAX-MIN for all components is required to
> +	 * be <= this value for flatness to be used
> +	 */
> +	unsigned long flatness_det_thresh;
> +	/* Initial value for scale factor */
> +	unsigned long initial_scale_value;
> +	/* Decrement scale factor every scale_decrement_interval groups */
> +	unsigned long scale_decrement_interval;
> +	/* Increment scale factor every scale_increment_interval groups */
> +	unsigned long scale_increment_interval;
> +	/* Non-first line BPG offset to use */
> +	unsigned long nfl_bpg_offset;
> +	/* BPG offset used to enforce slice bit */
> +	unsigned long slice_bpg_offset;
> +	/* Final RC linear transformation offset value */
> +	unsigned long final_offset;
> +	/* Enable on-off VBR (ie., disable stuffing bits) */
> +	bool vbr_enable;
> +	/* Mux word size (in bits) for SSM mode */
> +	unsigned long mux_word_size;
> +	/*
> +	 * The (max) size in bytes of the "chunks" that are
> +	 * used in slice multiplexing
> +	 */
> +	unsigned long chunk_size;
> +	/* Placeholder for PPS identifier */
> +	unsigned long pps_identifier;
> +	/* DSC Minor Version */
> +	unsigned long dsc_version_minor;
> +	/* DSC Major version */
> +	unsigned long dsc_version_major;
> +	/* Number of VDSC engines */
> +	unsigned long num_vdsc_instances;
> +};
> +
> +/* Compression caps stored in encoder */
> +struct i915_compression_params {
> +	bool compression_support;
> +	unsigned long compression_bpp;

Does this indicate the 16 bit value with 4 fractional bits? May be add a comment for that.

> +	struct vdsc_config dsc_cfg;
> +	unsigned char slice_count;
> +};

There is probably no need to have these convoluted structs, the compressed bpp and slice count
are obtained directly from DPCDs which can be populated where needed with the helpers instead
of populating them into dp_dsc_sink_cap and then populating i915_compression_params.slice_count/
compressed_bpp.

Again I have helpers for those already currently on the internal M-L.
intel_dp can then only have compression_support and dsc_cfg.

> +
>  enum intel_pch {
>  	PCH_NONE = 0,	/* No PCH present */
>  	PCH_IBX,	/* Ibexpeak PCH */
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 5853d92a6512..6e1b907990bf 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -954,6 +954,63 @@ struct intel_dp_compliance {
>  	u8 test_lane_count;
>  };
>  
> +/* Vesa Display Stream Capability of DP Sink */
> +struct dp_sink_dsc_caps {
> +	/* Display Stream Compression Support */
> +	bool is_dsc_supported;
> +	u8 dsc_major_ver;
> +	u8 dsc_minor_ver;
> +	u16 rcbuffer_blocksize;
> +	/* n+1 value */
> +	u16 rcbuffer_size_in_blocks;
> +	unsigned long rcbuffer_size;
> +
> +	union {
> +		u8 slice_caps;
> +		struct {
> +			u8 one_slice_per_line_support : 1;
> +			u8 two_slice_per_line_support : 1;
> +			u8 slice_caps_reserved1 : 1;
> +			u8 four_slice_per_line_support : 1;
> +			u8 slice_caps_reserved2 : 4;
> +		};
> +	};
> +	/* Decode line buffer bits of precision */
> +	unsigned long line_buffer_bit_depth;
> +	bool is_block_pred_supported;
> +	unsigned long sink_support_max_bpp;
> +
> +	union {
> +		u8 color_format_caps;
> +		struct {
> +			u8 RGB_support : 1;
> +			u8 YCbCr444_support : 1;
> +			u8 YCbCr422_support : 1;
> +			u8 color_format_caps_reserved : 5;
> +		};
> +	};
> +
> +	union {
> +		u8 color_depth_caps;
> +		struct {
> +			u8 color_depth_caps_reserved1 : 1;
> +			u8 support_8bpc : 1;
> +			u8 support_10bpc : 1;
> +			u8 support_12bpc : 1;
> +			u8 color_depth_caps_reserved2 : 4;
> +		};
> +	};
> +
> +	u16 slice_height;
> +	u16 slice_width;
> +	/* Y Resolution */
> +	u16 pic_height;
> +	/* X Resolution */
> +	u16 pic_width;
> +};

Since we will cache the entire DPCD register set for DSC, we really dont need to have structure
for saving those values, they can be computed whenever needed using helpers/macros that read the cached
DPCD values. That is the convention followed for values obtained from DP DPCD in rest of the driver.
I have the patches for helpers that give these values but currently on internal M-L.

Manasi

> +
> +
> +
>  struct intel_dp {
>  	i915_reg_t output_reg;
>  	i915_reg_t aux_ch_ctl_reg;
> @@ -971,6 +1028,8 @@ struct intel_dp {
>  	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
>  	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
>  	uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
> +	uint8_t dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
> +	uint8_t fec_dpcd;

>  	/* source rates */
>  	int num_source_rates;
>  	const int *source_rates;
> @@ -1046,6 +1105,9 @@ struct intel_dp {
>  
>  	/* Displayport compliance testing */
>  	struct intel_dp_compliance compliance;
> +
> +	/* For Vesa Display Stream Compression Support */
> +	struct i915_compression_params compr_params;
>  };
>  
>  struct intel_lspcon {
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index da58a428c8d7..05f811c50d28 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -896,6 +896,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
>  #define DP_RECEIVER_CAP_SIZE		0xf
>  #define EDP_PSR_RECEIVER_CAP_SIZE	2
>  #define EDP_DISPLAY_CTL_CAP_SIZE	3
> +#define DP_DSC_RECEIVER_CAP_SIZE	0xb
>  
>  void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
>  void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
> -- 
> 1.9.1
> 
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Re: [PATCH 02/10] drm: i915: Get DSC capability from DP sink

[Manasi Navare]

On Fri, Feb 23, 2018 at 09:25:45PM +0530, Gaurav K Singh wrote:
> Get decompression capabilities from DP sink by doing
> DPCD reads of different offsets as per eDP/DP specs.
> 
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 167 ++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 167 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 1868f73f730c..f494a851ff89 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -5883,6 +5883,149 @@ void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
>  	return downclock_mode;
>  }
>  
> +static void intel_dp_sink_get_dsc_capability(struct intel_dp *intel_dp,
> +					struct dp_sink_dsc_caps *dp_dsc_caps)
> +{
> +	u8 rcbuffer_blocksize;
> +	u8 fec_dpcd;
> +	unsigned long line_buffer_bit_depth, sink_support_max_bpp_msb;
> +

Clear the previously cached dsc_dpcd before caching them again since it might still
have those from previous edp > 1.4 but we might not need them if current edp < 1.4

> +	/* VDSC is supported only for eDp v1.4 or higher, DPCD 0x00700 offset */
> +	if (intel_dp->edp_dpcd[0] < 0x03)

Use the #define DP_EDP_14 for the eDP version check of 1.4

> +		return;
> +
> +	/* Read DPCD 0x060 to 0x06a */
> +	if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT, intel_dp->dsc_dpcd,
> +			     sizeof(intel_dp->dsc_dpcd)) < 0)
> +		return;
> +
> +	dp_dsc_caps->is_dsc_supported = intel_dp->dsc_dpcd[0] &
> +					DP_DSC_DECOMPRESSION_IS_SUPPORTED;

Like I mentioned on patch 1/10 from the reviews I had got on my DSC patches,
no need to have is_dsc_supported field or dp_dsc_caps since the entire set of
DPCD registers is cached, this can be computed on the fly when needed.

> +
> +	if (!dp_dsc_caps->is_dsc_supported)
> +		return;
> +
> +	drm_dp_dpcd_readb(&intel_dp->aux, 0x090, &fec_dpcd);
> +	intel_dp->fec_dpcd = fec_dpcd;
> +
> +	/* For DP DSC, FEC support is must */

FEC support is only needed for DP DSC not eDP, but looks like currently this
function is only getting called on eDP init connector and not on all DP
hotplug processing. If its for DP then, even DP 1.4 version check needed.
Since here its only eDP, FEC is not mandatory infact no FEC support on eDP 1.4.

> +	if (!(intel_dp->fec_dpcd & 0x1))
> +		return;
> +
> +	/* No VDSC support for less than 8 BPC */
> +	if (intel_dp->dsc_dpcd[0xa] < DP_DSC_8_BPC)

Use some #define instead of 0xa ( I had used intel_dp->dsc_dpcd[DP_DSC_BPC - DP_DSC_SUPPORT])

> +		return;

What happens to the cached values when you return from this function in case of
no VDSC support. Shouldnt they be reset now that it cannot be implemented.

> +
> +	if (intel_dp->dsc_dpcd[0xa] & DP_DSC_8_BPC)
> +		DRM_INFO("8 Bits per color support\n");
> +	if (intel_dp->dsc_dpcd[0xa] & DP_DSC_10_BPC)
> +		DRM_INFO("10 Bits per color support\n");
> +	if (intel_dp->dsc_dpcd[0xa] & DP_DSC_12_BPC)
> +		DRM_INFO("12 Bits per color support\n");
> +
> +	dp_dsc_caps->dsc_major_ver = intel_dp->dsc_dpcd[1] & DP_DSC_MAJOR_MASK;
> +	dp_dsc_caps->dsc_minor_ver = (intel_dp->dsc_dpcd[1] &
> +				DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT;
> +
> +	rcbuffer_blocksize = intel_dp->dsc_dpcd[2] & 0x3;
> +
> +	switch (rcbuffer_blocksize) {
> +	case 0:
> +		dp_dsc_caps->rcbuffer_blocksize = 1;
> +		break;
> +	case 1:
> +		dp_dsc_caps->rcbuffer_blocksize = 4;
> +		break;
> +	case 2:
> +		dp_dsc_caps->rcbuffer_blocksize = 16;
> +		break;
> +	case 3:
> +		dp_dsc_caps->rcbuffer_blocksize = 64;
> +		break;
> +	default:
> +		break;
> +
> +	}
> +	dp_dsc_caps->rcbuffer_size_in_blocks = intel_dp->dsc_dpcd[3] + 1;
> +
> +	dp_dsc_caps->rcbuffer_size =
> +			dp_dsc_caps->rcbuffer_size_in_blocks *
> +			dp_dsc_caps->rcbuffer_blocksize * 1024 * 8;
> +

Move this rc buffer computation to a helper. (refer to my patch)

> +	dp_dsc_caps->slice_caps = intel_dp->dsc_dpcd[4];

get this again in a  helper. Refer to my patch.

> +	line_buffer_bit_depth = intel_dp->dsc_dpcd[5];
> +
> +	if (line_buffer_bit_depth == 8)
> +		dp_dsc_caps->line_buffer_bit_depth = intel_dp->dsc_dpcd[5];
> +	else
> +		dp_dsc_caps->line_buffer_bit_depth = intel_dp->dsc_dpcd[5] + 9;

Move these above to helpers and use #defines for these numerical values making it
more readable.

> +
> +	dp_dsc_caps->is_block_pred_supported = intel_dp->dsc_dpcd[6] &
> +					DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
> +
> +	dp_dsc_caps->sink_support_max_bpp = intel_dp->dsc_dpcd[7];
> +	sink_support_max_bpp_msb = (intel_dp->dsc_dpcd[8] & 0x3) << 8;
> +	dp_dsc_caps->sink_support_max_bpp |= sink_support_max_bpp_msb;
> +
> +	dp_dsc_caps->color_format_caps = intel_dp->dsc_dpcd[9];
> +	dp_dsc_caps->color_depth_caps = intel_dp->dsc_dpcd[0xa];
> +}
> +
> +static void intel_dp_get_compression_data(struct intel_dp *intel_dp,
> +					struct dp_sink_dsc_caps dp_dsc_caps)
> +{
> +	if (!dp_dsc_caps.is_dsc_supported)
> +		return;

Directly compute from dsc_dpcd[0] & compression_supported

> +
> +	intel_dp->compr_params.compression_support =
> +						dp_dsc_caps.is_dsc_supported;
> +	intel_dp->compr_params.dsc_cfg.dsc_version_major =
> +						dp_dsc_caps.dsc_major_ver;
> +	intel_dp->compr_params.dsc_cfg.dsc_version_minor =
> +						dp_dsc_caps.dsc_minor_ver;
> +
> +	/* By default set bpc to 8 */
> +	intel_dp->compr_params.dsc_cfg.bits_per_component = 8;
> +
> +	/* Take the max for Bits per component */
> +	if (intel_dp->dsc_dpcd[0xa] & DP_DSC_8_BPC)
> +		intel_dp->compr_params.dsc_cfg.bits_per_component = 8;
> +	if (intel_dp->dsc_dpcd[0xa] & DP_DSC_10_BPC)
> +		intel_dp->compr_params.dsc_cfg.bits_per_component = 10;
> +	if (intel_dp->dsc_dpcd[0xa] & DP_DSC_12_BPC)
> +		intel_dp->compr_params.dsc_cfg.bits_per_component = 12;
> +

Move this to a separate helper computing max bpc from dsc_dpcd

> +	intel_dp->compr_params.compression_bpp =
> +					dp_dsc_caps.sink_support_max_bpp >> 4;

Compute in a helper (refer to my patch)

> +	intel_dp->compr_params.dsc_cfg.bits_per_pixel =
> +					dp_dsc_caps.sink_support_max_bpp;
> +	intel_dp->compr_params.dsc_cfg.convert_rgb = dp_dsc_caps.RGB_support;
> +	intel_dp->compr_params.dsc_cfg.enable422 = dp_dsc_caps.YCbCr422_support;
> +	intel_dp->compr_params.dsc_cfg.block_pred_enable =
> +					dp_dsc_caps.is_block_pred_supported;
> +
> +	/* Always try to enable 2 DSC instances, by default */
> +	intel_dp->compr_params.dsc_cfg.num_vdsc_instances = 2;
> +
> +	if (dp_dsc_caps.four_slice_per_line_support)
> +		intel_dp->compr_params.dsc_cfg.slice_count = 4;
> +	else if (dp_dsc_caps.two_slice_per_line_support)
> +		intel_dp->compr_params.dsc_cfg.slice_count = 2;
> +	else if (dp_dsc_caps.one_slice_per_line_support) {
> +		/*
> +		 * Cannot use 2 DSC engines simultaneously when
> +		 * slice per line support is only 1
> +		 */
> +		intel_dp->compr_params.dsc_cfg.slice_count = 1;
> +		intel_dp->compr_params.dsc_cfg.num_vdsc_instances = 1;
> +	} else
> +		DRM_INFO("Slice count not supported:%d\n",
> +							dp_dsc_caps.slice_caps);

Move the slice count computation to a helper (refer to my patch)

> +
> +	intel_dp->compr_params.dsc_cfg.line_buf_depth =
> +					dp_dsc_caps.line_buffer_bit_depth;
> +}
> +
>  static bool intel_edp_init_connector(struct intel_dp *intel_dp,
>  				     struct intel_connector *intel_connector)
>  {
> @@ -5892,6 +6035,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
>  	struct drm_display_mode *fixed_mode = NULL;
>  	struct drm_display_mode *alt_fixed_mode = NULL;
>  	struct drm_display_mode *downclock_mode = NULL;
> +	struct dp_sink_dsc_caps sink_dp_dsc_caps = {0};
>  	bool has_dpcd;
>  	struct drm_display_mode *scan;
>  	struct edid *edid;
> @@ -5930,6 +6074,12 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
>  		goto out_vdd_off;
>  	}
>  
> +	/* Get DSC capability of DP sink */
> +	if (INTEL_GEN(dev_priv) >= 9) {
> +		intel_dp_sink_get_dsc_capability(intel_dp, &sink_dp_dsc_caps);
> +		intel_dp_get_compression_data(intel_dp, sink_dp_dsc_caps);
> +	}
> +

This can be moved to intel_edp_init_dpcd

>  	mutex_lock(&dev->mode_config.mutex);
>  	edid = drm_get_edid(connector, &intel_dp->aux.ddc);
>  	if (edid) {
> @@ -5968,6 +6118,23 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
>  	}
>  	mutex_unlock(&dev->mode_config.mutex);
>  
> +	if (intel_dp->compr_params.compression_support) {
> +		intel_dp->compr_params.dsc_cfg.pic_width = fixed_mode->hdisplay;
> +		intel_dp->compr_params.dsc_cfg.pic_height =
> +							fixed_mode->vdisplay;
> +		intel_dp->compr_params.dsc_cfg.slice_width = DIV_ROUND_UP(
> +				intel_dp->compr_params.dsc_cfg.pic_width,
> +				intel_dp->compr_params.dsc_cfg.slice_count);
> +
> +		/* slice height data is not available from dpcd */
> +		if (intel_dp->compr_params.dsc_cfg.pic_height % 8 == 0)
> +			intel_dp->compr_params.dsc_cfg.slice_height = 8;
> +		if (intel_dp->compr_params.dsc_cfg.pic_height % 4 == 0)
> +			intel_dp->compr_params.dsc_cfg.slice_height = 4;
> +		if (intel_dp->compr_params.dsc_cfg.pic_height % 2 == 0)
> +			intel_dp->compr_params.dsc_cfg.slice_height = 2;

This configuration should happen at compute_config time where we configure the pipe for
a specific mode, also configure dsc_config.
This dsc_config should be a intel_crtc_state field. Please refer to my patch following on M-L soon.

Manasi

> +	}
> +
>  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
>  		intel_dp->edp_notifier.notifier_call = edp_notify_handler;
>  		register_reboot_notifier(&intel_dp->edp_notifier);
> -- 
> 1.9.1
> 
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Re: [PATCH 00/10] Enabling VDSC in i915 driver for GLK

[Singh, Gaurav K]

On 2/24/2018 4:23 AM, Manasi Navare wrote:
> Thanks for the patches. I am working on the DSC support on i915 for eDP/DP
> as well. Looking at the patches below, this is specific to VDSC enabling for eDP
> panels and not for the external DP.
> So please mention that specifically in the cover letter as well.
  Since most of the VDSC functionality will be same across EDP and DP, i 
mentioned DP in generic terms.
But no worries, i will mention EDP explicitly in the next patch set 
while fixing the review comments.
>
> On Fri, Feb 23, 2018 at 09:25:43PM +0530, Gaurav K Singh wrote:
>> Display  manufacturers are turning to higher-resolution displays
>> to differentiate their products. The increased pixel counts have
>> required increased bandwidth over the links that drive these displays.
>> However, advances in physical layer technology have not kept up
>> with the increases in pixel counts.
>>
>> These factors have created a need for compression on display links.
>> The Video Electronics Standards Association(VESA),in liaison with the
>> MIPI Alliance, has developed an industry standard Display Stream Compression(DSC)
>> for interoperable, visually lossless compression over display links.
>>
>> These patches enable VDSC in i915 gfx driver for Gen9,Gen10 platforms
> Please specify that this enables VDSC for eDp in i915 gfx driver.
Sure, will take care.
>
>> and provide basic code for future platforms.
>>
>> Testing:
>> Did testing on GLK RVP. By default GLK RVP has non-DSC EDP panel, there was no regression with these patches.
>>
>> BA Chrome Team (OTC) do not have EDP panel which supports DSC.
>> Trying to arrrage DSC EDP panel from other teams in BA, hopeful to get it in few weeks.
>>
> I do have a DSC eDP panel here in Oregon and can volunteer for testing your patches with that on GLK RVP.
>
> Manasi
I am hopeful to get the panel sometime late next week. If i am not able 
to get it, I would surely take your help to test my patches.
>   
>> Dropping the patches to get the review started.
>>
>> Gaurav K Singh (10):
>>    drm: i915: Defining Compression Capabilities
>>    drm: i915: Get DSC capability from DP sink
>>    drm: i915: Enable/Disable DSC in DP sink
>>    drm: i915: Compute RC & DSC parameters
>>    drm: i915: Define Picture Parameter Set
>>    drm/i915: Populate PPS Secondary Data Pkt for Sink
>>    drm: i915: Define VDSC regs and DSC params
>>    drm: i915: Enable VDSC in Source
>>    drm: i915: Disable VDSC from Source
>>    drm/i915: Encoder enable/disable seq wrt DSC
>>
>>   drivers/gpu/drm/i915/Makefile        |    1 +
>>   drivers/gpu/drm/i915/i915_drv.h      |  589 ++++++++++++++++
>>   drivers/gpu/drm/i915/i915_reg.h      |  451 ++++++++++++
>>   drivers/gpu/drm/i915/intel_ddi.c     |    4 +
>>   drivers/gpu/drm/i915/intel_display.c |   20 +
>>   drivers/gpu/drm/i915/intel_dp.c      |  182 +++++
>>   drivers/gpu/drm/i915/intel_drv.h     |   64 ++
>>   drivers/gpu/drm/i915/intel_vdsc.c    | 1243 ++++++++++++++++++++++++++++++++++
>>   include/drm/drm_dp_helper.h          |    3 +
>>   9 files changed, 2557 insertions(+)
>>   create mode 100644 drivers/gpu/drm/i915/intel_vdsc.c
>>
>> -- 
>> 1.9.1
>>
>> _______________________________________________
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>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH 01/10] drm: i915: Defining Compression Capabilities

[Singh, Gaurav K]

On 2/24/2018 5:24 AM, Manasi Navare wrote:
> On Fri, Feb 23, 2018 at 09:25:44PM +0530, Gaurav K Singh wrote:
>> For Vesa Display Stream compression, defining structures for
>> compression capabilities to be stored in encoder.
>>
>> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_drv.h  | 125 +++++++++++++++++++++++++++++++++++++++
>>   drivers/gpu/drm/i915/intel_drv.h |  62 +++++++++++++++++++
>>   include/drm/drm_dp_helper.h      |   1 +
>>   3 files changed, 188 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 0d8cb74e7d02..4b1c323c0925 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -780,6 +780,131 @@ struct i915_psr {
>>   	void (*setup_vsc)(struct intel_dp *, const struct intel_crtc_state *);
>>   };
>>   
>> +/* DSC Configuration structure */
>> +#define NUM_BUF_RANGES		15
>> +
>> +/* Configuration for a single Rate Control model range */
>> +struct rc_range_parameters {
>> +	/* Min Quantization Parameters allowed for this range */
>> +	unsigned long range_min_qp;
> Its only a 5 bit value, so uint_8 should be good, why have a unsigned long.
> Same for max_qp which is 5 bits and bpg_offset which is 6 bits.
> Please consider these for the parameters below.
My bad, will take care in next patchset.
>
>> +	/* Max Quantization Parameters allowed for this range */
>> +	unsigned long range_max_qp;
>> +	/* Bits/group offset to apply to target for this group */
>> +	unsigned long range_bpg_offset;
>> +};
>> +
>> +struct vdsc_config {
>> +	/* Bits / component for previous reconstructed line buffer */
>> +	unsigned long line_buf_depth;
>> +	/*
>> +	 * Rate control buffer size (in bits); not in PPS,
>> +	 * used only in C model for checking overflow
>> +	 */
>> +	unsigned long rc_bits;
>> +	/* Bits per component to code (must be 8, 10, or 12) */
>> +	unsigned long bits_per_component;
>> +	/*
>> +	 * Flag indicating to do RGB - YCoCg conversion
>> +	 * and back (should be 1 for RGB input)
>> +	 */
>> +	bool convert_rgb;
>> +	unsigned long slice_count;
> For eDP, it can be max 4, why unsigned long?
Will take care.
>
>> +	/* Slice Width */
>> +	unsigned long slice_width;
>> +	/* Slice Height */
>> +	unsigned long slice_height;
>> +	/*
>> +	 * 4:2:2 enable mode (from PPS, 4:2:2 conversion happens
>> +	 * outside of DSC encode/decode algorithm)
>> +	 */
>> +	bool enable422;
>> +	/* Picture Width */
>> +	unsigned long pic_width;
>> +	/* Picture Height */
>> +	unsigned long pic_height;
>> +	/* Offset to bits/group used by RC to determine QP adjustment */
>> +	unsigned long rc_tgt_offset_high;
>> +	/* Offset to bits/group used by RC to determine QP adjustment */
>> +	unsigned long rc_tgt_offset_low;
>> +	/* Bits/pixel target << 4 (ie., 4 fractional bits) */
>> +	unsigned long bits_per_pixel;
>> +	/*
>> +	 * Factor to determine if an edge is present based
>> +	 * on the bits produced
>> +	 */
>> +	unsigned long rc_edge_factor;
>> +	/* Slow down incrementing once the range reaches this value */
>> +	unsigned long rc_quant_incr_limit1;
>> +	/* Slow down incrementing once the range reaches this value */
>> +	unsigned long rc_quant_incr_limit0;
>> +	/* Number of pixels to delay the initial transmission */
>> +	unsigned long initial_xmit_delay;
>> +	/* Number of pixels to delay the VLD on the decoder,not including SSM */
>> +	unsigned long  initial_dec_delay;
>> +	/* Block prediction range (in pixels) */
>> +	bool block_pred_enable;
>> +	/* Bits/group offset to use for first line of the slice */
>> +	unsigned long first_line_bpg_Ofs;
>> +	/* Value to use for RC model offset at slice start */
>> +	unsigned long initial_offset;
>> +	/* X position in the picture of top-left corner of slice */
>> +	unsigned long x_start;
>> +	/* Y position in the picture of top-left corner of slice */
>> +	unsigned long y_start;
>> +	/* Thresholds defining each of the buffer ranges */
>> +	unsigned long rc_buf_thresh[NUM_BUF_RANGES - 1];
>> +	/* Parameters for each of the RC ranges */
>> +	struct rc_range_parameters rc_range_params[NUM_BUF_RANGES];
>> +	/* Total size of RC model */
>> +	unsigned long rc_model_size;
>> +	/* Minimum QP where flatness information is sent */
>> +	unsigned long flatness_minQp;
>> +	/* Maximum QP where flatness information is sent */
>> +	unsigned long flatness_maxQp;
>> +	/*
>> +	 * MAX-MIN for all components is required to
>> +	 * be <= this value for flatness to be used
>> +	 */
>> +	unsigned long flatness_det_thresh;
>> +	/* Initial value for scale factor */
>> +	unsigned long initial_scale_value;
>> +	/* Decrement scale factor every scale_decrement_interval groups */
>> +	unsigned long scale_decrement_interval;
>> +	/* Increment scale factor every scale_increment_interval groups */
>> +	unsigned long scale_increment_interval;
>> +	/* Non-first line BPG offset to use */
>> +	unsigned long nfl_bpg_offset;
>> +	/* BPG offset used to enforce slice bit */
>> +	unsigned long slice_bpg_offset;
>> +	/* Final RC linear transformation offset value */
>> +	unsigned long final_offset;
>> +	/* Enable on-off VBR (ie., disable stuffing bits) */
>> +	bool vbr_enable;
>> +	/* Mux word size (in bits) for SSM mode */
>> +	unsigned long mux_word_size;
>> +	/*
>> +	 * The (max) size in bytes of the "chunks" that are
>> +	 * used in slice multiplexing
>> +	 */
>> +	unsigned long chunk_size;
>> +	/* Placeholder for PPS identifier */
>> +	unsigned long pps_identifier;
>> +	/* DSC Minor Version */
>> +	unsigned long dsc_version_minor;
>> +	/* DSC Major version */
>> +	unsigned long dsc_version_major;
>> +	/* Number of VDSC engines */
>> +	unsigned long num_vdsc_instances;
>> +};
>> +
>> +/* Compression caps stored in encoder */
>> +struct i915_compression_params {
>> +	bool compression_support;
>> +	unsigned long compression_bpp;
> Does this indicate the 16 bit value with 4 fractional bits? May be add a comment for that.
Yes, it indicates that only. Will add a comment for that.
>
>> +	struct vdsc_config dsc_cfg;
>> +	unsigned char slice_count;
>> +};
> There is probably no need to have these convoluted structs, the compressed bpp and slice count
> are obtained directly from DPCDs which can be populated where needed with the helpers instead
> of populating them into dp_dsc_sink_cap and then populating i915_compression_params.slice_count/
> compressed_bpp.
>
> Again I have helpers for those already currently on the internal M-L.
> intel_dp can then only have compression_support and dsc_cfg.
My idea was to use a local struct variable named dp_sink_dsc_caps and 
then get the required values from DPCDs and do the required bitwise 
operations if needed .Using this local struct to populate dsc_cfg.
But i do agree and will populate dsc_cfg directly from DPCDs in the next 
patchset without using the local struct variable.
>> +
>>   enum intel_pch {
>>   	PCH_NONE = 0,	/* No PCH present */
>>   	PCH_IBX,	/* Ibexpeak PCH */
>> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
>> index 5853d92a6512..6e1b907990bf 100644
>> --- a/drivers/gpu/drm/i915/intel_drv.h
>> +++ b/drivers/gpu/drm/i915/intel_drv.h
>> @@ -954,6 +954,63 @@ struct intel_dp_compliance {
>>   	u8 test_lane_count;
>>   };
>>   
>> +/* Vesa Display Stream Capability of DP Sink */
>> +struct dp_sink_dsc_caps {
>> +	/* Display Stream Compression Support */
>> +	bool is_dsc_supported;
>> +	u8 dsc_major_ver;
>> +	u8 dsc_minor_ver;
>> +	u16 rcbuffer_blocksize;
>> +	/* n+1 value */
>> +	u16 rcbuffer_size_in_blocks;
>> +	unsigned long rcbuffer_size;
>> +
>> +	union {
>> +		u8 slice_caps;
>> +		struct {
>> +			u8 one_slice_per_line_support : 1;
>> +			u8 two_slice_per_line_support : 1;
>> +			u8 slice_caps_reserved1 : 1;
>> +			u8 four_slice_per_line_support : 1;
>> +			u8 slice_caps_reserved2 : 4;
>> +		};
>> +	};
>> +	/* Decode line buffer bits of precision */
>> +	unsigned long line_buffer_bit_depth;
>> +	bool is_block_pred_supported;
>> +	unsigned long sink_support_max_bpp;
>> +
>> +	union {
>> +		u8 color_format_caps;
>> +		struct {
>> +			u8 RGB_support : 1;
>> +			u8 YCbCr444_support : 1;
>> +			u8 YCbCr422_support : 1;
>> +			u8 color_format_caps_reserved : 5;
>> +		};
>> +	};
>> +
>> +	union {
>> +		u8 color_depth_caps;
>> +		struct {
>> +			u8 color_depth_caps_reserved1 : 1;
>> +			u8 support_8bpc : 1;
>> +			u8 support_10bpc : 1;
>> +			u8 support_12bpc : 1;
>> +			u8 color_depth_caps_reserved2 : 4;
>> +		};
>> +	};
>> +
>> +	u16 slice_height;
>> +	u16 slice_width;
>> +	/* Y Resolution */
>> +	u16 pic_height;
>> +	/* X Resolution */
>> +	u16 pic_width;
>> +};
> Since we will cache the entire DPCD register set for DSC, we really dont need to have structure
> for saving those values, they can be computed whenever needed using helpers/macros that read the cached
> DPCD values. That is the convention followed for values obtained from DP DPCD in rest of the driver.
> I have the patches for helpers that give these values but currently on internal M-L.
>
> Manasi
>
>> +
>> +
>> +
>>   struct intel_dp {
>>   	i915_reg_t output_reg;
>>   	i915_reg_t aux_ch_ctl_reg;
>> @@ -971,6 +1028,8 @@ struct intel_dp {
>>   	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
>>   	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
>>   	uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
>> +	uint8_t dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE];
>> +	uint8_t fec_dpcd;
>>   	/* source rates */
>>   	int num_source_rates;
>>   	const int *source_rates;
>> @@ -1046,6 +1105,9 @@ struct intel_dp {
>>   
>>   	/* Displayport compliance testing */
>>   	struct intel_dp_compliance compliance;
>> +
>> +	/* For Vesa Display Stream Compression Support */
>> +	struct i915_compression_params compr_params;
>>   };
>>   
>>   struct intel_lspcon {
>> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
>> index da58a428c8d7..05f811c50d28 100644
>> --- a/include/drm/drm_dp_helper.h
>> +++ b/include/drm/drm_dp_helper.h
>> @@ -896,6 +896,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
>>   #define DP_RECEIVER_CAP_SIZE		0xf
>>   #define EDP_PSR_RECEIVER_CAP_SIZE	2
>>   #define EDP_DISPLAY_CTL_CAP_SIZE	3
>> +#define DP_DSC_RECEIVER_CAP_SIZE	0xb
>>   
>>   void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
>>   void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
>> -- 
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

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Re: [PATCH 08/10] drm: i915: Enable VDSC in Source

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 4235 bytes --]

Hi Gaurav,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on next-20180223]
[cannot apply to drm-intel/for-linux-next drm/drm-next v4.16-rc3 v4.16-rc2 v4.16-rc1 v4.16-rc3]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Gaurav-K-Singh/Enabling-VDSC-in-i915-driver-for-GLK/20180226-114246
config: x86_64-randconfig-x009-201808 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

Note: it may well be a FALSE warning. FWIW you are at least aware of it now.
http://gcc.gnu.org/wiki/Better_Uninitialized_Warnings

All warnings (new ones prefixed by >>):

   drivers/gpu//drm/i915/intel_vdsc.c: In function 'intel_dsc_enable':
>> drivers/gpu//drm/i915/intel_vdsc.c:1164:3: warning: 'dsc_type2' may be used uninitialized in this function [-Wmaybe-uninitialized]
      configure_dsc_params_for_dsc_controller(encoder, pipe_config,
      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           &dsc_regs, dsc_type2);
           ~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu//drm/i915/intel_vdsc.c:1160:2: warning: 'dsc_type1' may be used uninitialized in this function [-Wmaybe-uninitialized]
     configure_dsc_params_for_dsc_controller(encoder, pipe_config,
     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
           &dsc_regs, dsc_type1);
           ~~~~~~~~~~~~~~~~~~~~~

vim +/dsc_type2 +1164 drivers/gpu//drm/i915/intel_vdsc.c

  1103	
  1104	void intel_dsc_enable(struct intel_encoder *encoder,
  1105					struct intel_crtc_state *pipe_config)
  1106	{
  1107		struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
  1108		struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
  1109		struct picture_parameters_set pps_params;
  1110		struct intel_dsc_regs dsc_regs;
  1111		struct drm_crtc *crtc = pipe_config->base.crtc;
  1112		struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  1113		int pipe = intel_crtc->pipe;
  1114		int dsc_type1;
  1115		int dsc_type2;
  1116		int type = encoder->type;
  1117		unsigned int dss_ctrl1_value = 0;
  1118		unsigned int dss_ctrl2_value = 0;
  1119	
  1120		if ((INTEL_GEN(dev_priv) < 9) ||
  1121					!intel_dp->compr_params.compression_support)
  1122			return;
  1123		/* TO DO: configure DSC params and program source regs */
  1124	
  1125		if (type == INTEL_OUTPUT_EDP) {
  1126			dsc_regs.dss_ctrl1_reg = DSS_CONTROL1;
  1127			dsc_regs.dss_ctrl2_reg = DSS_CONTROL2;
  1128			dsc_regs.dip_ctrl_reg = VIDEO_DIP_CTL_EDP;
  1129			dsc_regs.dip_pps_data_ctrl_reg = VIDEO_DIP_PPS_DATA_EDP_REG;
  1130			dsc_type1 = DSC_A;
  1131			dsc_type2 = DSC_C;
  1132		} else if (type == INTEL_OUTPUT_DP) {
  1133			switch (pipe) {
  1134			case PIPE_A:
  1135				dsc_regs.dss_ctrl1_reg = PIPE_DSS_CTL1_PB;
  1136				dsc_regs.dss_ctrl2_reg = PIPE_DSS_CTL2_PB;
  1137				dsc_regs.dip_ctrl_reg = VIDEO_DIP_CTL_A;
  1138				dsc_regs.dip_pps_data_ctrl_reg =
  1139							VIDEO_DIP_DRM_DATA_TRANSA_REG;
  1140				dsc_type1 = PIPEA_DSC_0;
  1141				dsc_type2 = PIPEA_DSC_1;
  1142				break;
  1143			case PIPE_B:
  1144				dsc_regs.dss_ctrl1_reg = PIPE_DSS_CTL1_PC;
  1145				dsc_regs.dss_ctrl2_reg = PIPE_DSS_CTL2_PC;
  1146				dsc_regs.dip_ctrl_reg = VIDEO_DIP_CTL_B;
  1147				dsc_regs.dip_pps_data_ctrl_reg =
  1148							VIDEO_DIP_DRM_DATA_TRANSB_REG;
  1149				dsc_type1 = PIPEB_DSC_0;
  1150				dsc_type2 = PIPEB_DSC_1;
  1151				break;
  1152			default:
  1153				return;
  1154			}
  1155		} else {
  1156			DRM_ERROR("Func:%s Unsupported port:%d\n", __func__, type);
  1157		}
  1158	
  1159		intel_dsc_regs_init(encoder, &dsc_regs, dsc_type1);
> 1160		configure_dsc_params_for_dsc_controller(encoder, pipe_config,
  1161								&dsc_regs, dsc_type1);
  1162		if (intel_dp->compr_params.dsc_cfg.num_vdsc_instances != 1) {
  1163			intel_dsc_regs_init(encoder, &dsc_regs, dsc_type2);
> 1164			configure_dsc_params_for_dsc_controller(encoder, pipe_config,

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 31744 bytes --]

[-- Attachment #3: Type: text/plain, Size: 160 bytes --]

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Re: [PATCH 08/10] drm: i915: Enable VDSC in Source

[kbuild test robot]

Hi Gaurav,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on next-20180223]
[cannot apply to drm-intel/for-linux-next drm/drm-next v4.16-rc3 v4.16-rc2 v4.16-rc1 v4.16-rc3]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Gaurav-K-Singh/Enabling-VDSC-in-i915-driver-for-GLK/20180226-114246


coccinelle warnings: (new ones prefixed by >>)

>> drivers/gpu/drm/i915/intel_vdsc.c:828:2-3: Unneeded semicolon

vim +828 drivers/gpu/drm/i915/intel_vdsc.c

   771	
   772	void intel_dsc_regs_init(struct intel_encoder *encoder,
   773					struct intel_dsc_regs *dsc_regs, int dsc_type)
   774	{
   775		switch (dsc_type) {
   776		case DSC_A:
   777			dsc_regs->dsc_picture_params0 = DSCA_PICTURE_PARAMETER_SET_0;
   778			dsc_regs->dsc_picture_params1 = DSCA_PICTURE_PARAMETER_SET_1;
   779			dsc_regs->dsc_picture_params2 = DSCA_PICTURE_PARAMETER_SET_2;
   780			dsc_regs->dsc_picture_params3 = DSCA_PICTURE_PARAMETER_SET_3;
   781			dsc_regs->dsc_picture_params4 = DSCA_PICTURE_PARAMETER_SET_4;
   782			dsc_regs->dsc_picture_params5 = DSCA_PICTURE_PARAMETER_SET_5;
   783			dsc_regs->dsc_picture_params6 = DSCA_PICTURE_PARAMETER_SET_6;
   784			dsc_regs->dsc_picture_params7 = DSCA_PICTURE_PARAMETER_SET_7;
   785			dsc_regs->dsc_picture_params8 = DSCA_PICTURE_PARAMETER_SET_8;
   786			dsc_regs->dsc_picture_params9 = DSCA_PICTURE_PARAMETER_SET_9;
   787			dsc_regs->dsc_picture_params10 = DSCA_PICTURE_PARAMETER_SET_10;
   788			dsc_regs->dsc_picture_params16 = DSCA_PICTURE_PARAMETER_SET_16;
   789			dsc_regs->dsc_rc_buff_thresh0_0 = DSCA_RC_BUF_THRESH_0_0;
   790			dsc_regs->dsc_rc_buff_thresh0_1 = DSCA_RC_BUF_THRESH_0_1;
   791			dsc_regs->dsc_rc_buff_thresh1_0 = DSCA_RC_BUF_THRESH_1_0;
   792			dsc_regs->dsc_rc_buff_thresh1_1 = DSCA_RC_BUF_THRESH_1_1;
   793			dsc_regs->dsc_rc_range0_0 = DSCA_RC_RANGE_PARAMETERS_0_0;
   794			dsc_regs->dsc_rc_range0_1 = DSCA_RC_RANGE_PARAMETERS_0_1;
   795			dsc_regs->dsc_rc_range1_0 = DSCA_RC_RANGE_PARAMETERS_1_0;
   796			dsc_regs->dsc_rc_range1_1 = DSCA_RC_RANGE_PARAMETERS_1_1;
   797			dsc_regs->dsc_rc_range2_0 = DSCA_RC_RANGE_PARAMETERS_2_0;
   798			dsc_regs->dsc_rc_range2_1 = DSCA_RC_RANGE_PARAMETERS_2_1;
   799			dsc_regs->dsc_rc_range3_0 = DSCA_RC_RANGE_PARAMETERS_3_0;
   800			dsc_regs->dsc_rc_range3_1 = DSCA_RC_RANGE_PARAMETERS_3_1;
   801			break;
   802		case DSC_C:
   803			dsc_regs->dsc_picture_params0 = DSCC_PICTURE_PARAMETER_SET_0;
   804			dsc_regs->dsc_picture_params1 = DSCC_PICTURE_PARAMETER_SET_1;
   805			dsc_regs->dsc_picture_params2 = DSCC_PICTURE_PARAMETER_SET_2;
   806			dsc_regs->dsc_picture_params3 = DSCC_PICTURE_PARAMETER_SET_3;
   807			dsc_regs->dsc_picture_params4 = DSCC_PICTURE_PARAMETER_SET_4;
   808			dsc_regs->dsc_picture_params5 = DSCC_PICTURE_PARAMETER_SET_5;
   809			dsc_regs->dsc_picture_params6 = DSCC_PICTURE_PARAMETER_SET_6;
   810			dsc_regs->dsc_picture_params7 = DSCC_PICTURE_PARAMETER_SET_7;
   811			dsc_regs->dsc_picture_params8 = DSCC_PICTURE_PARAMETER_SET_8;
   812			dsc_regs->dsc_picture_params9 = DSCC_PICTURE_PARAMETER_SET_9;
   813			dsc_regs->dsc_picture_params10 = DSCC_PICTURE_PARAMETER_SET_10;
   814			dsc_regs->dsc_picture_params16 = DSCC_PICTURE_PARAMETER_SET_16;
   815			dsc_regs->dsc_rc_buff_thresh0_0 = DSCC_RC_BUF_THRESH_0_0;
   816			dsc_regs->dsc_rc_buff_thresh0_1 = DSCC_RC_BUF_THRESH_0_1;
   817			dsc_regs->dsc_rc_buff_thresh1_0 = DSCC_RC_BUF_THRESH_1_0;
   818			dsc_regs->dsc_rc_buff_thresh1_1 = DSCC_RC_BUF_THRESH_1_1;
   819			dsc_regs->dsc_rc_range0_0 = DSCC_RC_RANGE_PARAMETERS_0_0;
   820			dsc_regs->dsc_rc_range0_1 = DSCC_RC_RANGE_PARAMETERS_0_1;
   821			dsc_regs->dsc_rc_range1_0 = DSCC_RC_RANGE_PARAMETERS_1_0;
   822			dsc_regs->dsc_rc_range1_1 = DSCC_RC_RANGE_PARAMETERS_1_1;
   823			dsc_regs->dsc_rc_range2_0 = DSCC_RC_RANGE_PARAMETERS_2_0;
   824			dsc_regs->dsc_rc_range2_1 = DSCC_RC_RANGE_PARAMETERS_2_1;
   825			dsc_regs->dsc_rc_range3_0 = DSCC_RC_RANGE_PARAMETERS_3_0;
   826			dsc_regs->dsc_rc_range3_1 = DSCC_RC_RANGE_PARAMETERS_3_1;
   827			break;
 > 828		};
   829	}
   830	

---
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Re: [Intel-gfx] [PATCH 02/10] drm: i915: Get DSC capability from DP sink

[Dan Carpenter]

Hi Gaurav,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on next-20180223]
[also build test WARNING on v4.16-rc3]
[cannot apply to drm-intel/for-linux-next drm/drm-next v4.16-rc3 v4.16-rc2 v4.16-rc1]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Gaurav-K-Singh/Enabling-VDSC-in-i915-driver-for-GLK/20180226-114246

smatch warnings:
drivers/gpu/drm/i915/intel_dp.c:6379 intel_edp_init_connector() error: we previously assumed 'fixed_mode' could be null (see line 6367)

# https://github.com/0day-ci/linux/commit/0be77ee7aeeb70345533485fec0f376c0180bafa
git remote add linux-review https://github.com/0day-ci/linux
git remote update linux-review
git checkout 0be77ee7aeeb70345533485fec0f376c0180bafa
vim +/fixed_mode +6379 drivers/gpu/drm/i915/intel_dp.c

0be77ee7ae Gaurav K Singh 2018-02-23  6285  
ed92f0b239 Paulo Zanoni   2013-06-12  6286  static bool intel_edp_init_connector(struct intel_dp *intel_dp,
36b5f425dd Ville Syrjälä  2014-10-16  6287  				     struct intel_connector *intel_connector)
ed92f0b239 Paulo Zanoni   2013-06-12  6288  {
2f7734770c Ville Syrjälä  2017-11-09  6289  	struct drm_device *dev = intel_dp_to_dev(intel_dp);
fac5e23e3c Chris Wilson   2016-07-04  6290  	struct drm_i915_private *dev_priv = to_i915(dev);
2f7734770c Ville Syrjälä  2017-11-09  6291  	struct drm_connector *connector = &intel_connector->base;
ed92f0b239 Paulo Zanoni   2013-06-12  6292  	struct drm_display_mode *fixed_mode = NULL;
dc911f5bd8 Jim Bride      2017-08-09  6293  	struct drm_display_mode *alt_fixed_mode = NULL;
4f9db5b51c Pradeep Bhat   2014-04-05  6294  	struct drm_display_mode *downclock_mode = NULL;
0be77ee7ae Gaurav K Singh 2018-02-23  6295  	struct dp_sink_dsc_caps sink_dp_dsc_caps = {0};
ed92f0b239 Paulo Zanoni   2013-06-12  6296  	bool has_dpcd;
ed92f0b239 Paulo Zanoni   2013-06-12  6297  	struct drm_display_mode *scan;
ed92f0b239 Paulo Zanoni   2013-06-12  6298  	struct edid *edid;
6517d2734d Ville Syrjälä  2014-11-07  6299  	enum pipe pipe = INVALID_PIPE;
ed92f0b239 Paulo Zanoni   2013-06-12  6300  
1853a9daa1 Jani Nikula    2017-08-18  6301  	if (!intel_dp_is_edp(intel_dp))
ed92f0b239 Paulo Zanoni   2013-06-12  6302  		return true;
ed92f0b239 Paulo Zanoni   2013-06-12  6303  
97a824e156 Imre Deak      2016-06-21  6304  	/*
97a824e156 Imre Deak      2016-06-21  6305  	 * On IBX/CPT we may get here with LVDS already registered. Since the
97a824e156 Imre Deak      2016-06-21  6306  	 * driver uses the only internal power sequencer available for both
97a824e156 Imre Deak      2016-06-21  6307  	 * eDP and LVDS bail out early in this case to prevent interfering
97a824e156 Imre Deak      2016-06-21  6308  	 * with an already powered-on LVDS power sequencer.
97a824e156 Imre Deak      2016-06-21  6309  	 */
2f7734770c Ville Syrjälä  2017-11-09  6310  	if (intel_get_lvds_encoder(&dev_priv->drm)) {
97a824e156 Imre Deak      2016-06-21  6311  		WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
97a824e156 Imre Deak      2016-06-21  6312  		DRM_INFO("LVDS was detected, not registering eDP\n");
97a824e156 Imre Deak      2016-06-21  6313  
97a824e156 Imre Deak      2016-06-21  6314  		return false;
97a824e156 Imre Deak      2016-06-21  6315  	}
97a824e156 Imre Deak      2016-06-21  6316  
49e6bc51bc Ville Syrjälä  2014-10-28  6317  	pps_lock(intel_dp);
b4d06ede4e Imre Deak      2016-06-21  6318  
b4d06ede4e Imre Deak      2016-06-21  6319  	intel_dp_init_panel_power_timestamps(intel_dp);
46bd8383d8 Ville Syrjälä  2017-10-31  6320  	intel_dp_pps_init(intel_dp);
b4d06ede4e Imre Deak      2016-06-21  6321  	intel_edp_panel_vdd_sanitize(intel_dp);
b4d06ede4e Imre Deak      2016-06-21  6322  
49e6bc51bc Ville Syrjälä  2014-10-28  6323  	pps_unlock(intel_dp);
636352173a Paulo Zanoni   2014-04-22  6324  
ed92f0b239 Paulo Zanoni   2013-06-12  6325  	/* Cache DPCD and EDID for edp. */
fe5a66f91c Ville Syrjälä  2016-07-29  6326  	has_dpcd = intel_edp_init_dpcd(intel_dp);
ed92f0b239 Paulo Zanoni   2013-06-12  6327  
fe5a66f91c Ville Syrjälä  2016-07-29  6328  	if (!has_dpcd) {
ed92f0b239 Paulo Zanoni   2013-06-12  6329  		/* if this fails, presume the device is a ghost */
ed92f0b239 Paulo Zanoni   2013-06-12  6330  		DRM_INFO("failed to retrieve link info, disabling eDP\n");
b4d06ede4e Imre Deak      2016-06-21  6331  		goto out_vdd_off;
ed92f0b239 Paulo Zanoni   2013-06-12  6332  	}
ed92f0b239 Paulo Zanoni   2013-06-12  6333  
0be77ee7ae Gaurav K Singh 2018-02-23  6334  	/* Get DSC capability of DP sink */
0be77ee7ae Gaurav K Singh 2018-02-23  6335  	if (INTEL_GEN(dev_priv) >= 9) {
0be77ee7ae Gaurav K Singh 2018-02-23  6336  		intel_dp_sink_get_dsc_capability(intel_dp, &sink_dp_dsc_caps);
0be77ee7ae Gaurav K Singh 2018-02-23  6337  		intel_dp_get_compression_data(intel_dp, sink_dp_dsc_caps);
0be77ee7ae Gaurav K Singh 2018-02-23  6338  	}
0be77ee7ae Gaurav K Singh 2018-02-23  6339  
060c877848 Daniel Vetter  2014-03-21  6340  	mutex_lock(&dev->mode_config.mutex);
0b99836f23 Jani Nikula    2014-03-14  6341  	edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b239 Paulo Zanoni   2013-06-12  6342  	if (edid) {
ed92f0b239 Paulo Zanoni   2013-06-12  6343  		if (drm_add_edid_modes(connector, edid)) {
ed92f0b239 Paulo Zanoni   2013-06-12  6344  			drm_mode_connector_update_edid_property(connector,
ed92f0b239 Paulo Zanoni   2013-06-12  6345  								edid);
ed92f0b239 Paulo Zanoni   2013-06-12  6346  		} else {
ed92f0b239 Paulo Zanoni   2013-06-12  6347  			kfree(edid);
ed92f0b239 Paulo Zanoni   2013-06-12  6348  			edid = ERR_PTR(-EINVAL);
ed92f0b239 Paulo Zanoni   2013-06-12  6349  		}
ed92f0b239 Paulo Zanoni   2013-06-12  6350  	} else {
ed92f0b239 Paulo Zanoni   2013-06-12  6351  		edid = ERR_PTR(-ENOENT);
ed92f0b239 Paulo Zanoni   2013-06-12  6352  	}
ed92f0b239 Paulo Zanoni   2013-06-12  6353  	intel_connector->edid = edid;
ed92f0b239 Paulo Zanoni   2013-06-12  6354  
dc911f5bd8 Jim Bride      2017-08-09  6355  	/* prefer fixed mode from EDID if available, save an alt mode also */
ed92f0b239 Paulo Zanoni   2013-06-12  6356  	list_for_each_entry(scan, &connector->probed_modes, head) {
ed92f0b239 Paulo Zanoni   2013-06-12  6357  		if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
ed92f0b239 Paulo Zanoni   2013-06-12  6358  			fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b51c Pradeep Bhat   2014-04-05  6359  			downclock_mode = intel_dp_drrs_init(
4f9db5b51c Pradeep Bhat   2014-04-05  6360  						intel_connector, fixed_mode);
dc911f5bd8 Jim Bride      2017-08-09  6361  		} else if (!alt_fixed_mode) {
dc911f5bd8 Jim Bride      2017-08-09  6362  			alt_fixed_mode = drm_mode_duplicate(dev, scan);
ed92f0b239 Paulo Zanoni   2013-06-12  6363  		}
ed92f0b239 Paulo Zanoni   2013-06-12  6364  	}
ed92f0b239 Paulo Zanoni   2013-06-12  6365  
ed92f0b239 Paulo Zanoni   2013-06-12  6366  	/* fallback to VBT if available for eDP */
ed92f0b239 Paulo Zanoni   2013-06-12 @6367  	if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
ed92f0b239 Paulo Zanoni   2013-06-12  6368  		fixed_mode = drm_mode_duplicate(dev,
ed92f0b239 Paulo Zanoni   2013-06-12  6369  					dev_priv->vbt.lfp_lvds_vbt_mode);
df457245b5 Ville Syrjälä  2016-05-31  6370  		if (fixed_mode) {
                                                            ^^^^^^^^^^
Check for NULL.

ed92f0b239 Paulo Zanoni   2013-06-12  6371  			fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
df457245b5 Ville Syrjälä  2016-05-31  6372  			connector->display_info.width_mm = fixed_mode->width_mm;
df457245b5 Ville Syrjälä  2016-05-31  6373  			connector->display_info.height_mm = fixed_mode->height_mm;
df457245b5 Ville Syrjälä  2016-05-31  6374  		}
ed92f0b239 Paulo Zanoni   2013-06-12  6375  	}
060c877848 Daniel Vetter  2014-03-21  6376  	mutex_unlock(&dev->mode_config.mutex);
ed92f0b239 Paulo Zanoni   2013-06-12  6377  
0be77ee7ae Gaurav K Singh 2018-02-23  6378  	if (intel_dp->compr_params.compression_support) {
0be77ee7ae Gaurav K Singh 2018-02-23 @6379  		intel_dp->compr_params.dsc_cfg.pic_width = fixed_mode->hdisplay;
                                                                                                   ^^^^^^^^^^^^^^^^^^^^^
Not checked.

0be77ee7ae Gaurav K Singh 2018-02-23  6380  		intel_dp->compr_params.dsc_cfg.pic_height =
0be77ee7ae Gaurav K Singh 2018-02-23  6381  							fixed_mode->vdisplay;
0be77ee7ae Gaurav K Singh 2018-02-23  6382  		intel_dp->compr_params.dsc_cfg.slice_width = DIV_ROUND_UP(
0be77ee7ae Gaurav K Singh 2018-02-23  6383  				intel_dp->compr_params.dsc_cfg.pic_width,
0be77ee7ae Gaurav K Singh 2018-02-23  6384  				intel_dp->compr_params.dsc_cfg.slice_count);
0be77ee7ae Gaurav K Singh 2018-02-23  6385  
0be77ee7ae Gaurav K Singh 2018-02-23  6386  		/* slice height data is not available from dpcd */
0be77ee7ae Gaurav K Singh 2018-02-23  6387  		if (intel_dp->compr_params.dsc_cfg.pic_height % 8 == 0)
0be77ee7ae Gaurav K Singh 2018-02-23  6388  			intel_dp->compr_params.dsc_cfg.slice_height = 8;
0be77ee7ae Gaurav K Singh 2018-02-23  6389  		if (intel_dp->compr_params.dsc_cfg.pic_height % 4 == 0)
0be77ee7ae Gaurav K Singh 2018-02-23  6390  			intel_dp->compr_params.dsc_cfg.slice_height = 4;
0be77ee7ae Gaurav K Singh 2018-02-23  6391  		if (intel_dp->compr_params.dsc_cfg.pic_height % 2 == 0)
0be77ee7ae Gaurav K Singh 2018-02-23  6392  			intel_dp->compr_params.dsc_cfg.slice_height = 2;
0be77ee7ae Gaurav K Singh 2018-02-23  6393  	}
0be77ee7ae Gaurav K Singh 2018-02-23  6394  
920a14b245 Tvrtko Ursulin 2016-10-14  6395  	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
01527b3127 Clint Taylor   2014-07-07  6396  		intel_dp->edp_notifier.notifier_call = edp_notify_handler;
01527b3127 Clint Taylor   2014-07-07  6397  		register_reboot_notifier(&intel_dp->edp_notifier);
6517d2734d Ville Syrjälä  2014-11-07  6398  
6517d2734d Ville Syrjälä  2014-11-07  6399  		/*
6517d2734d Ville Syrjälä  2014-11-07  6400  		 * Figure out the current pipe for the initial backlight setup.
6517d2734d Ville Syrjälä  2014-11-07  6401  		 * If the current pipe isn't valid, try the PPS pipe, and if that
6517d2734d Ville Syrjälä  2014-11-07  6402  		 * fails just assume pipe A.
6517d2734d Ville Syrjälä  2014-11-07  6403  		 */
9f2bdb006a Ville Syrjälä  2016-12-14  6404  		pipe = vlv_active_pipe(intel_dp);
6517d2734d Ville Syrjälä  2014-11-07  6405  
6517d2734d Ville Syrjälä  2014-11-07  6406  		if (pipe != PIPE_A && pipe != PIPE_B)
6517d2734d Ville Syrjälä  2014-11-07  6407  			pipe = intel_dp->pps_pipe;
6517d2734d Ville Syrjälä  2014-11-07  6408  
6517d2734d Ville Syrjälä  2014-11-07  6409  		if (pipe != PIPE_A && pipe != PIPE_B)
6517d2734d Ville Syrjälä  2014-11-07  6410  			pipe = PIPE_A;
6517d2734d Ville Syrjälä  2014-11-07  6411  
6517d2734d Ville Syrjälä  2014-11-07  6412  		DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
6517d2734d Ville Syrjälä  2014-11-07  6413  			      pipe_name(pipe));
01527b3127 Clint Taylor   2014-07-07  6414  	}
01527b3127 Clint Taylor   2014-07-07  6415  
dc911f5bd8 Jim Bride      2017-08-09  6416  	intel_panel_init(&intel_connector->panel, fixed_mode, alt_fixed_mode,
dc911f5bd8 Jim Bride      2017-08-09  6417  			 downclock_mode);
5507faeb03 Jani Nikula    2015-09-14  6418  	intel_connector->panel.backlight.power = intel_edp_backlight_power;
6517d2734d Ville Syrjälä  2014-11-07  6419  	intel_panel_setup_backlight(connector, pipe);
ed92f0b239 Paulo Zanoni   2013-06-12  6420  
ed92f0b239 Paulo Zanoni   2013-06-12  6421  	return true;
b4d06ede4e Imre Deak      2016-06-21  6422  
b4d06ede4e Imre Deak      2016-06-21  6423  out_vdd_off:
b4d06ede4e Imre Deak      2016-06-21  6424  	cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
b4d06ede4e Imre Deak      2016-06-21  6425  	/*
b4d06ede4e Imre Deak      2016-06-21  6426  	 * vdd might still be enabled do to the delayed vdd off.
b4d06ede4e Imre Deak      2016-06-21  6427  	 * Make sure vdd is actually turned off here.
b4d06ede4e Imre Deak      2016-06-21  6428  	 */
b4d06ede4e Imre Deak      2016-06-21  6429  	pps_lock(intel_dp);
b4d06ede4e Imre Deak      2016-06-21  6430  	edp_panel_vdd_off_sync(intel_dp);
b4d06ede4e Imre Deak      2016-06-21  6431  	pps_unlock(intel_dp);
b4d06ede4e Imre Deak      2016-06-21  6432  
b4d06ede4e Imre Deak      2016-06-21  6433  	return false;
ed92f0b239 Paulo Zanoni   2013-06-12  6434  }
ed92f0b239 Paulo Zanoni   2013-06-12  6435