* [PATCH v3 0/2] CNL port refactoring
@ 2018-03-13 4:16 Mahesh Kumar
2018-03-13 4:16 ` [PATCH v3 1/2] drm/i915/cnl; Add macro to get PORT_TX register Mahesh Kumar
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Mahesh Kumar @ 2018-03-13 4:16 UTC (permalink / raw)
To: intel-gfx; +Cc: lucas.demarchi, rodrigo.vivi
This series fixes CNL PORT_TX_DW5/7_LNO_D register address.
This series also introduces macros to get register address of
CNL_PORT_TX registers instead of defining for each DW instance.
changes since V1:
completely kill _MMIO_PORT6 macro
changes since V2:
use underscore prefix in macro
merge patch 1 and 2
Mahesh Kumar (2):
drm/i915/cnl; Add macro to get PORT_TX register
drm/i915/cnl: Kill _MMIO_PORT6 macro
drivers/gpu/drm/i915/i915_reg.h | 147 ++++++++++++----------------------------
1 file changed, 44 insertions(+), 103 deletions(-)
--
2.14.1
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^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v3 1/2] drm/i915/cnl; Add macro to get PORT_TX register 2018-03-13 4:16 [PATCH v3 0/2] CNL port refactoring Mahesh Kumar @ 2018-03-13 4:16 ` Mahesh Kumar 2018-03-13 4:16 ` [PATCH v3 2/2] drm/i915/cnl: Kill _MMIO_PORT6 macro Mahesh Kumar ` (2 subsequent siblings) 3 siblings, 0 replies; 6+ messages in thread From: Mahesh Kumar @ 2018-03-13 4:16 UTC (permalink / raw) To: intel-gfx; +Cc: lucas.demarchi, rodrigo.vivi This patch creates a new macro to get PORT_TX register for any given DW. This removes the need of defining register address for each port & DW. Changes since V1: - Use underscope prefix, as macro isn't returning an mmio reg(Lucas) - Merge patch 1 & 2 of the series Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 135 ++++++++++++---------------------------- 1 file changed, 39 insertions(+), 96 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e6a8c0ee7df1..98268163cb83 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1964,30 +1964,36 @@ enum i915_power_well_id { _CNL_PORT_PCS_DW1_LN0_F) #define COMMON_KEEPER_EN (1 << 26) -#define _CNL_PORT_TX_DW2_GRP_AE 0x162348 -#define _CNL_PORT_TX_DW2_GRP_B 0x1623C8 -#define _CNL_PORT_TX_DW2_GRP_C 0x162B48 -#define _CNL_PORT_TX_DW2_GRP_D 0x162BC8 -#define _CNL_PORT_TX_DW2_GRP_F 0x162A48 -#define _CNL_PORT_TX_DW2_LN0_AE 0x162448 -#define _CNL_PORT_TX_DW2_LN0_B 0x162648 -#define _CNL_PORT_TX_DW2_LN0_C 0x162C48 -#define _CNL_PORT_TX_DW2_LN0_D 0x162E48 -#define _CNL_PORT_TX_DW2_LN0_F 0x162848 -#define CNL_PORT_TX_DW2_GRP(port) _MMIO_PORT6(port, \ - _CNL_PORT_TX_DW2_GRP_AE, \ - _CNL_PORT_TX_DW2_GRP_B, \ - _CNL_PORT_TX_DW2_GRP_C, \ - _CNL_PORT_TX_DW2_GRP_D, \ - _CNL_PORT_TX_DW2_GRP_AE, \ - _CNL_PORT_TX_DW2_GRP_F) -#define CNL_PORT_TX_DW2_LN0(port) _MMIO_PORT6(port, \ - _CNL_PORT_TX_DW2_LN0_AE, \ - _CNL_PORT_TX_DW2_LN0_B, \ - _CNL_PORT_TX_DW2_LN0_C, \ - _CNL_PORT_TX_DW2_LN0_D, \ - _CNL_PORT_TX_DW2_LN0_AE, \ - _CNL_PORT_TX_DW2_LN0_F) +/* CNL Port TX registers */ +#define _CNL_PORT_TX_AE_GRP_OFFSET 0x162340 +#define _CNL_PORT_TX_B_GRP_OFFSET 0x1623C0 +#define _CNL_PORT_TX_C_GRP_OFFSET 0x162B40 +#define _CNL_PORT_TX_D_GRP_OFFSET 0x162BC0 +#define _CNL_PORT_TX_F_GRP_OFFSET 0x162A40 +#define _CNL_PORT_TX_AE_LN0_OFFSET 0x162440 +#define _CNL_PORT_TX_B_LN0_OFFSET 0x162640 +#define _CNL_PORT_TX_C_LN0_OFFSET 0x162C40 +#define _CNL_PORT_TX_D_LN0_OFFSET 0x162E40 +#define _CNL_PORT_TX_F_LN0_OFFSET 0x162840 +#define _CNL_PORT_TX_DW_GRP(port, dw) (_PICK((port), \ + _CNL_PORT_TX_AE_GRP_OFFSET, \ + _CNL_PORT_TX_B_GRP_OFFSET, \ + _CNL_PORT_TX_B_GRP_OFFSET, \ + _CNL_PORT_TX_D_GRP_OFFSET, \ + _CNL_PORT_TX_AE_GRP_OFFSET, \ + _CNL_PORT_TX_F_GRP_OFFSET) + \ + 4*(dw)) +#define _CNL_PORT_TX_DW_LN0(port, dw) (_PICK((port), \ + _CNL_PORT_TX_AE_LN0_OFFSET, \ + _CNL_PORT_TX_B_LN0_OFFSET, \ + _CNL_PORT_TX_B_LN0_OFFSET, \ + _CNL_PORT_TX_D_LN0_OFFSET, \ + _CNL_PORT_TX_AE_LN0_OFFSET, \ + _CNL_PORT_TX_F_LN0_OFFSET) + \ + 4*(dw)) + +#define CNL_PORT_TX_DW2_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 2)) +#define CNL_PORT_TX_DW2_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 2)) #define SWING_SEL_UPPER(x) ((x >> 3) << 15) #define SWING_SEL_UPPER_MASK (1 << 15) #define SWING_SEL_LOWER(x) ((x & 0x7) << 11) @@ -1995,32 +2001,13 @@ enum i915_power_well_id { #define RCOMP_SCALAR(x) ((x) << 0) #define RCOMP_SCALAR_MASK (0xFF << 0) -#define _CNL_PORT_TX_DW4_GRP_AE 0x162350 -#define _CNL_PORT_TX_DW4_GRP_B 0x1623D0 -#define _CNL_PORT_TX_DW4_GRP_C 0x162B50 -#define _CNL_PORT_TX_DW4_GRP_D 0x162BD0 -#define _CNL_PORT_TX_DW4_GRP_F 0x162A50 #define _CNL_PORT_TX_DW4_LN0_AE 0x162450 #define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0 -#define _CNL_PORT_TX_DW4_LN0_B 0x162650 -#define _CNL_PORT_TX_DW4_LN0_C 0x162C50 -#define _CNL_PORT_TX_DW4_LN0_D 0x162E50 -#define _CNL_PORT_TX_DW4_LN0_F 0x162850 -#define CNL_PORT_TX_DW4_GRP(port) _MMIO_PORT6(port, \ - _CNL_PORT_TX_DW4_GRP_AE, \ - _CNL_PORT_TX_DW4_GRP_B, \ - _CNL_PORT_TX_DW4_GRP_C, \ - _CNL_PORT_TX_DW4_GRP_D, \ - _CNL_PORT_TX_DW4_GRP_AE, \ - _CNL_PORT_TX_DW4_GRP_F) -#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO_PORT6_LN(port, ln, \ - _CNL_PORT_TX_DW4_LN0_AE, \ - _CNL_PORT_TX_DW4_LN1_AE, \ - _CNL_PORT_TX_DW4_LN0_B, \ - _CNL_PORT_TX_DW4_LN0_C, \ - _CNL_PORT_TX_DW4_LN0_D, \ - _CNL_PORT_TX_DW4_LN0_AE, \ - _CNL_PORT_TX_DW4_LN0_F) +#define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 4)) +#define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4)) +#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO(_CNL_PORT_TX_DW_LN0((port), 4) + \ + (ln * (_CNL_PORT_TX_DW4_LN1_AE - \ + _CNL_PORT_TX_DW4_LN0_AE))) #define LOADGEN_SELECT (1 << 31) #define POST_CURSOR_1(x) ((x) << 12) #define POST_CURSOR_1_MASK (0x3F << 12) @@ -2029,30 +2016,8 @@ enum i915_power_well_id { #define CURSOR_COEFF(x) ((x) << 0) #define CURSOR_COEFF_MASK (0x3F << 0) -#define _CNL_PORT_TX_DW5_GRP_AE 0x162354 -#define _CNL_PORT_TX_DW5_GRP_B 0x1623D4 -#define _CNL_PORT_TX_DW5_GRP_C 0x162B54 -#define _CNL_PORT_TX_DW5_GRP_D 0x162BD4 -#define _CNL_PORT_TX_DW5_GRP_F 0x162A54 -#define _CNL_PORT_TX_DW5_LN0_AE 0x162454 -#define _CNL_PORT_TX_DW5_LN0_B 0x162654 -#define _CNL_PORT_TX_DW5_LN0_C 0x162C54 -#define _CNL_PORT_TX_DW5_LN0_D 0x162E54 -#define _CNL_PORT_TX_DW5_LN0_F 0x162854 -#define CNL_PORT_TX_DW5_GRP(port) _MMIO_PORT6(port, \ - _CNL_PORT_TX_DW5_GRP_AE, \ - _CNL_PORT_TX_DW5_GRP_B, \ - _CNL_PORT_TX_DW5_GRP_C, \ - _CNL_PORT_TX_DW5_GRP_D, \ - _CNL_PORT_TX_DW5_GRP_AE, \ - _CNL_PORT_TX_DW5_GRP_F) -#define CNL_PORT_TX_DW5_LN0(port) _MMIO_PORT6(port, \ - _CNL_PORT_TX_DW5_LN0_AE, \ - _CNL_PORT_TX_DW5_LN0_B, \ - _CNL_PORT_TX_DW5_LN0_C, \ - _CNL_PORT_TX_DW5_LN0_D, \ - _CNL_PORT_TX_DW5_LN0_AE, \ - _CNL_PORT_TX_DW5_LN0_F) +#define CNL_PORT_TX_DW5_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 5)) +#define CNL_PORT_TX_DW5_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 5)) #define TX_TRAINING_EN (1 << 31) #define TAP3_DISABLE (1 << 29) #define SCALING_MODE_SEL(x) ((x) << 18) @@ -2060,30 +2025,8 @@ enum i915_power_well_id { #define RTERM_SELECT(x) ((x) << 3) #define RTERM_SELECT_MASK (0x7 << 3) -#define _CNL_PORT_TX_DW7_GRP_AE 0x16235C -#define _CNL_PORT_TX_DW7_GRP_B 0x1623DC -#define _CNL_PORT_TX_DW7_GRP_C 0x162B5C -#define _CNL_PORT_TX_DW7_GRP_D 0x162BDC -#define _CNL_PORT_TX_DW7_GRP_F 0x162A5C -#define _CNL_PORT_TX_DW7_LN0_AE 0x16245C -#define _CNL_PORT_TX_DW7_LN0_B 0x16265C -#define _CNL_PORT_TX_DW7_LN0_C 0x162C5C -#define _CNL_PORT_TX_DW7_LN0_D 0x162E5C -#define _CNL_PORT_TX_DW7_LN0_F 0x16285C -#define CNL_PORT_TX_DW7_GRP(port) _MMIO_PORT6(port, \ - _CNL_PORT_TX_DW7_GRP_AE, \ - _CNL_PORT_TX_DW7_GRP_B, \ - _CNL_PORT_TX_DW7_GRP_C, \ - _CNL_PORT_TX_DW7_GRP_D, \ - _CNL_PORT_TX_DW7_GRP_AE, \ - _CNL_PORT_TX_DW7_GRP_F) -#define CNL_PORT_TX_DW7_LN0(port) _MMIO_PORT6(port, \ - _CNL_PORT_TX_DW7_LN0_AE, \ - _CNL_PORT_TX_DW7_LN0_B, \ - _CNL_PORT_TX_DW7_LN0_C, \ - _CNL_PORT_TX_DW7_LN0_D, \ - _CNL_PORT_TX_DW7_LN0_AE, \ - _CNL_PORT_TX_DW7_LN0_F) +#define CNL_PORT_TX_DW7_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP((port), 7)) +#define CNL_PORT_TX_DW7_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0((port), 7)) #define N_SCALAR(x) ((x) << 24) #define N_SCALAR_MASK (0x7F << 24) -- 2.14.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3 2/2] drm/i915/cnl: Kill _MMIO_PORT6 macro 2018-03-13 4:16 [PATCH v3 0/2] CNL port refactoring Mahesh Kumar 2018-03-13 4:16 ` [PATCH v3 1/2] drm/i915/cnl; Add macro to get PORT_TX register Mahesh Kumar @ 2018-03-13 4:16 ` Mahesh Kumar 2018-03-13 20:44 ` Rodrigo Vivi 2018-03-13 5:05 ` ✓ Fi.CI.BAT: success for CNL port refactoring (rev3) Patchwork 2018-03-13 8:37 ` ✗ Fi.CI.IGT: warning " Patchwork 3 siblings, 1 reply; 6+ messages in thread From: Mahesh Kumar @ 2018-03-13 4:16 UTC (permalink / raw) To: intel-gfx; +Cc: lucas.demarchi, rodrigo.vivi This patch replaces use of remaining _MMIO_PORT6 macro and removes the macro. Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 98268163cb83..9d5afcffe641 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -153,9 +153,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) #define _PLL(pll, a, b) ((a) + (pll)*((b)-(a))) #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) -#define _MMIO_PORT6(port, a, b, c, d, e, f) _MMIO(_PICK(port, a, b, c, d, e, f)) -#define _MMIO_PORT6_LN(port, ln, a0, a1, b, c, d, e, f) \ - _MMIO(_PICK(port, a0, b, c, d, e, f) + (ln * (a1 - a0))) #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__) #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) @@ -1948,20 +1945,21 @@ enum i915_power_well_id { #define _CNL_PORT_PCS_DW1_LN0_C 0x162C04 #define _CNL_PORT_PCS_DW1_LN0_D 0x162E04 #define _CNL_PORT_PCS_DW1_LN0_F 0x162804 -#define CNL_PORT_PCS_DW1_GRP(port) _MMIO_PORT6(port, \ +#define CNL_PORT_PCS_DW1_GRP(port) _MMIO(_PICK(port, \ _CNL_PORT_PCS_DW1_GRP_AE, \ _CNL_PORT_PCS_DW1_GRP_B, \ _CNL_PORT_PCS_DW1_GRP_C, \ _CNL_PORT_PCS_DW1_GRP_D, \ _CNL_PORT_PCS_DW1_GRP_AE, \ - _CNL_PORT_PCS_DW1_GRP_F) -#define CNL_PORT_PCS_DW1_LN0(port) _MMIO_PORT6(port, \ + _CNL_PORT_PCS_DW1_GRP_F)) + +#define CNL_PORT_PCS_DW1_LN0(port) _MMIO(_PICK(port, \ _CNL_PORT_PCS_DW1_LN0_AE, \ _CNL_PORT_PCS_DW1_LN0_B, \ _CNL_PORT_PCS_DW1_LN0_C, \ _CNL_PORT_PCS_DW1_LN0_D, \ _CNL_PORT_PCS_DW1_LN0_AE, \ - _CNL_PORT_PCS_DW1_LN0_F) + _CNL_PORT_PCS_DW1_LN0_F)) #define COMMON_KEEPER_EN (1 << 26) /* CNL Port TX registers */ -- 2.14.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v3 2/2] drm/i915/cnl: Kill _MMIO_PORT6 macro 2018-03-13 4:16 ` [PATCH v3 2/2] drm/i915/cnl: Kill _MMIO_PORT6 macro Mahesh Kumar @ 2018-03-13 20:44 ` Rodrigo Vivi 0 siblings, 0 replies; 6+ messages in thread From: Rodrigo Vivi @ 2018-03-13 20:44 UTC (permalink / raw) To: Mahesh Kumar; +Cc: intel-gfx, lucas.demarchi On Tue, Mar 13, 2018 at 09:46:22AM +0530, Mahesh Kumar wrote: > This patch replaces use of remaining _MMIO_PORT6 macro and removes the > macro. > > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Sorry, but I noticed one more thing here :( > --- > drivers/gpu/drm/i915/i915_reg.h | 12 +++++------- > 1 file changed, 5 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 98268163cb83..9d5afcffe641 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -153,9 +153,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) > #define _PLL(pll, a, b) ((a) + (pll)*((b)-(a))) > #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) > -#define _MMIO_PORT6(port, a, b, c, d, e, f) _MMIO(_PICK(port, a, b, c, d, e, f)) > -#define _MMIO_PORT6_LN(port, ln, a0, a1, b, c, d, e, f) \ > - _MMIO(_PICK(port, a0, b, c, d, e, f) + (ln * (a1 - a0))) I had to go back and forth here so I noticed this removal of LN belongs to the first patch. With this moved: Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> for both patches. > #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__) > #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c)) > > @@ -1948,20 +1945,21 @@ enum i915_power_well_id { > #define _CNL_PORT_PCS_DW1_LN0_C 0x162C04 > #define _CNL_PORT_PCS_DW1_LN0_D 0x162E04 > #define _CNL_PORT_PCS_DW1_LN0_F 0x162804 > -#define CNL_PORT_PCS_DW1_GRP(port) _MMIO_PORT6(port, \ > +#define CNL_PORT_PCS_DW1_GRP(port) _MMIO(_PICK(port, \ > _CNL_PORT_PCS_DW1_GRP_AE, \ > _CNL_PORT_PCS_DW1_GRP_B, \ > _CNL_PORT_PCS_DW1_GRP_C, \ > _CNL_PORT_PCS_DW1_GRP_D, \ > _CNL_PORT_PCS_DW1_GRP_AE, \ > - _CNL_PORT_PCS_DW1_GRP_F) > -#define CNL_PORT_PCS_DW1_LN0(port) _MMIO_PORT6(port, \ > + _CNL_PORT_PCS_DW1_GRP_F)) > + > +#define CNL_PORT_PCS_DW1_LN0(port) _MMIO(_PICK(port, \ > _CNL_PORT_PCS_DW1_LN0_AE, \ > _CNL_PORT_PCS_DW1_LN0_B, \ > _CNL_PORT_PCS_DW1_LN0_C, \ > _CNL_PORT_PCS_DW1_LN0_D, \ > _CNL_PORT_PCS_DW1_LN0_AE, \ > - _CNL_PORT_PCS_DW1_LN0_F) > + _CNL_PORT_PCS_DW1_LN0_F)) > #define COMMON_KEEPER_EN (1 << 26) > > /* CNL Port TX registers */ > -- > 2.14.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* ✓ Fi.CI.BAT: success for CNL port refactoring (rev3) 2018-03-13 4:16 [PATCH v3 0/2] CNL port refactoring Mahesh Kumar 2018-03-13 4:16 ` [PATCH v3 1/2] drm/i915/cnl; Add macro to get PORT_TX register Mahesh Kumar 2018-03-13 4:16 ` [PATCH v3 2/2] drm/i915/cnl: Kill _MMIO_PORT6 macro Mahesh Kumar @ 2018-03-13 5:05 ` Patchwork 2018-03-13 8:37 ` ✗ Fi.CI.IGT: warning " Patchwork 3 siblings, 0 replies; 6+ messages in thread From: Patchwork @ 2018-03-13 5:05 UTC (permalink / raw) To: Mahesh Kumar; +Cc: intel-gfx == Series Details == Series: CNL port refactoring (rev3) URL : https://patchwork.freedesktop.org/series/38334/ State : success == Summary == Series 38334v3 CNL port refactoring https://patchwork.freedesktop.org/api/1.0/series/38334/revisions/3/mbox/ ---- Known issues: Test kms_pipe_crc_basic: Subgroup suspend-read-crc-pipe-b: incomplete -> PASS (fi-snb-2520m) fdo#103713 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fi-bdw-5557u total:288 pass:267 dwarn:0 dfail:0 fail:0 skip:21 time:430s fi-blb-e6850 total:288 pass:223 dwarn:1 dfail:0 fail:0 skip:64 time:381s fi-bsw-n3050 total:288 pass:242 dwarn:0 dfail:0 fail:0 skip:46 time:535s fi-bwr-2160 total:288 pass:183 dwarn:0 dfail:0 fail:0 skip:105 time:298s fi-bxt-dsi total:288 pass:258 dwarn:0 dfail:0 fail:0 skip:30 time:511s fi-bxt-j4205 total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:505s fi-byt-j1900 total:288 pass:253 dwarn:0 dfail:0 fail:0 skip:35 time:508s fi-byt-n2820 total:288 pass:249 dwarn:0 dfail:0 fail:0 skip:39 time:494s fi-cfl-8700k total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:411s fi-cfl-s2 total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:591s fi-elk-e7500 total:288 pass:229 dwarn:0 dfail:0 fail:0 skip:59 time:428s fi-gdg-551 total:288 pass:179 dwarn:0 dfail:0 fail:1 skip:108 time:315s fi-glk-1 total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:535s fi-hsw-4770 total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:402s fi-ilk-650 total:288 pass:228 dwarn:0 dfail:0 fail:0 skip:60 time:421s fi-ivb-3520m total:288 pass:259 dwarn:0 dfail:0 fail:0 skip:29 time:472s fi-ivb-3770 total:288 pass:255 dwarn:0 dfail:0 fail:0 skip:33 time:435s fi-kbl-7500u total:288 pass:263 dwarn:1 dfail:0 fail:0 skip:24 time:471s fi-kbl-7567u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:467s fi-kbl-r total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:514s fi-pnv-d510 total:288 pass:222 dwarn:1 dfail:0 fail:0 skip:65 time:643s fi-skl-6260u total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:440s fi-skl-6600u total:288 pass:261 dwarn:0 dfail:0 fail:0 skip:27 time:531s fi-skl-6700hq total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:537s fi-skl-6700k2 total:288 pass:264 dwarn:0 dfail:0 fail:0 skip:24 time:509s fi-skl-6770hq total:288 pass:268 dwarn:0 dfail:0 fail:0 skip:20 time:489s fi-skl-guc total:288 pass:260 dwarn:0 dfail:0 fail:0 skip:28 time:426s fi-snb-2520m total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:535s fi-snb-2600 total:288 pass:248 dwarn:0 dfail:0 fail:0 skip:40 time:400s Blacklisted hosts: fi-cfl-u total:288 pass:262 dwarn:0 dfail:0 fail:0 skip:26 time:513s fi-cnl-drrs total:288 pass:257 dwarn:3 dfail:0 fail:0 skip:28 time:524s da600bbe24412edd1c46591fd21ef81518e49c5d drm-tip: 2018y-03m-12d-22h-06m-53s UTC integration manifest 46bdab3e5d91 drm/i915/cnl: Kill _MMIO_PORT6 macro fa76e6ba6304 drm/i915/cnl; Add macro to get PORT_TX register == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8321/issues.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
* ✗ Fi.CI.IGT: warning for CNL port refactoring (rev3) 2018-03-13 4:16 [PATCH v3 0/2] CNL port refactoring Mahesh Kumar ` (2 preceding siblings ...) 2018-03-13 5:05 ` ✓ Fi.CI.BAT: success for CNL port refactoring (rev3) Patchwork @ 2018-03-13 8:37 ` Patchwork 3 siblings, 0 replies; 6+ messages in thread From: Patchwork @ 2018-03-13 8:37 UTC (permalink / raw) To: Mahesh Kumar; +Cc: intel-gfx == Series Details == Series: CNL port refactoring (rev3) URL : https://patchwork.freedesktop.org/series/38334/ State : warning == Summary == ---- Possible new issues: Test drv_suspend: Subgroup forcewake: pass -> SKIP (shard-snb) ---- Known issues: Test gem_eio: Subgroup in-flight-contexts: incomplete -> PASS (shard-apl) fdo#105341 Test kms_atomic_transition: Subgroup 1x-modeset-transitions-nonblocking-fencing: fail -> PASS (shard-apl) fdo#103207 Test kms_flip: Subgroup 2x-plain-flip-ts-check: pass -> FAIL (shard-hsw) fdo#100368 Test kms_sysfs_edid_timing: warn -> PASS (shard-apl) fdo#100047 Test testdisplay: pass -> DMESG-WARN (shard-apl) fdo#104727 fdo#105341 https://bugs.freedesktop.org/show_bug.cgi?id=105341 fdo#103207 https://bugs.freedesktop.org/show_bug.cgi?id=103207 fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#100047 https://bugs.freedesktop.org/show_bug.cgi?id=100047 fdo#104727 https://bugs.freedesktop.org/show_bug.cgi?id=104727 shard-apl total:3473 pass:1830 dwarn:2 dfail:0 fail:7 skip:1634 time:13179s shard-hsw total:3473 pass:1776 dwarn:1 dfail:0 fail:3 skip:1692 time:11909s shard-snb total:3473 pass:1363 dwarn:1 dfail:0 fail:3 skip:2106 time:7154s Blacklisted hosts: shard-kbl total:3393 pass:1918 dwarn:1 dfail:0 fail:9 skip:1464 time:9500s == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8321/shards.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-03-13 20:44 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2018-03-13 4:16 [PATCH v3 0/2] CNL port refactoring Mahesh Kumar 2018-03-13 4:16 ` [PATCH v3 1/2] drm/i915/cnl; Add macro to get PORT_TX register Mahesh Kumar 2018-03-13 4:16 ` [PATCH v3 2/2] drm/i915/cnl: Kill _MMIO_PORT6 macro Mahesh Kumar 2018-03-13 20:44 ` Rodrigo Vivi 2018-03-13 5:05 ` ✓ Fi.CI.BAT: success for CNL port refactoring (rev3) Patchwork 2018-03-13 8:37 ` ✗ Fi.CI.IGT: warning " Patchwork
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