From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: "José Roberto de Souza" <jose.souza@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 07/12] drm/i915/psr: Use PSR2 macro for PSR2
Date: Thu, 22 Mar 2018 16:12:08 -0700 [thread overview]
Message-ID: <20180322231208.GL2557@intel.com> (raw)
In-Reply-To: <20180322214848.28022-7-jose.souza@intel.com>
On Thu, Mar 22, 2018 at 02:48:43PM -0700, José Roberto de Souza wrote:
> Cosmetic change.
>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 ++-
> drivers/gpu/drm/i915/intel_psr.c | 2 +-
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9c4be6bcd1ef..e660c8a707cf 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3903,8 +3903,9 @@ enum {
> #define EDP_PSR2_TP2_TIME_MASK (3<<8)
> #define EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
> #define EDP_PSR2_FRAME_BEFORE_SU_MASK (0xf<<4)
> -#define EDP_PSR2_IDLE_MASK 0xf
> #define EDP_PSR2_FRAME_BEFORE_SU(a) ((a)<<4)
> +#define EDP_PSR2_IDLE_FRAME_MASK 0xf
> +#define EDP_PSR2_IDLE_FRAME_SHIFT 0
>
> #define EDP_PSR2_STATUS _MMIO(0x6f940)
> #define EDP_PSR2_STATUS_STATE_MASK (0xf<<28)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index f73e2734a859..ad69722c329d 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -331,7 +331,7 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
> uint32_t val = EDP_PSR_ENABLE;
>
> val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
> - val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
> + val |= idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
>
> if (IS_HASWELL(dev_priv))
> val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
> --
> 2.16.2
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2018-03-22 23:12 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-22 21:48 [PATCH 01/12] drm: Add DP PSR2 sink enable bit José Roberto de Souza
2018-03-22 21:48 ` [PATCH 02/12] drm: Add DP last received PSR SDP VSC register and bits José Roberto de Souza
2018-03-22 23:23 ` Rodrigo Vivi
2018-03-23 0:59 ` Souza, Jose
2018-03-23 5:40 ` Rodrigo Vivi
2018-03-22 21:48 ` [PATCH 03/12] drm/i915/psr: Nuke aux frame sync José Roberto de Souza
2018-03-22 22:57 ` Rodrigo Vivi
2018-03-23 0:53 ` Souza, Jose
2018-03-23 22:14 ` Pandiyan, Dhinakaran
2018-03-23 23:49 ` Souza, Jose
2018-03-24 2:16 ` Pandiyan, Dhinakaran
2018-03-27 0:11 ` Souza, Jose
2018-03-22 21:48 ` [PATCH 04/12] drm/i915/psr: Tie PSR2 support to Y coordinate requirement José Roberto de Souza
2018-03-22 23:09 ` Rodrigo Vivi
2018-03-22 23:16 ` Souza, Jose
2018-03-23 22:59 ` Pandiyan, Dhinakaran
2018-03-23 23:51 ` Souza, Jose
2018-03-24 2:34 ` Pandiyan, Dhinakaran
2018-03-27 21:36 ` Rodrigo Vivi
2018-03-28 3:35 ` Nagaraju, Vathsala
2018-03-22 21:48 ` [PATCH 05/12] drm/i915/psr/cnl: Enable Y-coordinate support in source José Roberto de Souza
2018-03-22 21:48 ` [PATCH 06/12] drm/i915/psr: Do not override PSR2 sink support José Roberto de Souza
2018-03-22 21:48 ` [PATCH 07/12] drm/i915/psr: Use PSR2 macro for PSR2 José Roberto de Souza
2018-03-22 23:12 ` Rodrigo Vivi [this message]
2018-03-22 21:48 ` [PATCH 08/12] drm/i915/psr: Cache sink synchronization latency José Roberto de Souza
2018-03-22 23:15 ` Rodrigo Vivi
2018-03-23 0:21 ` Souza, Jose
2018-03-22 21:48 ` [PATCH 09/12] drm/i915/psr: Set DPCD PSR2 enable bit when needed José Roberto de Souza
2018-03-22 23:20 ` Rodrigo Vivi
2018-03-22 21:48 ` [PATCH 10/12] drm/i915/debugfs: Print sink PSR state and debug info José Roberto de Souza
2018-03-22 23:31 ` Rodrigo Vivi
2018-03-23 0:06 ` Souza, Jose
2018-03-23 0:11 ` Rodrigo Vivi
2018-03-24 3:23 ` Pandiyan, Dhinakaran
2018-03-22 21:48 ` [PATCH 11/12] drm/i915/debugfs: Print information about what caused a PSR exit José Roberto de Souza
2018-03-22 23:27 ` Rodrigo Vivi
2018-03-22 23:43 ` Pandiyan, Dhinakaran
2018-03-23 0:16 ` Souza, Jose
2018-03-23 0:22 ` Pandiyan, Dhinakaran
2018-03-22 21:48 ` [PATCH 12/12] drm/i915/debugfs: Print how many blocks were sent in a selective update José Roberto de Souza
2018-03-22 23:46 ` Rodrigo Vivi
2018-03-23 0:52 ` Souza, Jose
2018-03-22 21:56 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/12] drm: Add DP PSR2 sink enable bit Patchwork
2018-03-22 22:14 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-03-22 23:19 ` [PATCH 01/12] " Rodrigo Vivi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20180322231208.GL2557@intel.com \
--to=rodrigo.vivi@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=jose.souza@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox