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From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: "Souza, Jose" <jose.souza@intel.com>
Cc: "intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"Pandiyan, Dhinakaran" <dhinakaran.pandiyan@intel.com>
Subject: Re: [PATCH 10/12] drm/i915/debugfs: Print sink PSR state and debug info
Date: Thu, 22 Mar 2018 17:11:06 -0700	[thread overview]
Message-ID: <20180323001106.GV2557@intel.com> (raw)
In-Reply-To: <1521763386.10092.10.camel@intel.com>

On Thu, Mar 22, 2018 at 05:06:13PM -0700, Souza, Jose wrote:
> On Thu, 2018-03-22 at 16:31 -0700, Rodrigo Vivi wrote:
> > On Thu, Mar 22, 2018 at 02:48:46PM -0700, José Roberto de Souza
> > wrote:
> > 
> > please add some justification on why this is useful....
> 
> Okay something like this should be fine?
> 
> IGT tests could be improved with sink status, knowing for sure that
> hardware have activate PSR before get the CRC.
> This is also userful to check if hardware is really doing PSR2
> selective update with the y-coordinate.

I think so. Although for the tests I'd like you sync with DK on this
versus the Interrupt approach.

> 
> 
> > 
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_debugfs.c | 54
> > > +++++++++++++++++++++++++++++++++++++
> > >  1 file changed, 54 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> > > b/drivers/gpu/drm/i915/i915_debugfs.c
> > > index 16f9977995df..0a0642c61cd0 100644
> > > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > > @@ -2603,6 +2603,44 @@ static const char *psr2_live_status(u32 val)
> > >  	return "unknown";
> > >  }
> > >  
> > > +static const char *psr_sink_self_refresh_status(u8 val)
> > > +{
> > > +	static const char * const sink_status[] = {
> > > +		"inactive",
> > > +		"transitioning to active",
> > > +		"active",
> > > +		"active receiving selective update",
> > > +		"transitioning to inactive",
> > > +		"reserved",
> > > +		"reserved",
> > > +		"sink internal error"
> > > +	};
> > > +
> > > +	val &= DP_PSR_SINK_STATE_MASK;
> > > +	if (val < ARRAY_SIZE(sink_status))
> > > +		return sink_status[val];
> > > +
> > > +	return "unknown";
> > > +}
> > > +
> > > +static void psr_sink_last_received_psr_sdp_sprintf(struct seq_file
> > > *m, u32 val)
> > > +{
> > > +	if (val & DP_PSR_STATE_BIT)
> > > +		seq_puts(m, "\tPSR active\n");
> > 
> > I'm a bit confused here why we are printing status here again if we
> > are adding the
> > sink_status char * array with some status definition up there.
> > 
> > Any simplification possible?
> 
> Huum yeah, DP_PSR_STATE_BIT and DP_SU_VALID changes will cause the
> status of the sink to change, so I this 2 can be removed.
> 
> > 
> > > +	if (val & DP_UPDATE_RFB_BIT)
> > > +		seq_puts(m, "\tUpdate RFB\n");
> > > +	if (val & DP_CRC_VALID_BIT)
> > > +		seq_puts(m, "\tCRC valid\n");
> > > +	if (val & DP_SU_VALID)
> > > +		seq_puts(m, "\tSU valid\n");
> > > +	if (val & DP_FIRST_SCAN_LINE_SU_REGION)
> > > +		seq_puts(m, "\tFirst scan line of the SU
> > > region\n");
> > > +	if (val & DP_LAST_SCAN_LINE_SU_REGION)
> > > +		seq_puts(m, "\tLast scan line of the SU
> > > region\n");
> > > +	if (val & DP_Y_COORDINATE_VALID)
> > > +		seq_puts(m, "\tY-Coordinate valid\n");
> > > +}
> > > +
> > >  static int i915_edp_psr_status(struct seq_file *m, void *data)
> > >  {
> > >  	struct drm_i915_private *dev_priv = node_to_i915(m-
> > > >private);
> > > @@ -2684,6 +2722,22 @@ static int i915_edp_psr_status(struct
> > > seq_file *m, void *data)
> > >  		seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
> > >  			   psr2, psr2_live_status(psr2));
> > >  	}
> > > +
> > > +	if (dev_priv->psr.enabled) {
> > > +		struct drm_dp_aux *aux = &dev_priv->psr.enabled-
> > > >aux;
> > > +		u8 val;
> > > +
> > > +		if (drm_dp_dpcd_readb(aux, DP_PSR_STATUS, &val) ==
> > > 1)
> > > +			seq_printf(m, "Sink self refresh status:
> > > 0x%x [%s]\n",
> > > +				   val,
> > > psr_sink_self_refresh_status(val));
> > > +
> > > +		if (drm_dp_dpcd_readb(aux,
> > > DP_LAST_RECEIVED_PSR_SDP, &val)
> > > +		    == 1) {
> > > +			seq_printf(m, "Sink last received PSR SDP:
> > > 0x%x\n",
> > > +				   val);
> > > +			psr_sink_last_received_psr_sdp_sprintf(m,
> > > val);
> > > +		}
> > > +	}
> > >  	mutex_unlock(&dev_priv->psr.lock);
> > >  
> > >  	intel_runtime_pm_put(dev_priv);
> > > -- 
> > > 2.16.2
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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  reply	other threads:[~2018-03-23  0:11 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-22 21:48 [PATCH 01/12] drm: Add DP PSR2 sink enable bit José Roberto de Souza
2018-03-22 21:48 ` [PATCH 02/12] drm: Add DP last received PSR SDP VSC register and bits José Roberto de Souza
2018-03-22 23:23   ` Rodrigo Vivi
2018-03-23  0:59     ` Souza, Jose
2018-03-23  5:40       ` Rodrigo Vivi
2018-03-22 21:48 ` [PATCH 03/12] drm/i915/psr: Nuke aux frame sync José Roberto de Souza
2018-03-22 22:57   ` Rodrigo Vivi
2018-03-23  0:53     ` Souza, Jose
2018-03-23 22:14     ` Pandiyan, Dhinakaran
2018-03-23 23:49       ` Souza, Jose
2018-03-24  2:16         ` Pandiyan, Dhinakaran
2018-03-27  0:11           ` Souza, Jose
2018-03-22 21:48 ` [PATCH 04/12] drm/i915/psr: Tie PSR2 support to Y coordinate requirement José Roberto de Souza
2018-03-22 23:09   ` Rodrigo Vivi
2018-03-22 23:16     ` Souza, Jose
2018-03-23 22:59   ` Pandiyan, Dhinakaran
2018-03-23 23:51     ` Souza, Jose
2018-03-24  2:34       ` Pandiyan, Dhinakaran
2018-03-27 21:36         ` Rodrigo Vivi
2018-03-28  3:35           ` Nagaraju, Vathsala
2018-03-22 21:48 ` [PATCH 05/12] drm/i915/psr/cnl: Enable Y-coordinate support in source José Roberto de Souza
2018-03-22 21:48 ` [PATCH 06/12] drm/i915/psr: Do not override PSR2 sink support José Roberto de Souza
2018-03-22 21:48 ` [PATCH 07/12] drm/i915/psr: Use PSR2 macro for PSR2 José Roberto de Souza
2018-03-22 23:12   ` Rodrigo Vivi
2018-03-22 21:48 ` [PATCH 08/12] drm/i915/psr: Cache sink synchronization latency José Roberto de Souza
2018-03-22 23:15   ` Rodrigo Vivi
2018-03-23  0:21     ` Souza, Jose
2018-03-22 21:48 ` [PATCH 09/12] drm/i915/psr: Set DPCD PSR2 enable bit when needed José Roberto de Souza
2018-03-22 23:20   ` Rodrigo Vivi
2018-03-22 21:48 ` [PATCH 10/12] drm/i915/debugfs: Print sink PSR state and debug info José Roberto de Souza
2018-03-22 23:31   ` Rodrigo Vivi
2018-03-23  0:06     ` Souza, Jose
2018-03-23  0:11       ` Rodrigo Vivi [this message]
2018-03-24  3:23       ` Pandiyan, Dhinakaran
2018-03-22 21:48 ` [PATCH 11/12] drm/i915/debugfs: Print information about what caused a PSR exit José Roberto de Souza
2018-03-22 23:27   ` Rodrigo Vivi
2018-03-22 23:43     ` Pandiyan, Dhinakaran
2018-03-23  0:16       ` Souza, Jose
2018-03-23  0:22         ` Pandiyan, Dhinakaran
2018-03-22 21:48 ` [PATCH 12/12] drm/i915/debugfs: Print how many blocks were sent in a selective update José Roberto de Souza
2018-03-22 23:46   ` Rodrigo Vivi
2018-03-23  0:52     ` Souza, Jose
2018-03-22 21:56 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/12] drm: Add DP PSR2 sink enable bit Patchwork
2018-03-22 22:14 ` ✗ Fi.CI.BAT: failure " Patchwork
2018-03-22 23:19 ` [PATCH 01/12] " Rodrigo Vivi

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