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From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>,
	Gaurav K Singh <gaurav.k.singh@intel.com>
Subject: Re: [PATCH v5 18/28] drm/i915/dp: Enable/Disable DSC in DP Sink
Date: Mon, 22 Oct 2018 11:50:16 -0700	[thread overview]
Message-ID: <20181022185016.GB17333@intel.com> (raw)
In-Reply-To: <20181005232306.31133-19-manasi.d.navare@intel.com>

On Fri, Oct 05, 2018 at 04:22:56PM -0700, Manasi Navare wrote:
> From: Gaurav K Singh <gaurav.k.singh@intel.com>
> 
> This patch enables decompression support in sink device
> before link training and disables the same during the
> DDI disabling.
> 
> v2:(From Manasi)
> * Change the enable/disable function to take crtc_state
> instead of intel_dp as an argument (Manasi)
> * Use the compression_enable flag as part of crtc_state (Manasi)
> 
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Gaurav K Singh <gaurav.k.singh@intel.com>
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c |  5 +++++
>  drivers/gpu/drm/i915/intel_dp.c  | 15 +++++++++++++++
>  drivers/gpu/drm/i915/intel_drv.h |  3 +++
>  3 files changed, 23 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index b6594948b617..0c0461cc664c 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2906,6 +2906,8 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
>  	intel_ddi_init_dp_buf_reg(encoder);
>  	if (!is_mst)
>  		intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
> +	intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
> +					      DP_DECOMPRESSION_EN);
>  	intel_dp_start_link_train(intel_dp);
>  	if (port != PORT_A || INTEL_GEN(dev_priv) >= 9)
>  		intel_dp_stop_link_train(intel_dp);
> @@ -3236,6 +3238,9 @@ static void intel_disable_ddi_dp(struct intel_encoder *encoder,
>  	intel_edp_drrs_disable(intel_dp, old_crtc_state);
>  	intel_psr_disable(intel_dp, old_crtc_state);
>  	intel_edp_backlight_off(old_conn_state);
> +	/* Disable the decompression in DP Sink */
> +	intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
> +					      ~DP_DECOMPRESSION_EN);
>  }
>  
>  static void intel_disable_ddi_hdmi(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 89990a96263b..9a4012f3f1da 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2970,6 +2970,21 @@ static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
>  		intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
>  }
>  
> +void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
> +					   const struct intel_crtc_state *crtc_state,
> +					   int state)

Jani, Ville,

Should this function also be moved to intel_ddi.c or rather intel_dsc.c since its setting the
dsc state?

Manasi

> +{
> +	int ret;
> +
> +	if (!crtc_state->dsc_params.compression_enable)
> +		return;
> +
> +	ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE, state);
> +	if (ret < 0)
> +		DRM_DEBUG_KMS("Failed to %s sink decompression state\n",
> +			      state == DP_DECOMPRESSION_EN ? "enable" : "disable");
> +}
> +
>  /* If the sink supports it, try to set the power state appropriately */
>  void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
>  {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 36089c77e493..3996df385d33 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1702,6 +1702,9 @@ void intel_dp_stop_link_train(struct intel_dp *intel_dp);
>  int intel_dp_retrain_link(struct intel_encoder *encoder,
>  			  struct drm_modeset_acquire_ctx *ctx);
>  void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
> +void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
> +					   const struct intel_crtc_state *crtc_state,
> +					   int state);
>  void intel_dp_encoder_reset(struct drm_encoder *encoder);
>  void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
>  void intel_dp_encoder_destroy(struct drm_encoder *encoder);
> -- 
> 2.18.0
> 
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  reply	other threads:[~2018-10-22 18:50 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-05 23:22 [PATCH v5 00/28] Display Stream Compression enabling on eDP/DP Manasi Navare
2018-10-05 23:22 ` [PATCH v5 01/28] drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming Manasi Navare
2018-10-05 23:22 ` [PATCH v5 02/28] drm/dp: Add DP DSC DPCD receiver capability size define and missing SHIFT Manasi Navare
2018-10-05 23:22 ` [PATCH v5 03/28] drm/i915/dp: Cache the DP/eDP DSC DPCD register set on Hotplug/eDP Init Manasi Navare
2018-10-05 23:22 ` [PATCH v5 04/28] drm/dp: DRM DP helper/macros to get DP sink DSC parameters Manasi Navare
2018-10-05 23:22 ` [PATCH v5 05/28] drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC Manasi Navare
2018-10-05 23:22 ` [PATCH v5 06/28] drm/i915/dp: Validate modes using max Output BPP and slice count when DSC supported Manasi Navare
2018-10-05 23:22 ` [PATCH v5 07/28] drm/dp: Define payload size for DP SDP PPS packet Manasi Navare
2018-10-05 23:22 ` [PATCH v5 08/28] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare
2018-10-05 23:22 ` [PATCH v5 09/28] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare
2018-10-05 23:22 ` [PATCH v5 10/28] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare
2018-10-05 23:22 ` [PATCH v5 11/28] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare
2018-10-16  1:27   ` Manasi Navare
2018-10-05 23:22 ` [PATCH v5 12/28] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-10-05 23:22 ` [PATCH v5 13/28] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare
2018-10-16  1:29   ` Manasi Navare
2018-10-22 23:53   ` Srivatsa, Anusha
2018-10-05 23:22 ` [PATCH v5 14/28] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare
2018-10-05 23:22 ` [PATCH v5 15/28] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Manasi Navare
2018-10-22 22:04   ` [Intel-gfx] " Srivatsa, Anusha
2018-10-05 23:22 ` [PATCH v5 16/28] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare
2018-10-16  1:31   ` Manasi Navare
2018-10-22 22:26   ` Srivatsa, Anusha
2018-10-05 23:22 ` [PATCH v5 17/28] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare
2018-10-22 23:34   ` Srivatsa, Anusha
2018-10-23 18:42     ` Manasi Navare
2018-10-23 18:45       ` Srivatsa, Anusha
2018-10-05 23:22 ` [PATCH v5 18/28] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare
2018-10-22 18:50   ` Manasi Navare [this message]
2018-10-05 23:22 ` [PATCH v5 19/28] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI Manasi Navare
2018-10-16  1:22   ` Manasi Navare
2018-10-16 19:01   ` Ville Syrjälä
2018-10-16 19:19     ` Ville Syrjälä
2018-10-16 19:42       ` Manasi Navare
2018-10-16 19:45         ` Ville Syrjälä
2018-10-16 21:04           ` Manasi Navare
2018-10-16 21:21             ` [Intel-gfx] " Manasi Navare
2018-10-16 19:19     ` Manasi Navare
2018-10-16 19:33       ` Ville Syrjälä
2018-10-05 23:22 ` [PATCH v5 20/28] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare
2018-10-16 19:58   ` Srivatsa, Anusha
2018-10-16 21:02     ` Manasi Navare
2018-10-17 16:58       ` Srivatsa, Anusha
2018-10-05 23:22 ` [PATCH v5 21/28] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare
2018-10-05 23:23 ` [PATCH v5 22/28] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare
2018-10-05 23:23 ` [PATCH v5 23/28] drm/i915/icl: Add Display Stream Splitter control registers Manasi Navare
2018-10-05 23:23 ` [PATCH v5 24/28] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare
2018-10-18 17:02   ` Ville Syrjälä
2018-10-19 22:40     ` Manasi Navare
2018-10-05 23:23 ` [PATCH v5 25/28] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare
2018-10-05 23:23 ` [PATCH v5 26/28] drm/i915/dsc: Enable and disable appropriate power wells for VDSC Manasi Navare
2018-10-16  1:23   ` Manasi Navare
2018-10-16 19:31   ` Ville Syrjälä
2018-10-05 23:23 ` [PATCH v5 27/28] drm/i915/dsc: Add Per connector debugfs node for DSC support/enable Manasi Navare
2018-10-05 23:34   ` Lyude Paul
2018-10-09 22:20     ` Manasi Navare
2018-10-09 22:24       ` Lyude Paul
2018-10-05 23:23 ` [PATCH v5 28/28] drm/i915/dsc: Force DSC enable if requested by IGT/userspace Manasi Navare
2018-10-24 17:51   ` Srivatsa, Anusha
2018-10-06  0:21 ` ✗ Fi.CI.CHECKPATCH: warning for Display Stream Compression enabling on eDP/DP (rev5) Patchwork
2018-10-06  0:31 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-10-06  0:45 ` ✗ Fi.CI.BAT: failure " Patchwork

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