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* [PATCH v4 1/2] drm/i915/guc: Limit number of scratch registers used for H2G
@ 2018-10-19 10:17 Michal Wajdeczko
  2018-10-19 10:17 ` [PATCH v4 2/2] HAX: Enable GuC for CI Michal Wajdeczko
  2018-10-22 11:20 ` ✗ Fi.CI.BAT: failure for series starting with [v4,1/2] drm/i915/guc: Limit number of scratch registers used for H2G Patchwork
  0 siblings, 2 replies; 5+ messages in thread
From: Michal Wajdeczko @ 2018-10-19 10:17 UTC (permalink / raw)
  To: intel-gfx

We wrongly assumed that GuC is only using last scratch register
for G2H messages, but in fact it is also using register [14] to
report sleep state status. Remove that register from our H2G
send registers pool.

v2: No message from host to GuC uses more than 8 registers and
the GuC FW itself uses an 8-element array to store the H2G message,
so we may reduce our send array to just 8 registers (Daniele)
v3: use explicit define (Daniele)
v4: and explicit comment (Daniele)

Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
 drivers/gpu/drm/i915/intel_guc.c      | 3 ++-
 drivers/gpu/drm/i915/intel_guc_fwif.h | 6 +++++-
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c
index 4c61eb9..8660af3 100644
--- a/drivers/gpu/drm/i915/intel_guc.c
+++ b/drivers/gpu/drm/i915/intel_guc.c
@@ -50,7 +50,8 @@ void intel_guc_init_send_regs(struct intel_guc *guc)
 	unsigned int i;
 
 	guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
-	guc->send_regs.count = SOFT_SCRATCH_COUNT - 1;
+	guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;
+	BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);
 
 	for (i = 0; i < guc->send_regs.count; i++) {
 		fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index d1bbaba..ef79e0f 100644
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -601,7 +601,9 @@ struct guc_shared_ctx_data {
  * registers, where first register holds data treated as message header,
  * and other registers are used to hold message payload.
  *
- * For Gen9+, GuC uses software scratch registers 0xC180-0xC1B8
+ * For Gen9+, GuC uses software scratch registers 0xC180-0xC1B8,
+ * but no H2G command takes more than 8 parameters and the GuC FW
+ * itself uses an 8-element array to store the H2G message.
  *
  *      +-----------+---------+---------+---------+
  *      |  MMIO[0]  | MMIO[1] |   ...   | MMIO[n] |
@@ -633,6 +635,8 @@ struct guc_shared_ctx_data {
  *   field.
  */
 
+#define GUC_MAX_MMIO_MSG_LEN		8
+
 #define INTEL_GUC_MSG_TYPE_SHIFT	28
 #define INTEL_GUC_MSG_TYPE_MASK		(0xF << INTEL_GUC_MSG_TYPE_SHIFT)
 #define INTEL_GUC_MSG_DATA_SHIFT	16
-- 
1.9.1

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^ permalink raw reply related	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2018-11-05  0:23 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-10-19 10:17 [PATCH v4 1/2] drm/i915/guc: Limit number of scratch registers used for H2G Michal Wajdeczko
2018-10-19 10:17 ` [PATCH v4 2/2] HAX: Enable GuC for CI Michal Wajdeczko
2018-11-05  0:23   ` [LKP] [HAX] ddc7f46e1c: drm:i915_gem_init_hw[i915]] kernel test robot
2018-10-22 11:20 ` ✗ Fi.CI.BAT: failure for series starting with [v4,1/2] drm/i915/guc: Limit number of scratch registers used for H2G Patchwork
2018-10-22 11:37   ` Chris Wilson

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