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From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: "José Roberto de Souza" <jose.souza@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
	Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Subject: Re: [PATCH 2/7] drm/i915: Remove unused VLV/CHV PSR registers
Date: Wed, 3 Apr 2019 17:22:25 -0700	[thread overview]
Message-ID: <20190404002225.GB25758@intel.com> (raw)
In-Reply-To: <20190403233539.31828-2-jose.souza@intel.com>

On Wed, Apr 03, 2019 at 04:35:34PM -0700, José Roberto de Souza wrote:
> PSR support for VLV and CHV was dropped in commit ce3508fd2a77
> ("drm/i915/psr: Nuke PSR support for VLV and CHV") so no need to keep
> this registers around.

o.O


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>



> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 36 ---------------------------------
>  1 file changed, 36 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 00e03560c4e7..c59cfa83dbaf 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4209,42 +4209,6 @@ enum {
>  #define PIPESRC(trans)		_MMIO_TRANS2(trans, _PIPEASRC)
>  #define PIPE_MULT(trans)	_MMIO_TRANS2(trans, _PIPE_MULT_A)
>  
> -/* VLV eDP PSR registers */
> -#define _PSRCTLA				(VLV_DISPLAY_BASE + 0x60090)
> -#define _PSRCTLB				(VLV_DISPLAY_BASE + 0x61090)
> -#define  VLV_EDP_PSR_ENABLE			(1 << 0)
> -#define  VLV_EDP_PSR_RESET			(1 << 1)
> -#define  VLV_EDP_PSR_MODE_MASK			(7 << 2)
> -#define  VLV_EDP_PSR_MODE_HW_TIMER		(1 << 3)
> -#define  VLV_EDP_PSR_MODE_SW_TIMER		(1 << 2)
> -#define  VLV_EDP_PSR_SINGLE_FRAME_UPDATE	(1 << 7)
> -#define  VLV_EDP_PSR_ACTIVE_ENTRY		(1 << 8)
> -#define  VLV_EDP_PSR_SRC_TRANSMITTER_STATE	(1 << 9)
> -#define  VLV_EDP_PSR_DBL_FRAME			(1 << 10)
> -#define  VLV_EDP_PSR_FRAME_COUNT_MASK		(0xff << 16)
> -#define  VLV_EDP_PSR_IDLE_FRAME_SHIFT		16
> -#define VLV_PSRCTL(pipe)	_MMIO_PIPE(pipe, _PSRCTLA, _PSRCTLB)
> -
> -#define _VSCSDPA			(VLV_DISPLAY_BASE + 0x600a0)
> -#define _VSCSDPB			(VLV_DISPLAY_BASE + 0x610a0)
> -#define  VLV_EDP_PSR_SDP_FREQ_MASK	(3 << 30)
> -#define  VLV_EDP_PSR_SDP_FREQ_ONCE	(1 << 31)
> -#define  VLV_EDP_PSR_SDP_FREQ_EVFRAME	(1 << 30)
> -#define VLV_VSCSDP(pipe)	_MMIO_PIPE(pipe, _VSCSDPA, _VSCSDPB)
> -
> -#define _PSRSTATA			(VLV_DISPLAY_BASE + 0x60094)
> -#define _PSRSTATB			(VLV_DISPLAY_BASE + 0x61094)
> -#define  VLV_EDP_PSR_LAST_STATE_MASK	(7 << 3)
> -#define  VLV_EDP_PSR_CURR_STATE_MASK	7
> -#define  VLV_EDP_PSR_DISABLED		(0 << 0)
> -#define  VLV_EDP_PSR_INACTIVE		(1 << 0)
> -#define  VLV_EDP_PSR_IN_TRANS_TO_ACTIVE	(2 << 0)
> -#define  VLV_EDP_PSR_ACTIVE_NORFB_UP	(3 << 0)
> -#define  VLV_EDP_PSR_ACTIVE_SF_UPDATE	(4 << 0)
> -#define  VLV_EDP_PSR_EXIT		(5 << 0)
> -#define  VLV_EDP_PSR_IN_TRANS		(1 << 7)
> -#define VLV_PSRSTAT(pipe)	_MMIO_PIPE(pipe, _PSRSTATA, _PSRSTATB)
> -
>  /* HSW+ eDP PSR registers */
>  #define HSW_EDP_PSR_BASE	0x64800
>  #define BDW_EDP_PSR_BASE	0x6f800
> -- 
> 2.21.0
> 
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  reply	other threads:[~2019-04-04  0:22 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-03 23:35 [PATCH 1/7] drm/i915/psr: Update PSR2 SU corruption workaround comment José Roberto de Souza
2019-04-03 23:35 ` [PATCH 2/7] drm/i915: Remove unused VLV/CHV PSR registers José Roberto de Souza
2019-04-04  0:22   ` Rodrigo Vivi [this message]
2019-04-03 23:35 ` [PATCH 3/7] drm/i915/psr: Initialize PSR mutex even when sink is not reliable José Roberto de Souza
2019-04-04  0:27   ` Rodrigo Vivi
2019-04-04 19:25     ` Souza, Jose
2019-04-04 23:22       ` Rodrigo Vivi
2019-04-05  0:22   ` Dhinakaran Pandiyan
2019-04-05  0:32     ` Souza, Jose
2019-04-05  0:45       ` Dhinakaran Pandiyan
2019-04-03 23:35 ` [PATCH 4/7] drm/i915/psr: Do not enable PSR in interlaced mode for all GENs José Roberto de Souza
2019-04-04  0:29   ` Rodrigo Vivi
2019-04-04 22:02     ` Dhinakaran Pandiyan
2019-04-03 23:35 ` [PATCH 5/7] drm/i915/bdw+: Move misc display IRQ handling to it own function José Roberto de Souza
2019-04-05  0:38   ` Dhinakaran Pandiyan
2019-04-03 23:35 ` [PATCH 6/7] drm/i915/psr: Remove partial PSR support on multiple transcoders José Roberto de Souza
2019-04-04  0:31   ` Rodrigo Vivi
2019-04-04 19:40     ` Souza, Jose
2019-04-04 21:20       ` Rodrigo Vivi
2019-04-04 21:41         ` Pandiyan, Dhinakaran
2019-04-04 21:51           ` Rodrigo Vivi
2019-04-04 22:19             ` Souza, Jose
2019-04-04 22:06           ` Dhinakaran Pandiyan
2019-04-03 23:35 ` [PATCH 7/7] drm/i915: Make PSR registers relative to transcoders José Roberto de Souza
2019-04-06  0:55   ` Dhinakaran Pandiyan
2019-04-06  1:05     ` Souza, Jose
2019-04-03 23:43 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] drm/i915/psr: Update PSR2 SU corruption workaround comment Patchwork
2019-04-03 23:46 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-04-04  0:04 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-04-04  0:22 ` [PATCH 1/7] " Rodrigo Vivi
2019-04-04  0:39   ` Runyan, Arthur J
2019-04-04  0:51     ` Rodrigo Vivi
2019-04-04 20:37 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] drm/i915/psr: Update PSR2 SU corruption workaround comment (rev2) Patchwork
2019-04-04 20:40 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-04-04 21:01 ` ✓ Fi.CI.BAT: success " Patchwork
2019-04-05 16:44 ` ✓ Fi.CI.IGT: " Patchwork

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