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From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: "José Roberto de Souza" <jose.souza@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
	Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Subject: Re: [PATCH 4/7] drm/i915/psr: Do not enable PSR in interlaced mode for all GENs
Date: Wed, 3 Apr 2019 17:29:28 -0700	[thread overview]
Message-ID: <20190404002928.GD25758@intel.com> (raw)
In-Reply-To: <20190403233539.31828-4-jose.souza@intel.com>

On Wed, Apr 03, 2019 at 04:35:36PM -0700, José Roberto de Souza wrote:
> This interlaced restriction applies to all gens, not only to Haswell.

I believe this came from VLV times and I doubt we would be
impacted by it ever, but better to protect just in case:


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


> 
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_psr.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index a84da931c3be..bb97c1657493 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -627,8 +627,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
>  		return;
>  	}
>  
> -	if (IS_HASWELL(dev_priv) &&
> -	    adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> +	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
>  		DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
>  		return;
>  	}
> -- 
> 2.21.0
> 
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  reply	other threads:[~2019-04-04  0:29 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-03 23:35 [PATCH 1/7] drm/i915/psr: Update PSR2 SU corruption workaround comment José Roberto de Souza
2019-04-03 23:35 ` [PATCH 2/7] drm/i915: Remove unused VLV/CHV PSR registers José Roberto de Souza
2019-04-04  0:22   ` Rodrigo Vivi
2019-04-03 23:35 ` [PATCH 3/7] drm/i915/psr: Initialize PSR mutex even when sink is not reliable José Roberto de Souza
2019-04-04  0:27   ` Rodrigo Vivi
2019-04-04 19:25     ` Souza, Jose
2019-04-04 23:22       ` Rodrigo Vivi
2019-04-05  0:22   ` Dhinakaran Pandiyan
2019-04-05  0:32     ` Souza, Jose
2019-04-05  0:45       ` Dhinakaran Pandiyan
2019-04-03 23:35 ` [PATCH 4/7] drm/i915/psr: Do not enable PSR in interlaced mode for all GENs José Roberto de Souza
2019-04-04  0:29   ` Rodrigo Vivi [this message]
2019-04-04 22:02     ` Dhinakaran Pandiyan
2019-04-03 23:35 ` [PATCH 5/7] drm/i915/bdw+: Move misc display IRQ handling to it own function José Roberto de Souza
2019-04-05  0:38   ` Dhinakaran Pandiyan
2019-04-03 23:35 ` [PATCH 6/7] drm/i915/psr: Remove partial PSR support on multiple transcoders José Roberto de Souza
2019-04-04  0:31   ` Rodrigo Vivi
2019-04-04 19:40     ` Souza, Jose
2019-04-04 21:20       ` Rodrigo Vivi
2019-04-04 21:41         ` Pandiyan, Dhinakaran
2019-04-04 21:51           ` Rodrigo Vivi
2019-04-04 22:19             ` Souza, Jose
2019-04-04 22:06           ` Dhinakaran Pandiyan
2019-04-03 23:35 ` [PATCH 7/7] drm/i915: Make PSR registers relative to transcoders José Roberto de Souza
2019-04-06  0:55   ` Dhinakaran Pandiyan
2019-04-06  1:05     ` Souza, Jose
2019-04-03 23:43 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] drm/i915/psr: Update PSR2 SU corruption workaround comment Patchwork
2019-04-03 23:46 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-04-04  0:04 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-04-04  0:22 ` [PATCH 1/7] " Rodrigo Vivi
2019-04-04  0:39   ` Runyan, Arthur J
2019-04-04  0:51     ` Rodrigo Vivi
2019-04-04 20:37 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/7] drm/i915/psr: Update PSR2 SU corruption workaround comment (rev2) Patchwork
2019-04-04 20:40 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-04-04 21:01 ` ✓ Fi.CI.BAT: success " Patchwork
2019-04-05 16:44 ` ✓ Fi.CI.IGT: " Patchwork

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