From: Manasi Navare <manasi.d.navare@intel.com>
To: "Souza, Jose" <jose.souza@intel.com>
Cc: "intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"De Marchi, Lucas" <lucas.demarchi@intel.com>
Subject: Re: [PATCH v2 08/25] drm/i915/tgl: use TRANSCODER_EDP_VDSC on transcoder A
Date: Tue, 9 Jul 2019 13:00:53 -0700 [thread overview]
Message-ID: <20190709200053.GA19906@intel.com> (raw)
In-Reply-To: <78195a95a2f4e18aa3e1ce003150365f0cc038f1.camel@intel.com>
On Tue, Jul 09, 2019 at 01:07:17AM +0000, Souza, Jose wrote:
> On Mon, 2019-07-08 at 16:16 -0700, Lucas De Marchi wrote:
> > From: José Roberto de Souza <jose.souza@intel.com>
> >
> > On TGL the special EDP transcoder is gone and it should be handled by
> > transcoder A.
> >
> > v2 (Lucas):
> > - Reuse POWER_DOMAIN_TRANSCODER_EDP_VDSC (suggested by Ville)
> > - Use crtc->dev since new_crtc_state->state may be NULL on atomic
> > commit (suggested by Maarten)
>
> As we are reusing would be nice also rename it to something like:
> POWER_DOMAIN_TRANSCODER_VDSC_PW2
> POWER_DOMAIN_LOW_POWER_TRANSCODER_VDSC /
> POWER_DOMAIN_LP_TRANSCODER_VDSC
We did struggle initially as well to find an appropriate name and settled for
POWER_DOMAIN_TRANSCODER_EDP_VDSC but I agree that now since it is not just for EDP
but for Transcoder A which could be any connector, its better to rename the power well
POWER_DOMAIN_TRANSCODER_VDSC_PW2 or
POWER_DOMAIN_TRANSCODER_EDP_A_VDSC and then in the comment clearly mention that
for Gen 11 it is for Transcoder EDP VDSC and then Gen 12 + it is for Transcoder A VDSC
Manasi
>
> >
> > Cc: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_vdsc.c | 9 ++++++---
> > 1 file changed, 6 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > index ffec807b8960..c27912f552f0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> > @@ -459,16 +459,19 @@ int intel_dp_compute_dsc_params(struct intel_dp
> > *intel_dp,
> > enum intel_display_power_domain
> > intel_dsc_power_domain(const struct intel_crtc_state *crtc_state)
> > {
> > + struct drm_i915_private *i915 = to_i915(crtc_state->base.crtc-
> > >dev);
> > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> >
> > /*
> > - * On ICL VDSC/joining for eDP transcoder uses a separate power
> > well PW2
> > - * This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power domain.
> > + * On ICL+ VDSC/joining for eDP/A transcoder uses a separate
> > power well
> > + * PW2. This requires POWER_DOMAIN_TRANSCODER_EDP_VDSC power
> > domain.
> > * For any other transcoder, VDSC/joining uses the power well
> > associated
> > * with the pipe/transcoder in use. Hence another reference on
> > the
> > * transcoder power domain will suffice.
> > */
> > - if (cpu_transcoder == TRANSCODER_EDP)
> > + if (INTEL_GEN(i915) >= 12 && cpu_transcoder == TRANSCODER_A)
> > + return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
> > + else if (cpu_transcoder == TRANSCODER_EDP)
> > return POWER_DOMAIN_TRANSCODER_EDP_VDSC;
> > else
> > return POWER_DOMAIN_TRANSCODER(cpu_transcoder);
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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next prev parent reply other threads:[~2019-07-09 19:58 UTC|newest]
Thread overview: 73+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-08 23:16 [PATCH v2 00/25] Initial support for Tiger Lake Lucas De Marchi
2019-07-08 23:16 ` [PATCH v2 01/25] drm/i915: Add 4th pipe and transcoder Lucas De Marchi
2019-07-08 23:16 ` [PATCH v2 02/25] drm/i915/tgl: add initial Tiger Lake definitions Lucas De Marchi
2019-07-08 23:16 ` [PATCH v2 03/25] drm/i915/tgl: Introduce Tiger Lake PCH Lucas De Marchi
2019-07-09 12:04 ` Rodrigo Vivi
2019-07-08 23:16 ` [PATCH v2 04/25] drm/i915/tgl: Add TGL PCH detection in virtualized environment Lucas De Marchi
2019-07-08 23:16 ` [PATCH v2 05/25] drm/i915/tgl: Add TGL PCI IDs Lucas De Marchi
2019-07-09 11:52 ` Rodrigo Vivi
2019-07-09 12:26 ` Kahola, Mika
2019-07-08 23:16 ` [PATCH v2 06/25] x86/gpu: add TGL stolen memory support Lucas De Marchi
2019-07-08 23:16 ` [PATCH v2 07/25] drm/i915/tgl: Check if pipe D is fused Lucas De Marchi
2019-07-09 12:39 ` Kahola, Mika
2019-07-08 23:16 ` [PATCH v2 08/25] drm/i915/tgl: use TRANSCODER_EDP_VDSC on transcoder A Lucas De Marchi
2019-07-09 1:07 ` Souza, Jose
2019-07-09 16:01 ` Lucas De Marchi
2019-07-09 20:00 ` Manasi Navare [this message]
2019-07-10 19:49 ` [PATCH] drm/i915/tgl: rename TRANSCODER_EDP_VDSC to use " Lucas De Marchi
2019-07-10 23:40 ` Souza, Jose
2019-07-08 23:16 ` [PATCH v2 09/25] drm/i915/tgl: Add power well support Lucas De Marchi
2019-07-09 15:53 ` Ville Syrjälä
2019-07-10 19:54 ` [PATCH v3] " Lucas De Marchi
2019-07-08 23:16 ` [PATCH v2 10/25] drm/i915/tgl: Add power well to support 4th pipe Lucas De Marchi
2019-07-09 11:57 ` Rodrigo Vivi
2019-07-09 16:20 ` Lucas De Marchi
2019-07-10 11:04 ` Rodrigo Vivi
2019-07-10 16:02 ` Lucas De Marchi
2019-07-10 16:42 ` Rodrigo Vivi
2019-07-10 19:58 ` [PATCH v2] " Lucas De Marchi
2019-07-08 23:16 ` [PATCH v2 11/25] drm/i915/tgl: Add new pll ids Lucas De Marchi
2019-07-08 23:16 ` [PATCH v2 12/25] drm/i915/tgl: Add pll manager Lucas De Marchi
2019-07-09 12:14 ` Rodrigo Vivi
2019-07-08 23:16 ` [PATCH v2 13/25] drm/i915/tgl: Add additional ports for Tiger Lake Lucas De Marchi
2019-07-09 19:43 ` Souza, Jose
2019-07-08 23:16 ` [PATCH v2 14/25] drm/i915/tgl: update ddi/tc clock_off bits Lucas De Marchi
2019-07-09 19:49 ` Souza, Jose
2019-07-09 19:58 ` Lucas De Marchi
2019-07-08 23:16 ` [PATCH v2 15/25] drm/i915/tgl: Add gmbus gpio pin to port mapping Lucas De Marchi
2019-07-11 0:19 ` Souza, Jose
2019-07-08 23:16 ` [PATCH v2 16/25] drm/i915/tgl: port to ddc pin mapping Lucas De Marchi
2019-07-09 12:11 ` Rodrigo Vivi
2019-07-09 16:28 ` Lucas De Marchi
2019-07-09 17:00 ` [PATCH v3 " Lucas De Marchi
2019-07-10 11:01 ` Rodrigo Vivi
2019-07-08 23:16 ` [PATCH v2 17/25] drm/i915/tgl: select correct bit for port select Lucas De Marchi
2019-07-10 18:40 ` Ville Syrjälä
2019-07-10 22:52 ` Lucas De Marchi
2019-07-08 23:16 ` [PATCH v2 18/25] drm/i915/tgl: extend intel_port_is_combophy/tc Lucas De Marchi
2019-07-09 19:54 ` Souza, Jose
2019-07-08 23:16 ` [PATCH v2 19/25] drm/i915/tgl: init ddi port A-C for Tiger Lake Lucas De Marchi
2019-07-09 19:55 ` Souza, Jose
2019-07-08 23:16 ` [PATCH v2 20/25] drm/i915/tgl: Add vbt value mapping for DDC Bus pin Lucas De Marchi
2019-07-11 0:21 ` Souza, Jose
2019-07-08 23:16 ` [PATCH v2 21/25] drm/i915/tgl: apply Display WA #1178 to fix type C dongles Lucas De Marchi
2019-07-09 12:13 ` Rodrigo Vivi
2019-07-08 23:16 ` [PATCH v2 22/25] drm/i915/gen12: MBUS B credit change Lucas De Marchi
2019-07-09 15:58 ` Ville Syrjälä
2019-07-08 23:16 ` [PATCH v2 23/25] drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization Lucas De Marchi
2019-07-09 20:10 ` Souza, Jose
2019-07-08 23:16 ` [PATCH v2 24/25] drm/i915/tgl: Add DPLL registers Lucas De Marchi
2019-07-09 12:56 ` Ville Syrjälä
2019-07-09 15:58 ` Lucas De Marchi
2019-07-10 18:43 ` Ville Syrjälä
2019-07-08 23:16 ` [PATCH v2 25/25] drm/i915/tgl: Update DPLL clock reference register Lucas De Marchi
2019-07-09 12:48 ` Ville Syrjälä
2019-07-08 23:29 ` ✗ Fi.CI.CHECKPATCH: warning for Initial support for Tiger Lake (rev2) Patchwork
2019-07-08 23:52 ` ✓ Fi.CI.BAT: success " Patchwork
2019-07-09 13:17 ` ✓ Fi.CI.IGT: " Patchwork
2019-07-09 18:24 ` ✗ Fi.CI.CHECKPATCH: warning for Initial support for Tiger Lake (rev3) Patchwork
2019-07-09 18:46 ` ✓ Fi.CI.BAT: success " Patchwork
2019-07-10 10:34 ` ✓ Fi.CI.IGT: " Patchwork
2019-07-10 20:32 ` ✗ Fi.CI.CHECKPATCH: warning for Initial support for Tiger Lake (rev6) Patchwork
2019-07-11 12:15 ` ✓ Fi.CI.BAT: success " Patchwork
2019-07-11 20:28 ` ✓ Fi.CI.IGT: " Patchwork
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