Re: [PATCH v2 24/25] drm/i915/tgl: Add DPLL registers

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Tue, Jul 09, 2019 at 08:58:32AM -0700, Lucas De Marchi wrote:
> On Tue, Jul 09, 2019 at 03:56:51PM +0300, Ville Syrjälä wrote:
> >On Mon, Jul 08, 2019 at 04:16:28PM -0700, Lucas De Marchi wrote:
> >> On TGL the port programming for combophy is very similar to ICL, so
> >> adapt the callers to possibly use the different register values.
> >>
> >> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> >> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 24 +++++++++++++++----
> >>  drivers/gpu/drm/i915/i915_reg.h               | 15 ++++++++++++
> >>  2 files changed, 34 insertions(+), 5 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> >> index ae1c552d7afb..330b42a1f54e 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> >> @@ -3113,8 +3113,13 @@ static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
> >>  	if (!(val & PLL_ENABLE))
> >>  		goto out;
> >>
> >> -	hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
> >> -	hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
> >> +	if (INTEL_GEN(dev_priv) >= 12) {
> >> +		hw_state->cfgcr0 = I915_READ(TGL_DPLL_CFGCR0(id));
> >> +		hw_state->cfgcr1 = I915_READ(TGL_DPLL_CFGCR1(id));
> >> +	} else {
> >> +		hw_state->cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(id));
> >> +		hw_state->cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(id));
> >> +	}
> >>
> >>  	ret = true;
> >>  out:
> >> @@ -3148,10 +3153,19 @@ static void icl_dpll_write(struct drm_i915_private *dev_priv,
> >>  {
> >>  	struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
> >>  	const enum intel_dpll_id id = pll->info->id;
> >> +	i915_reg_t cfgcr0_reg, cfgcr1_reg;
> >> +
> >> +	if (INTEL_GEN(dev_priv) >= 12) {
> >> +		cfgcr0_reg = TGL_DPLL_CFGCR0(id);
> >> +		cfgcr1_reg = TGL_DPLL_CFGCR1(id);
> >> +	} else {
> >> +		cfgcr0_reg = ICL_DPLL_CFGCR0(id);
> >> +		cfgcr1_reg = ICL_DPLL_CFGCR1(id);
> >> +	}
> >>
> >> -	I915_WRITE(ICL_DPLL_CFGCR0(id), hw_state->cfgcr0);
> >> -	I915_WRITE(ICL_DPLL_CFGCR1(id), hw_state->cfgcr1);
> >> -	POSTING_READ(ICL_DPLL_CFGCR1(id));
> >> +	I915_WRITE(cfgcr0_reg, hw_state->cfgcr0);
> >> +	I915_WRITE(cfgcr1_reg, hw_state->cfgcr1);
> >> +	POSTING_READ(cfgcr1_reg);
> >>  }
> >>
> >>  static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >> index fbcc7981c8c4..84c04ea67ec8 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -242,6 +242,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
> >>  #define _MMIO_PIPE3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
> >>  #define _MMIO_PORT3(pipe, a, b, c)	_MMIO(_PICK(pipe, a, b, c))
> >>  #define _MMIO_PHY3(phy, a, b, c)	_MMIO(_PHY3(phy, a, b, c))
> >> +#define _MMIO_PLL3(pll, a, b, c)	_MMIO(_PICK(pll, a, b, c))
> >>
> >>  /*
> >>   * Device info offset array based helpers for groups of registers with unevenly
> >> @@ -9958,6 +9959,20 @@ enum skl_power_gate {
> >>  #define ICL_DPLL_CFGCR1(pll)		_MMIO_PLL(pll, _ICL_DPLL0_CFGCR1, \
> >>  						  _ICL_DPLL1_CFGCR1)
> >>
> >> +#define _TGL_DPLL0_CFGCR0		0x164284
> >> +#define _TGL_DPLL1_CFGCR0		0x16428C
> >> +#define _TGL_TBTPLL_CFGCR0		0x16429C
> >
> >What about DPLL4?
> 
> not all TGL skus have DPLL4. The ones that do (and were not tested
> here), are very different from what is done for EHL so we can't reuse
> the implementation. I will leave the DPLL4 on TGL for later, when it
> makes sense to add it.

Fair enough. Could maybe use a FIXME/TODO somewhere maybe?

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> 
> Lucas De Marchi
> 
> >
> >In fact looks like the ICL counterparts are borked even for ehl DPLL4.
> >
> >> +#define TGL_DPLL_CFGCR0(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR0, \
> >> +						  _TGL_DPLL1_CFGCR0, \
> >> +						  _TGL_TBTPLL_CFGCR0)
> >> +
> >> +#define _TGL_DPLL0_CFGCR1		0x164288
> >> +#define _TGL_DPLL1_CFGCR1		0x164290
> >> +#define _TGL_TBTPLL_CFGCR1		0x1642A0
> >> +#define TGL_DPLL_CFGCR1(pll)		_MMIO_PLL3(pll, _TGL_DPLL0_CFGCR1, \
> >> +						   _TGL_DPLL1_CFGCR1, \
> >> +						   _TGL_TBTPLL_CFGCR1)
> >> +
> >>  /* BXT display engine PLL */
> >>  #define BXT_DE_PLL_CTL			_MMIO(0x6d000)
> >>  #define   BXT_DE_PLL_RATIO(x)		(x)	/* {60,65,100} * 19.2MHz */
> >> --
> >> 2.21.0
> >
> >-- 
> >Ville Syrjälä
> >Intel

-- 
Ville Syrjälä
Intel
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