From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 10/25] drm/i915/tgl: Add power well to support 4th pipe
Date: Wed, 10 Jul 2019 04:04:29 -0700 [thread overview]
Message-ID: <20190710110429.GK16315@intel.com> (raw)
In-Reply-To: <20190709162042.okv75ozrvplii7tk@ldmartin-desk1>
On Tue, Jul 09, 2019 at 09:20:42AM -0700, Lucas De Marchi wrote:
> On Tue, Jul 09, 2019 at 04:57:32AM -0700, Rodrigo Vivi wrote:
> > On Mon, Jul 08, 2019 at 04:16:14PM -0700, Lucas De Marchi wrote:
> > > From: Mika Kahola <mika.kahola@intel.com>
> > >
> > > Add power well 5 to support 4th pipe and transcoder on TGL.
> > >
> > > Cc: James Ausmus <james.ausmus@intel.com>
> > > Cc: Imre Deak <imre.deak@intel.com>
> > > Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > ---
> > > .../drm/i915/display/intel_display_power.c | 30 ++++++++++++++++---
> > > .../drm/i915/display/intel_display_power.h | 3 ++
> > > drivers/gpu/drm/i915/i915_reg.h | 3 +-
> > > 3 files changed, 31 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > index c3f42169831f..455f9aab188d 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > @@ -37,18 +37,24 @@ intel_display_power_domain_str(struct drm_i915_private *i915,
> > > return "PIPE_B";
> > > case POWER_DOMAIN_PIPE_C:
> > > return "PIPE_C";
> > > + case POWER_DOMAIN_PIPE_D:
> > > + return "PIPE_D";
> > > case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
> > > return "PIPE_A_PANEL_FITTER";
> > > case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
> > > return "PIPE_B_PANEL_FITTER";
> > > case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
> > > return "PIPE_C_PANEL_FITTER";
> > > + case POWER_DOMAIN_PIPE_D_PANEL_FITTER:
> > > + return "PIPE_D_PANEL_FITTER";
> > > case POWER_DOMAIN_TRANSCODER_A:
> > > return "TRANSCODER_A";
> > > case POWER_DOMAIN_TRANSCODER_B:
> > > return "TRANSCODER_B";
> > > case POWER_DOMAIN_TRANSCODER_C:
> > > return "TRANSCODER_C";
> > > + case POWER_DOMAIN_TRANSCODER_D:
> > > + return "TRANSCODER_D";
> > > case POWER_DOMAIN_TRANSCODER_EDP:
> > > return "TRANSCODER_EDP";
> > > case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
> > > @@ -2451,7 +2457,6 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> > > * - DDI_A
> > > * - FBC
> > > */
> > > -/* TODO: TGL_PW_5_POWER_DOMAINS: PIPE_D */
> > > #define ICL_PW_4_POWER_DOMAINS ( \
> > > BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> > > BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> > > @@ -2539,7 +2544,13 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> > > #define ICL_AUX_TBT4_IO_POWER_DOMAINS ( \
> > > BIT_ULL(POWER_DOMAIN_AUX_TBT4))
> > >
> > > +#define TGL_PW_5_POWER_DOMAINS ( \
> > > + BIT_ULL(POWER_DOMAIN_PIPE_D) | \
> > > + BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
> > > + BIT_ULL(POWER_DOMAIN_INIT))
> > > +
> > > #define TGL_PW_4_POWER_DOMAINS ( \
> > > + TGL_PW_5_POWER_DOMAINS | \
> >
> > why?
>
> not sure I understand this one. Are you saying we shouldn't have a new
> power well for pipe d? How would we handle the different ctl?
We should have a new one. The above block who adds PW5 domains is okay.
What I didn't understand is why to add pipe D also on PW4
>
> >
> > > BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> > > BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> > > BIT_ULL(POWER_DOMAIN_INIT))
> > > @@ -2549,7 +2560,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
> > > BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> > > BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> > > BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> > > - /* TODO: TRANSCODER_D */ \
> > > + BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
> > > BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> > > BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_LANES) | \
> > > BIT_ULL(POWER_DOMAIN_PORT_DDI_TC1_IO) | \
> > > @@ -3882,7 +3893,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > > },
> > > {
> > > .name = "power well 4",
> > > - .domains = ICL_PW_4_POWER_DOMAINS,
> > > + .domains = TGL_PW_4_POWER_DOMAINS,
> >
> > why?
>
> this is a leftover from v1 and should be squashed on previous patch, my
> bad. In v1 we were reusing the ICL definitions. I changed in this
> revision and forgot to squash this change there. I will send a new
> version
>
> thanks
>
> Lucas De Marchi
>
> >
> > > .ops = &hsw_power_well_ops,
> > > .id = DISP_PW_ID_NONE,
> > > {
> > > @@ -3892,7 +3903,18 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
> > > .hsw.irq_pipe_mask = BIT(PIPE_C),
> > > }
> > > },
> > > - /* TODO: power well 5 for pipe D */
> > > + {
> > > + .name = "power well 5",
> > > + .domains = TGL_PW_5_POWER_DOMAINS,
> > > + .ops = &hsw_power_well_ops,
> > > + .id = DISP_PW_ID_NONE,
> > > + {
> > > + .hsw.regs = &hsw_power_well_regs,
> > > + .hsw.idx = TGL_PW_CTL_IDX_PW_5,
> > > + .hsw.has_fuses = true,
> > > + .hsw.irq_pipe_mask = BIT(PIPE_D),
> > > + },
> > > + },
> > > };
> > >
> > > static int
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> > > index 86afd70c1fb2..ebb397e330ea 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> > > @@ -18,12 +18,15 @@ enum intel_display_power_domain {
> > > POWER_DOMAIN_PIPE_A,
> > > POWER_DOMAIN_PIPE_B,
> > > POWER_DOMAIN_PIPE_C,
> > > + POWER_DOMAIN_PIPE_D,
> > > POWER_DOMAIN_PIPE_A_PANEL_FITTER,
> > > POWER_DOMAIN_PIPE_B_PANEL_FITTER,
> > > POWER_DOMAIN_PIPE_C_PANEL_FITTER,
> > > + POWER_DOMAIN_PIPE_D_PANEL_FITTER,
> > > POWER_DOMAIN_TRANSCODER_A,
> > > POWER_DOMAIN_TRANSCODER_B,
> > > POWER_DOMAIN_TRANSCODER_C,
> > > + POWER_DOMAIN_TRANSCODER_D,
> > > POWER_DOMAIN_TRANSCODER_EDP,
> > > POWER_DOMAIN_TRANSCODER_EDP_VDSC,
> > > POWER_DOMAIN_TRANSCODER_DSI_A,
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index f59cb5c45c34..5ca74eca05a4 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -9147,7 +9147,8 @@ enum {
> > > #define GLK_PW_CTL_IDX_DDI_A 1
> > > #define SKL_PW_CTL_IDX_MISC_IO 0
> > >
> > > -/* ICL - power wells */
> > > +/* ICL/TGL - power wells */
> > > +#define TGL_PW_CTL_IDX_PW_5 4
> > > #define ICL_PW_CTL_IDX_PW_4 3
> > > #define ICL_PW_CTL_IDX_PW_3 2
> > > #define ICL_PW_CTL_IDX_PW_2 1
> > > --
> > > 2.21.0
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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next prev parent reply other threads:[~2019-07-10 11:03 UTC|newest]
Thread overview: 73+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-08 23:16 [PATCH v2 00/25] Initial support for Tiger Lake Lucas De Marchi
2019-07-08 23:16 ` [PATCH v2 01/25] drm/i915: Add 4th pipe and transcoder Lucas De Marchi
2019-07-08 23:16 ` [PATCH v2 02/25] drm/i915/tgl: add initial Tiger Lake definitions Lucas De Marchi
2019-07-08 23:16 ` [PATCH v2 03/25] drm/i915/tgl: Introduce Tiger Lake PCH Lucas De Marchi
2019-07-09 12:04 ` Rodrigo Vivi
2019-07-08 23:16 ` [PATCH v2 04/25] drm/i915/tgl: Add TGL PCH detection in virtualized environment Lucas De Marchi
2019-07-08 23:16 ` [PATCH v2 05/25] drm/i915/tgl: Add TGL PCI IDs Lucas De Marchi
2019-07-09 11:52 ` Rodrigo Vivi
2019-07-09 12:26 ` Kahola, Mika
2019-07-08 23:16 ` [PATCH v2 06/25] x86/gpu: add TGL stolen memory support Lucas De Marchi
2019-07-08 23:16 ` [PATCH v2 07/25] drm/i915/tgl: Check if pipe D is fused Lucas De Marchi
2019-07-09 12:39 ` Kahola, Mika
2019-07-08 23:16 ` [PATCH v2 08/25] drm/i915/tgl: use TRANSCODER_EDP_VDSC on transcoder A Lucas De Marchi
2019-07-09 1:07 ` Souza, Jose
2019-07-09 16:01 ` Lucas De Marchi
2019-07-09 20:00 ` Manasi Navare
2019-07-10 19:49 ` [PATCH] drm/i915/tgl: rename TRANSCODER_EDP_VDSC to use " Lucas De Marchi
2019-07-10 23:40 ` Souza, Jose
2019-07-08 23:16 ` [PATCH v2 09/25] drm/i915/tgl: Add power well support Lucas De Marchi
2019-07-09 15:53 ` Ville Syrjälä
2019-07-10 19:54 ` [PATCH v3] " Lucas De Marchi
2019-07-08 23:16 ` [PATCH v2 10/25] drm/i915/tgl: Add power well to support 4th pipe Lucas De Marchi
2019-07-09 11:57 ` Rodrigo Vivi
2019-07-09 16:20 ` Lucas De Marchi
2019-07-10 11:04 ` Rodrigo Vivi [this message]
2019-07-10 16:02 ` Lucas De Marchi
2019-07-10 16:42 ` Rodrigo Vivi
2019-07-10 19:58 ` [PATCH v2] " Lucas De Marchi
2019-07-08 23:16 ` [PATCH v2 11/25] drm/i915/tgl: Add new pll ids Lucas De Marchi
2019-07-08 23:16 ` [PATCH v2 12/25] drm/i915/tgl: Add pll manager Lucas De Marchi
2019-07-09 12:14 ` Rodrigo Vivi
2019-07-08 23:16 ` [PATCH v2 13/25] drm/i915/tgl: Add additional ports for Tiger Lake Lucas De Marchi
2019-07-09 19:43 ` Souza, Jose
2019-07-08 23:16 ` [PATCH v2 14/25] drm/i915/tgl: update ddi/tc clock_off bits Lucas De Marchi
2019-07-09 19:49 ` Souza, Jose
2019-07-09 19:58 ` Lucas De Marchi
2019-07-08 23:16 ` [PATCH v2 15/25] drm/i915/tgl: Add gmbus gpio pin to port mapping Lucas De Marchi
2019-07-11 0:19 ` Souza, Jose
2019-07-08 23:16 ` [PATCH v2 16/25] drm/i915/tgl: port to ddc pin mapping Lucas De Marchi
2019-07-09 12:11 ` Rodrigo Vivi
2019-07-09 16:28 ` Lucas De Marchi
2019-07-09 17:00 ` [PATCH v3 " Lucas De Marchi
2019-07-10 11:01 ` Rodrigo Vivi
2019-07-08 23:16 ` [PATCH v2 17/25] drm/i915/tgl: select correct bit for port select Lucas De Marchi
2019-07-10 18:40 ` Ville Syrjälä
2019-07-10 22:52 ` Lucas De Marchi
2019-07-08 23:16 ` [PATCH v2 18/25] drm/i915/tgl: extend intel_port_is_combophy/tc Lucas De Marchi
2019-07-09 19:54 ` Souza, Jose
2019-07-08 23:16 ` [PATCH v2 19/25] drm/i915/tgl: init ddi port A-C for Tiger Lake Lucas De Marchi
2019-07-09 19:55 ` Souza, Jose
2019-07-08 23:16 ` [PATCH v2 20/25] drm/i915/tgl: Add vbt value mapping for DDC Bus pin Lucas De Marchi
2019-07-11 0:21 ` Souza, Jose
2019-07-08 23:16 ` [PATCH v2 21/25] drm/i915/tgl: apply Display WA #1178 to fix type C dongles Lucas De Marchi
2019-07-09 12:13 ` Rodrigo Vivi
2019-07-08 23:16 ` [PATCH v2 22/25] drm/i915/gen12: MBUS B credit change Lucas De Marchi
2019-07-09 15:58 ` Ville Syrjälä
2019-07-08 23:16 ` [PATCH v2 23/25] drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization Lucas De Marchi
2019-07-09 20:10 ` Souza, Jose
2019-07-08 23:16 ` [PATCH v2 24/25] drm/i915/tgl: Add DPLL registers Lucas De Marchi
2019-07-09 12:56 ` Ville Syrjälä
2019-07-09 15:58 ` Lucas De Marchi
2019-07-10 18:43 ` Ville Syrjälä
2019-07-08 23:16 ` [PATCH v2 25/25] drm/i915/tgl: Update DPLL clock reference register Lucas De Marchi
2019-07-09 12:48 ` Ville Syrjälä
2019-07-08 23:29 ` ✗ Fi.CI.CHECKPATCH: warning for Initial support for Tiger Lake (rev2) Patchwork
2019-07-08 23:52 ` ✓ Fi.CI.BAT: success " Patchwork
2019-07-09 13:17 ` ✓ Fi.CI.IGT: " Patchwork
2019-07-09 18:24 ` ✗ Fi.CI.CHECKPATCH: warning for Initial support for Tiger Lake (rev3) Patchwork
2019-07-09 18:46 ` ✓ Fi.CI.BAT: success " Patchwork
2019-07-10 10:34 ` ✓ Fi.CI.IGT: " Patchwork
2019-07-10 20:32 ` ✗ Fi.CI.CHECKPATCH: warning for Initial support for Tiger Lake (rev6) Patchwork
2019-07-11 12:15 ` ✓ Fi.CI.BAT: success " Patchwork
2019-07-11 20:28 ` ✓ Fi.CI.IGT: " Patchwork
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