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From: Manasi Navare <manasi.d.navare@intel.com>
To: Madhumitha Tolakanahalli Pradeep
	<madhumitha.tolakanahalli.pradeep@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL
Date: Thu, 15 Aug 2019 11:24:21 -0700	[thread overview]
Message-ID: <20190815182420.GA22762@intel.com> (raw)
In-Reply-To: <20190814235117.11304-1-madhumitha.tolakanahalli.pradeep@intel.com>

On Wed, Aug 14, 2019 at 04:51:17PM -0700, Madhumitha Tolakanahalli Pradeep wrote:
> Removing restriction on Pipe A as TigerLake onwards, all the pipes support DSC.

May be elaborate this commit message a little bit something like:
"On previous platforms, DSC was not supported on Pipe A while starting TGL, its is supported
on all pipes. So remove the DSC and FEC restriction on Pipe A for TGL onwards.

> 
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++++++++----
>  1 file changed, 12 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4884c87c8ed7..a5b50f93fac5 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1739,8 +1739,12 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  
> -	return INTEL_GEN(dev_priv) >= 11 &&
> -		pipe_config->cpu_transcoder != TRANSCODER_A;
> +	/* On TGL, DSC is supported on all Pipes */

                   ^^^^ FEC supported on all pipes
> +	if (INTEL_GEN(dev_priv) >= 12)
> +		return true;
> +	else
> +		return INTEL_GEN(dev_priv) == 11 &&
> +			pipe_config->cpu_transcoder != TRANSCODER_A;
>  }
>  
>  static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
> @@ -1755,8 +1759,12 @@ static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  
> -	return INTEL_GEN(dev_priv) >= 10 &&
> -		pipe_config->cpu_transcoder != TRANSCODER_A;
> +	/* On TGL, DSC is supported on all Pipes */
> +	if (INTEL_GEN(dev_priv) >= 12)
> +		return true;
> +	else
> +		return (INTEL_GEN(dev_priv) == 10 || INTEL_GEN(dev_priv) == 11) &&

Why cant you just use INTEL_GEN(dev_priv) >=10 ?

Manasi

> +			pipe_config->cpu_transcoder != TRANSCODER_A;
>  }
>  
>  static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
> -- 
> 2.17.1
> 
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  parent reply	other threads:[~2019-08-15 18:22 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-14 23:51 [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL Madhumitha Tolakanahalli Pradeep
2019-08-15  0:04 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2019-08-15  1:05 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-15 18:01 ` ✓ Fi.CI.IGT: " Patchwork
2019-08-15 18:24 ` Manasi Navare [this message]
2019-08-15 18:39   ` [PATCH] " Tolakanahalli Pradeep, Madhumitha
2019-08-15 18:53     ` Manasi Navare
2019-08-15 19:07       ` Tolakanahalli Pradeep, Madhumitha
  -- strict thread matches above, loose matches on Subject: below --
2019-08-23  0:46 Madhumitha Tolakanahalli Pradeep
2019-08-23  0:59 ` Manasi Navare
2019-08-23  8:50 ` Lucas De Marchi
2019-08-28 20:12 ` Manasi Navare

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