* [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL
@ 2019-08-14 23:51 Madhumitha Tolakanahalli Pradeep
2019-08-15 0:04 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (3 more replies)
0 siblings, 4 replies; 12+ messages in thread
From: Madhumitha Tolakanahalli Pradeep @ 2019-08-14 23:51 UTC (permalink / raw)
To: intel-gfx
Removing restriction on Pipe A as TigerLake onwards, all the pipes support DSC.
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4884c87c8ed7..a5b50f93fac5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1739,8 +1739,12 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- return INTEL_GEN(dev_priv) >= 11 &&
- pipe_config->cpu_transcoder != TRANSCODER_A;
+ /* On TGL, DSC is supported on all Pipes */
+ if (INTEL_GEN(dev_priv) >= 12)
+ return true;
+ else
+ return INTEL_GEN(dev_priv) == 11 &&
+ pipe_config->cpu_transcoder != TRANSCODER_A;
}
static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
@@ -1755,8 +1759,12 @@ static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- return INTEL_GEN(dev_priv) >= 10 &&
- pipe_config->cpu_transcoder != TRANSCODER_A;
+ /* On TGL, DSC is supported on all Pipes */
+ if (INTEL_GEN(dev_priv) >= 12)
+ return true;
+ else
+ return (INTEL_GEN(dev_priv) == 10 || INTEL_GEN(dev_priv) == 11) &&
+ pipe_config->cpu_transcoder != TRANSCODER_A;
}
static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
--
2.17.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: Enabling DSC on Pipe A for TGL 2019-08-14 23:51 [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL Madhumitha Tolakanahalli Pradeep @ 2019-08-15 0:04 ` Patchwork 2019-08-15 1:05 ` ✓ Fi.CI.BAT: success " Patchwork ` (2 subsequent siblings) 3 siblings, 0 replies; 12+ messages in thread From: Patchwork @ 2019-08-15 0:04 UTC (permalink / raw) To: Madhumitha Tolakanahalli Pradeep; +Cc: intel-gfx == Series Details == Series: drm/i915/tgl: Enabling DSC on Pipe A for TGL URL : https://patchwork.freedesktop.org/series/65216/ State : warning == Summary == $ dim checkpatch origin/drm-tip 92b16928782e drm/i915/tgl: Enabling DSC on Pipe A for TGL -:7: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #7: Removing restriction on Pipe A as TigerLake onwards, all the pipes support DSC. total: 0 errors, 1 warnings, 0 checks, 28 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/tgl: Enabling DSC on Pipe A for TGL 2019-08-14 23:51 [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL Madhumitha Tolakanahalli Pradeep 2019-08-15 0:04 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork @ 2019-08-15 1:05 ` Patchwork 2019-08-15 18:01 ` ✓ Fi.CI.IGT: " Patchwork 2019-08-15 18:24 ` [PATCH] " Manasi Navare 3 siblings, 0 replies; 12+ messages in thread From: Patchwork @ 2019-08-15 1:05 UTC (permalink / raw) To: Madhumitha Tolakanahalli Pradeep; +Cc: intel-gfx == Series Details == Series: drm/i915/tgl: Enabling DSC on Pipe A for TGL URL : https://patchwork.freedesktop.org/series/65216/ State : success == Summary == CI Bug Log - changes from CI_DRM_6710 -> Patchwork_14019 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/ Known issues ------------ Here are the changes found in Patchwork_14019 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_suspend@basic-s4-devices: - fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/fi-blb-e6850/igt@gem_exec_suspend@basic-s4-devices.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/fi-blb-e6850/igt@gem_exec_suspend@basic-s4-devices.html #### Possible fixes #### * igt@i915_selftest@live_mman: - fi-bsw-n3050: [DMESG-WARN][3] ([fdo#111373]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/fi-bsw-n3050/igt@i915_selftest@live_mman.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/fi-bsw-n3050/igt@i915_selftest@live_mman.html * igt@kms_busy@basic-flip-a: - fi-kbl-7567u: [SKIP][5] ([fdo#109271] / [fdo#109278]) -> [PASS][6] +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/fi-kbl-7567u/igt@kms_busy@basic-flip-a.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/fi-kbl-7567u/igt@kms_busy@basic-flip-a.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [fdo#111373]: https://bugs.freedesktop.org/show_bug.cgi?id=111373 Participating hosts (53 -> 46) ------------------------------ Additional (1): fi-kbl-8809g Missing (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_6710 -> Patchwork_14019 CI-20190529: 20190529 CI_DRM_6710: 131c6ccdf21739498689f22c973b1b77660ae7b9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5134: 81df2f22385bc275975cf199d962eed9bc10f916 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14019: 92b16928782e1044339b264ad631dfea34712ec3 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 92b16928782e drm/i915/tgl: Enabling DSC on Pipe A for TGL == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/tgl: Enabling DSC on Pipe A for TGL 2019-08-14 23:51 [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL Madhumitha Tolakanahalli Pradeep 2019-08-15 0:04 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork 2019-08-15 1:05 ` ✓ Fi.CI.BAT: success " Patchwork @ 2019-08-15 18:01 ` Patchwork 2019-08-15 18:24 ` [PATCH] " Manasi Navare 3 siblings, 0 replies; 12+ messages in thread From: Patchwork @ 2019-08-15 18:01 UTC (permalink / raw) To: Madhumitha Tolakanahalli Pradeep; +Cc: intel-gfx == Series Details == Series: drm/i915/tgl: Enabling DSC on Pipe A for TGL URL : https://patchwork.freedesktop.org/series/65216/ State : success == Summary == CI Bug Log - changes from CI_DRM_6710_full -> Patchwork_14019_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_14019_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_eio@in-flight-suspend: - shard-apl: [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/shard-apl5/igt@gem_eio@in-flight-suspend.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/shard-apl7/igt@gem_eio@in-flight-suspend.html * igt@gem_exec_balancer@smoke: - shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#110854]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/shard-iclb2/igt@gem_exec_balancer@smoke.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/shard-iclb3/igt@gem_exec_balancer@smoke.html * igt@gem_exec_schedule@preempt-other-chain-bsd: - shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +3 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/shard-iclb7/igt@gem_exec_schedule@preempt-other-chain-bsd.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/shard-iclb4/igt@gem_exec_schedule@preempt-other-chain-bsd.html * igt@i915_suspend@sysfs-reader: - shard-skl: [PASS][7] -> [INCOMPLETE][8] ([fdo#104108]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/shard-skl6/igt@i915_suspend@sysfs-reader.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/shard-skl6/igt@i915_suspend@sysfs-reader.html * igt@kms_cursor_legacy@cursor-vs-flip-atomic: - shard-hsw: [PASS][9] -> [FAIL][10] ([fdo#103355]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/shard-hsw8/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/shard-hsw4/igt@kms_cursor_legacy@cursor-vs-flip-atomic.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-kbl: [PASS][11] -> [INCOMPLETE][12] ([fdo#103665]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite: - shard-iclb: [PASS][13] -> [FAIL][14] ([fdo#103167]) +4 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145] / [fdo#110403]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt@kms_plane_lowres@pipe-a-tiling-y: - shard-iclb: [PASS][17] -> [FAIL][18] ([fdo#103166]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/shard-iclb8/igt@kms_plane_lowres@pipe-a-tiling-y.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/shard-iclb7/igt@kms_plane_lowres@pipe-a-tiling-y.html * igt@kms_psr@psr2_cursor_render: - shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/shard-iclb2/igt@kms_psr@psr2_cursor_render.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/shard-iclb5/igt@kms_psr@psr2_cursor_render.html * igt@prime_vgem@fence-wait-bsd2: - shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109276]) +19 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/shard-iclb5/igt@prime_vgem@fence-wait-bsd2.html * igt@sw_sync@sync_multi_consumer: - shard-apl: [PASS][23] -> [INCOMPLETE][24] ([fdo#103927]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/shard-apl3/igt@sw_sync@sync_multi_consumer.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/shard-apl5/igt@sw_sync@sync_multi_consumer.html #### Possible fixes #### * igt@gem_eio@reset-stress: - shard-snb: [FAIL][25] ([fdo#109661]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/shard-snb2/igt@gem_eio@reset-stress.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/shard-snb5/igt@gem_eio@reset-stress.html * igt@gem_exec_schedule@promotion-bsd1: - shard-iclb: [SKIP][27] ([fdo#109276]) -> [PASS][28] +19 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/shard-iclb7/igt@gem_exec_schedule@promotion-bsd1.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/shard-iclb4/igt@gem_exec_schedule@promotion-bsd1.html * igt@gem_exec_schedule@reorder-wide-bsd: - shard-iclb: [SKIP][29] ([fdo#111325]) -> [PASS][30] +5 similar issues [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/shard-iclb4/igt@gem_exec_schedule@reorder-wide-bsd.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/shard-iclb8/igt@gem_exec_schedule@reorder-wide-bsd.html * igt@gem_softpin@noreloc-s3: - shard-skl: [INCOMPLETE][31] ([fdo#104108]) -> [PASS][32] +1 similar issue [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/shard-skl3/igt@gem_softpin@noreloc-s3.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/shard-skl1/igt@gem_softpin@noreloc-s3.html * igt@gem_tiled_swapping@non-threaded: - shard-glk: [DMESG-WARN][33] ([fdo#108686]) -> [PASS][34] [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/shard-glk5/igt@gem_tiled_swapping@non-threaded.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/shard-glk1/igt@gem_tiled_swapping@non-threaded.html * igt@gem_workarounds@suspend-resume-context: - shard-apl: [DMESG-WARN][35] ([fdo#108566]) -> [PASS][36] +3 similar issues [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/shard-apl5/igt@gem_workarounds@suspend-resume-context.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/shard-apl4/igt@gem_workarounds@suspend-resume-context.html * igt@kms_flip@plain-flip-ts-check: - shard-skl: [FAIL][37] ([fdo#100368]) -> [PASS][38] [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/shard-skl8/igt@kms_flip@plain-flip-ts-check.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/shard-skl5/igt@kms_flip@plain-flip-ts-check.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite: - shard-iclb: [FAIL][39] ([fdo#103167]) -> [PASS][40] +5 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/shard-iclb8/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite: - shard-snb: [SKIP][41] ([fdo#109271]) -> [PASS][42] [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/shard-snb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/shard-snb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite.html * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping: - shard-iclb: [INCOMPLETE][43] ([fdo#107713] / [fdo#110036 ]) -> [PASS][44] [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/shard-iclb7/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/shard-iclb4/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-iclb: [INCOMPLETE][45] ([fdo#107713] / [fdo#110042]) -> [PASS][46] [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/shard-iclb3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/shard-iclb3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: - shard-skl: [FAIL][47] ([fdo#108145]) -> [PASS][48] [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - shard-skl: [FAIL][49] ([fdo#108145] / [fdo#110403]) -> [PASS][50] [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [SKIP][51] ([fdo#109441]) -> [PASS][52] +2 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/shard-iclb5/igt@kms_psr@psr2_sprite_plane_move.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html * igt@kms_setmode@basic: - shard-apl: [FAIL][53] ([fdo#99912]) -> [PASS][54] [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/shard-apl7/igt@kms_setmode@basic.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/shard-apl6/igt@kms_setmode@basic.html * igt@perf@blocking: - shard-skl: [FAIL][55] ([fdo#110728]) -> [PASS][56] [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/shard-skl1/igt@perf@blocking.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/shard-skl2/igt@perf@blocking.html #### Warnings #### * igt@gem_ctx_isolation@vcs1-nonpriv: - shard-iclb: [FAIL][57] ([fdo#111329]) -> [SKIP][58] ([fdo#109276]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6710/shard-iclb2/igt@gem_ctx_isolation@vcs1-nonpriv.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/shard-iclb3/igt@gem_ctx_isolation@vcs1-nonpriv.html [fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368 [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166 [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167 [fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355 [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665 [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927 [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108 [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566 [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661 [fdo#110036 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110036 [fdo#110042]: https://bugs.freedesktop.org/show_bug.cgi?id=110042 [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403 [fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728 [fdo#110854]: https://bugs.freedesktop.org/show_bug.cgi?id=110854 [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325 [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329 [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912 Participating hosts (10 -> 10) ------------------------------ No changes in participating hosts Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_6710 -> Patchwork_14019 CI-20190529: 20190529 CI_DRM_6710: 131c6ccdf21739498689f22c973b1b77660ae7b9 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5134: 81df2f22385bc275975cf199d962eed9bc10f916 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_14019: 92b16928782e1044339b264ad631dfea34712ec3 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14019/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL 2019-08-14 23:51 [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL Madhumitha Tolakanahalli Pradeep ` (2 preceding siblings ...) 2019-08-15 18:01 ` ✓ Fi.CI.IGT: " Patchwork @ 2019-08-15 18:24 ` Manasi Navare 2019-08-15 18:39 ` Tolakanahalli Pradeep, Madhumitha 3 siblings, 1 reply; 12+ messages in thread From: Manasi Navare @ 2019-08-15 18:24 UTC (permalink / raw) To: Madhumitha Tolakanahalli Pradeep; +Cc: intel-gfx On Wed, Aug 14, 2019 at 04:51:17PM -0700, Madhumitha Tolakanahalli Pradeep wrote: > Removing restriction on Pipe A as TigerLake onwards, all the pipes support DSC. May be elaborate this commit message a little bit something like: "On previous platforms, DSC was not supported on Pipe A while starting TGL, its is supported on all pipes. So remove the DSC and FEC restriction on Pipe A for TGL onwards. > > Cc: Manasi Navare <manasi.d.navare@intel.com> > Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++++++++---- > 1 file changed, 12 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 4884c87c8ed7..a5b50f93fac5 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -1739,8 +1739,12 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp, > { > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > - return INTEL_GEN(dev_priv) >= 11 && > - pipe_config->cpu_transcoder != TRANSCODER_A; > + /* On TGL, DSC is supported on all Pipes */ ^^^^ FEC supported on all pipes > + if (INTEL_GEN(dev_priv) >= 12) > + return true; > + else > + return INTEL_GEN(dev_priv) == 11 && > + pipe_config->cpu_transcoder != TRANSCODER_A; > } > > static bool intel_dp_supports_fec(struct intel_dp *intel_dp, > @@ -1755,8 +1759,12 @@ static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp, > { > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > - return INTEL_GEN(dev_priv) >= 10 && > - pipe_config->cpu_transcoder != TRANSCODER_A; > + /* On TGL, DSC is supported on all Pipes */ > + if (INTEL_GEN(dev_priv) >= 12) > + return true; > + else > + return (INTEL_GEN(dev_priv) == 10 || INTEL_GEN(dev_priv) == 11) && Why cant you just use INTEL_GEN(dev_priv) >=10 ? Manasi > + pipe_config->cpu_transcoder != TRANSCODER_A; > } > > static bool intel_dp_supports_dsc(struct intel_dp *intel_dp, > -- > 2.17.1 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL 2019-08-15 18:24 ` [PATCH] " Manasi Navare @ 2019-08-15 18:39 ` Tolakanahalli Pradeep, Madhumitha 2019-08-15 18:53 ` Manasi Navare 0 siblings, 1 reply; 12+ messages in thread From: Tolakanahalli Pradeep, Madhumitha @ 2019-08-15 18:39 UTC (permalink / raw) To: Navare, Manasi D; +Cc: intel-gfx@lists.freedesktop.org On Thu, 2019-08-15 at 11:24 -0700, Manasi Navare wrote: > On Wed, Aug 14, 2019 at 04:51:17PM -0700, Madhumitha Tolakanahalli > Pradeep wrote: > > Removing restriction on Pipe A as TigerLake onwards, all the pipes > > support DSC. > > May be elaborate this commit message a little bit something like: > "On previous platforms, DSC was not supported on Pipe A while > starting TGL, its is supported > on all pipes. So remove the DSC and FEC restriction on Pipe A for TGL > onwards. > Alright, will update that for rev2. > > > > Cc: Manasi Navare <manasi.d.navare@intel.com> > > Signed-off-by: Madhumitha Tolakanahalli Pradeep < > > madhumitha.tolakanahalli.pradeep@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++++++++---- > > 1 file changed, 12 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > b/drivers/gpu/drm/i915/display/intel_dp.c > > index 4884c87c8ed7..a5b50f93fac5 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > @@ -1739,8 +1739,12 @@ static bool > > intel_dp_source_supports_fec(struct intel_dp *intel_dp, > > { > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > > > - return INTEL_GEN(dev_priv) >= 11 && > > - pipe_config->cpu_transcoder != TRANSCODER_A; > > + /* On TGL, DSC is supported on all Pipes */ > > ^^^^ FEC supported on all pipes Oops, will change this. > > + if (INTEL_GEN(dev_priv) >= 12) > > + return true; > > + else > > + return INTEL_GEN(dev_priv) == 11 && > > + pipe_config->cpu_transcoder != TRANSCODER_A; > > } > > > > static bool intel_dp_supports_fec(struct intel_dp *intel_dp, > > @@ -1755,8 +1759,12 @@ static bool > > intel_dp_source_supports_dsc(struct intel_dp *intel_dp, > > { > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > > > - return INTEL_GEN(dev_priv) >= 10 && > > - pipe_config->cpu_transcoder != TRANSCODER_A; > > + /* On TGL, DSC is supported on all Pipes */ > > + if (INTEL_GEN(dev_priv) >= 12) > > + return true; > > + else > > + return (INTEL_GEN(dev_priv) == 10 || > > INTEL_GEN(dev_priv) == 11) && > > Why cant you just use INTEL_GEN(dev_priv) >=10 ? INTEL_GEN(dev_priv) >= 10 was the existing condition. With the new condition added, there would be an overlapping set ie INTEL_GEN(dev_priv) >= 10 would still be TRUE for GEN >= 12. Though this wouldn't affect the logic of the code, thought it would make more sense to sperate it out this way. > > Manasi > > > + pipe_config->cpu_transcoder != TRANSCODER_A; > > } > > > > static bool intel_dp_supports_dsc(struct intel_dp *intel_dp, > > -- > > 2.17.1 > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL 2019-08-15 18:39 ` Tolakanahalli Pradeep, Madhumitha @ 2019-08-15 18:53 ` Manasi Navare 2019-08-15 19:07 ` Tolakanahalli Pradeep, Madhumitha 0 siblings, 1 reply; 12+ messages in thread From: Manasi Navare @ 2019-08-15 18:53 UTC (permalink / raw) To: Tolakanahalli Pradeep, Madhumitha; +Cc: intel-gfx@lists.freedesktop.org On Thu, Aug 15, 2019 at 11:39:54AM -0700, Tolakanahalli Pradeep, Madhumitha wrote: > On Thu, 2019-08-15 at 11:24 -0700, Manasi Navare wrote: > > On Wed, Aug 14, 2019 at 04:51:17PM -0700, Madhumitha Tolakanahalli > > Pradeep wrote: > > > Removing restriction on Pipe A as TigerLake onwards, all the pipes > > > support DSC. > > > > May be elaborate this commit message a little bit something like: > > "On previous platforms, DSC was not supported on Pipe A while > > starting TGL, its is supported > > on all pipes. So remove the DSC and FEC restriction on Pipe A for TGL > > onwards. > > > > Alright, will update that for rev2. > > > > > > > Cc: Manasi Navare <manasi.d.navare@intel.com> > > > Signed-off-by: Madhumitha Tolakanahalli Pradeep < > > > madhumitha.tolakanahalli.pradeep@intel.com> > > > --- > > > drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++++++++---- > > > 1 file changed, 12 insertions(+), 4 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > > b/drivers/gpu/drm/i915/display/intel_dp.c > > > index 4884c87c8ed7..a5b50f93fac5 100644 > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > @@ -1739,8 +1739,12 @@ static bool > > > intel_dp_source_supports_fec(struct intel_dp *intel_dp, > > > { > > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > > > > > - return INTEL_GEN(dev_priv) >= 11 && > > > - pipe_config->cpu_transcoder != TRANSCODER_A; > > > + /* On TGL, DSC is supported on all Pipes */ > > > > ^^^^ FEC supported on all pipes > > Oops, will change this. > > > > + if (INTEL_GEN(dev_priv) >= 12) > > > + return true; > > > + else > > > + return INTEL_GEN(dev_priv) == 11 && Also here I think its better to use IS_GEN(dev_priv, 11) > > > + pipe_config->cpu_transcoder != TRANSCODER_A; > > > } > > > > > > static bool intel_dp_supports_fec(struct intel_dp *intel_dp, > > > @@ -1755,8 +1759,12 @@ static bool > > > intel_dp_source_supports_dsc(struct intel_dp *intel_dp, > > > { > > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > > > > > - return INTEL_GEN(dev_priv) >= 10 && > > > - pipe_config->cpu_transcoder != TRANSCODER_A; > > > + /* On TGL, DSC is supported on all Pipes */ > > > + if (INTEL_GEN(dev_priv) >= 12) > > > + return true; > > > + else > > > + return (INTEL_GEN(dev_priv) == 10 || > > > INTEL_GEN(dev_priv) == 11) && > > > > Why cant you just use INTEL_GEN(dev_priv) >=10 ? > > INTEL_GEN(dev_priv) >= 10 was the existing condition. With the new > condition added, there would be an overlapping set > ie INTEL_GEN(dev_priv) >= 10 would still be TRUE for GEN >= 12. Though > this wouldn't affect the logic of the code, thought it would make more > sense to sperate it out this way. But since we return for GEN >=12 , the only time it would fall to GEN >=10 is for 10 and 11 so that should work, or you could use IS_GEN(dev_priv, 10) || IS_GEN(dev_priv, 11) But may be check with Lucas on what would be the preferred way Manasi > > > > > Manasi > > > > > + pipe_config->cpu_transcoder != TRANSCODER_A; > > > } > > > > > > static bool intel_dp_supports_dsc(struct intel_dp *intel_dp, > > > -- > > > 2.17.1 > > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL 2019-08-15 18:53 ` Manasi Navare @ 2019-08-15 19:07 ` Tolakanahalli Pradeep, Madhumitha 0 siblings, 0 replies; 12+ messages in thread From: Tolakanahalli Pradeep, Madhumitha @ 2019-08-15 19:07 UTC (permalink / raw) To: De Marchi, Lucas, Navare, Manasi D; +Cc: intel-gfx@lists.freedesktop.org On Thu, 2019-08-15 at 11:53 -0700, Manasi Navare wrote: > On Thu, Aug 15, 2019 at 11:39:54AM -0700, Tolakanahalli Pradeep, > Madhumitha wrote: > > On Thu, 2019-08-15 at 11:24 -0700, Manasi Navare wrote: > > > On Wed, Aug 14, 2019 at 04:51:17PM -0700, Madhumitha > > > Tolakanahalli > > > Pradeep wrote: > > > > Removing restriction on Pipe A as TigerLake onwards, all the > > > > pipes > > > > support DSC. > > > > > > May be elaborate this commit message a little bit something like: > > > "On previous platforms, DSC was not supported on Pipe A while > > > starting TGL, its is supported > > > on all pipes. So remove the DSC and FEC restriction on Pipe A for > > > TGL > > > onwards. > > > > > > > Alright, will update that for rev2. > > > > > > > > > > Cc: Manasi Navare <manasi.d.navare@intel.com> > > > > Signed-off-by: Madhumitha Tolakanahalli Pradeep < > > > > madhumitha.tolakanahalli.pradeep@intel.com> > > > > --- > > > > drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++++++++---- > > > > 1 file changed, 12 insertions(+), 4 deletions(-) > > > > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > > > > b/drivers/gpu/drm/i915/display/intel_dp.c > > > > index 4884c87c8ed7..a5b50f93fac5 100644 > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > > > > @@ -1739,8 +1739,12 @@ static bool > > > > intel_dp_source_supports_fec(struct intel_dp *intel_dp, > > > > { > > > > struct drm_i915_private *dev_priv = > > > > dp_to_i915(intel_dp); > > > > > > > > - return INTEL_GEN(dev_priv) >= 11 && > > > > - pipe_config->cpu_transcoder != TRANSCODER_A; > > > > + /* On TGL, DSC is supported on all Pipes */ > > > > > > ^^^^ FEC supported on all pipes > > > > Oops, will change this. > > > > > > + if (INTEL_GEN(dev_priv) >= 12) > > > > + return true; > > > > + else > > > > + return INTEL_GEN(dev_priv) == 11 && > > Also here I think its better to use IS_GEN(dev_priv, 11) Yes, that does make it clearer, I'll change it for v2. > > > > > + pipe_config->cpu_transcoder != > > > > TRANSCODER_A; > > > > } > > > > > > > > static bool intel_dp_supports_fec(struct intel_dp *intel_dp, > > > > @@ -1755,8 +1759,12 @@ static bool > > > > intel_dp_source_supports_dsc(struct intel_dp *intel_dp, > > > > { > > > > struct drm_i915_private *dev_priv = > > > > dp_to_i915(intel_dp); > > > > > > > > - return INTEL_GEN(dev_priv) >= 10 && > > > > - pipe_config->cpu_transcoder != TRANSCODER_A; > > > > + /* On TGL, DSC is supported on all Pipes */ > > > > + if (INTEL_GEN(dev_priv) >= 12) > > > > + return true; > > > > + else > > > > + return (INTEL_GEN(dev_priv) == 10 || > > > > INTEL_GEN(dev_priv) == 11) && > > > > > > Why cant you just use INTEL_GEN(dev_priv) >=10 ? > > > > INTEL_GEN(dev_priv) >= 10 was the existing condition. With the new > > condition added, there would be an overlapping set > > ie INTEL_GEN(dev_priv) >= 10 would still be TRUE for GEN >= 12. > > Though > > this wouldn't affect the logic of the code, thought it would make > > more > > sense to sperate it out this way. > > But since we return for GEN >=12 , the only time it would fall to GEN > >=10 is for 10 and 11 > so that should work, or you could use IS_GEN(dev_priv, 10) || > IS_GEN(dev_priv, 11) > > But may be check with Lucas on what would be the preferred way Yeah, it wouldn't affect the logic. I debated about it for a while too. @Lucas, what do you think is the preferred way to implement this? > > Manasi > > > > > > > > Manasi > > > > > > > + pipe_config->cpu_transcoder != > > > > TRANSCODER_A; > > > > } > > > > > > > > static bool intel_dp_supports_dsc(struct intel_dp *intel_dp, > > > > -- > > > > 2.17.1 > > > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL
@ 2019-08-23 0:46 Madhumitha Tolakanahalli Pradeep
2019-08-23 0:59 ` Manasi Navare
` (2 more replies)
0 siblings, 3 replies; 12+ messages in thread
From: Madhumitha Tolakanahalli Pradeep @ 2019-08-23 0:46 UTC (permalink / raw)
To: intel-gfx
DSC was not supported on Pipe A for previous platforms. Tigerlake onwards,
all the pipes support DSC. Hence, the DSC and FEC restriction on
Pipe A needs to be removed.
v2: Changes in the logic around removing the restriction around
Pipe A (Manasi, Lucas)
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 21 +++++++++++++++++----
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4884c87c8ed7..e2c8fe274c84 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1739,8 +1739,14 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- return INTEL_GEN(dev_priv) >= 11 &&
- pipe_config->cpu_transcoder != TRANSCODER_A;
+ /* On TGL, FEC is supported on all Pipes */
+ if (INTEL_GEN(dev_priv) >= 12)
+ return true;
+
+ if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
+ return true;
+
+ return false;
}
static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
@@ -1755,8 +1761,15 @@ static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp,
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- return INTEL_GEN(dev_priv) >= 10 &&
- pipe_config->cpu_transcoder != TRANSCODER_A;
+ /* On TGL, DSC is supported on all Pipes */
+ if (INTEL_GEN(dev_priv) >= 12)
+ return true;
+
+ if (INTEL_GEN(dev_priv) >= 10 &&
+ pipe_config->cpu_transcoder != TRANSCODER_A)
+ return true;
+
+ return false;
}
static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL 2019-08-23 0:46 Madhumitha Tolakanahalli Pradeep @ 2019-08-23 0:59 ` Manasi Navare 2019-08-23 8:50 ` Lucas De Marchi 2019-08-28 20:12 ` Manasi Navare 2 siblings, 0 replies; 12+ messages in thread From: Manasi Navare @ 2019-08-23 0:59 UTC (permalink / raw) To: Madhumitha Tolakanahalli Pradeep; +Cc: intel-gfx On Thu, Aug 22, 2019 at 05:46:55PM -0700, Madhumitha Tolakanahalli Pradeep wrote: > DSC was not supported on Pipe A for previous platforms. Tigerlake onwards, > all the pipes support DSC. Hence, the DSC and FEC restriction on > Pipe A needs to be removed. > > v2: Changes in the logic around removing the restriction around > Pipe A (Manasi, Lucas) > > Cc: Manasi Navare <manasi.d.navare@intel.com> > Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com> Looks good to me Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Manasi > --- > drivers/gpu/drm/i915/display/intel_dp.c | 21 +++++++++++++++++---- > 1 file changed, 17 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 4884c87c8ed7..e2c8fe274c84 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -1739,8 +1739,14 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp, > { > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > - return INTEL_GEN(dev_priv) >= 11 && > - pipe_config->cpu_transcoder != TRANSCODER_A; > + /* On TGL, FEC is supported on all Pipes */ > + if (INTEL_GEN(dev_priv) >= 12) > + return true; > + > + if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A) > + return true; > + > + return false; > } > > static bool intel_dp_supports_fec(struct intel_dp *intel_dp, > @@ -1755,8 +1761,15 @@ static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp, > { > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > - return INTEL_GEN(dev_priv) >= 10 && > - pipe_config->cpu_transcoder != TRANSCODER_A; > + /* On TGL, DSC is supported on all Pipes */ > + if (INTEL_GEN(dev_priv) >= 12) > + return true; > + > + if (INTEL_GEN(dev_priv) >= 10 && > + pipe_config->cpu_transcoder != TRANSCODER_A) > + return true; > + > + return false; > } > > static bool intel_dp_supports_dsc(struct intel_dp *intel_dp, > -- > 2.17.1 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL 2019-08-23 0:46 Madhumitha Tolakanahalli Pradeep 2019-08-23 0:59 ` Manasi Navare @ 2019-08-23 8:50 ` Lucas De Marchi 2019-08-28 20:12 ` Manasi Navare 2 siblings, 0 replies; 12+ messages in thread From: Lucas De Marchi @ 2019-08-23 8:50 UTC (permalink / raw) To: Madhumitha Tolakanahalli Pradeep; +Cc: Intel Graphics On Thu, Aug 22, 2019 at 5:46 PM Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com> wrote: > > DSC was not supported on Pipe A for previous platforms. Tigerlake onwards, > all the pipes support DSC. Hence, the DSC and FEC restriction on > Pipe A needs to be removed. > > v2: Changes in the logic around removing the restriction around > Pipe A (Manasi, Lucas) > > Cc: Manasi Navare <manasi.d.navare@intel.com> > Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Lucas De Marchi > --- > drivers/gpu/drm/i915/display/intel_dp.c | 21 +++++++++++++++++---- > 1 file changed, 17 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 4884c87c8ed7..e2c8fe274c84 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -1739,8 +1739,14 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp, > { > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > - return INTEL_GEN(dev_priv) >= 11 && > - pipe_config->cpu_transcoder != TRANSCODER_A; > + /* On TGL, FEC is supported on all Pipes */ > + if (INTEL_GEN(dev_priv) >= 12) > + return true; > + > + if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A) > + return true; > + > + return false; > } > > static bool intel_dp_supports_fec(struct intel_dp *intel_dp, > @@ -1755,8 +1761,15 @@ static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp, > { > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > - return INTEL_GEN(dev_priv) >= 10 && > - pipe_config->cpu_transcoder != TRANSCODER_A; > + /* On TGL, DSC is supported on all Pipes */ > + if (INTEL_GEN(dev_priv) >= 12) > + return true; > + > + if (INTEL_GEN(dev_priv) >= 10 && > + pipe_config->cpu_transcoder != TRANSCODER_A) > + return true; > + > + return false; > } > > static bool intel_dp_supports_dsc(struct intel_dp *intel_dp, > -- > 2.17.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Lucas De Marchi _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL 2019-08-23 0:46 Madhumitha Tolakanahalli Pradeep 2019-08-23 0:59 ` Manasi Navare 2019-08-23 8:50 ` Lucas De Marchi @ 2019-08-28 20:12 ` Manasi Navare 2 siblings, 0 replies; 12+ messages in thread From: Manasi Navare @ 2019-08-28 20:12 UTC (permalink / raw) To: Madhumitha Tolakanahalli Pradeep; +Cc: intel-gfx Thanks for the patch and reviews, pushed to dinq Regards Manasi On Thu, Aug 22, 2019 at 05:46:55PM -0700, Madhumitha Tolakanahalli Pradeep wrote: > DSC was not supported on Pipe A for previous platforms. Tigerlake onwards, > all the pipes support DSC. Hence, the DSC and FEC restriction on > Pipe A needs to be removed. > > v2: Changes in the logic around removing the restriction around > Pipe A (Manasi, Lucas) > > Cc: Manasi Navare <manasi.d.navare@intel.com> > Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com> > --- > drivers/gpu/drm/i915/display/intel_dp.c | 21 +++++++++++++++++---- > 1 file changed, 17 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index 4884c87c8ed7..e2c8fe274c84 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -1739,8 +1739,14 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp, > { > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > - return INTEL_GEN(dev_priv) >= 11 && > - pipe_config->cpu_transcoder != TRANSCODER_A; > + /* On TGL, FEC is supported on all Pipes */ > + if (INTEL_GEN(dev_priv) >= 12) > + return true; > + > + if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A) > + return true; > + > + return false; > } > > static bool intel_dp_supports_fec(struct intel_dp *intel_dp, > @@ -1755,8 +1761,15 @@ static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp, > { > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); > > - return INTEL_GEN(dev_priv) >= 10 && > - pipe_config->cpu_transcoder != TRANSCODER_A; > + /* On TGL, DSC is supported on all Pipes */ > + if (INTEL_GEN(dev_priv) >= 12) > + return true; > + > + if (INTEL_GEN(dev_priv) >= 10 && > + pipe_config->cpu_transcoder != TRANSCODER_A) > + return true; > + > + return false; > } > > static bool intel_dp_supports_dsc(struct intel_dp *intel_dp, > -- > 2.17.1 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2019-08-28 20:10 UTC | newest] Thread overview: 12+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2019-08-14 23:51 [PATCH] drm/i915/tgl: Enabling DSC on Pipe A for TGL Madhumitha Tolakanahalli Pradeep 2019-08-15 0:04 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork 2019-08-15 1:05 ` ✓ Fi.CI.BAT: success " Patchwork 2019-08-15 18:01 ` ✓ Fi.CI.IGT: " Patchwork 2019-08-15 18:24 ` [PATCH] " Manasi Navare 2019-08-15 18:39 ` Tolakanahalli Pradeep, Madhumitha 2019-08-15 18:53 ` Manasi Navare 2019-08-15 19:07 ` Tolakanahalli Pradeep, Madhumitha -- strict thread matches above, loose matches on Subject: below -- 2019-08-23 0:46 Madhumitha Tolakanahalli Pradeep 2019-08-23 0:59 ` Manasi Navare 2019-08-23 8:50 ` Lucas De Marchi 2019-08-28 20:12 ` Manasi Navare
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