* Re: [PATCH] drm/i915/gen11: Add Wa_1604278689:icl,ehl
2019-08-15 21:58 [PATCH] drm/i915/gen11: Add Wa_1604278689:icl,ehl Matt Roper
@ 2019-08-15 22:19 ` Chris Wilson
2019-08-15 22:24 ` Matt Roper
2019-08-15 23:52 ` ✗ Fi.CI.BAT: failure for " Patchwork
` (3 subsequent siblings)
4 siblings, 1 reply; 12+ messages in thread
From: Chris Wilson @ 2019-08-15 22:19 UTC (permalink / raw)
To: Matt Roper, intel-gfx
Quoting Matt Roper (2019-08-15 22:58:59)
> From the bspec:
>
> "SW must always program the FBC_RT_BASE_ADDR_REGISTER_* register
> in Render Engine to a reserved value (0xFFFF_FFFF) such that the
> programmed value doesn’t match the render target surface address
> programmed. This would disable render engine from generating
> modify messages to FBC unit in display."
>
> Bspec: 11388
> Bspec: 33451
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 704ace01e7f5..29b50e2c0627 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -567,6 +567,12 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> /* allow headerless messages for preemptible GPGPU context */
> WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE,
> GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
> +
> + /* Wa_1604278689:icl,ehl */
> + wa_write_masked_or(wal, IVB_FBC_RT_BASE_UPPER,
> + 0, /* write-only register; skip validation */
> + 0xFFFFFFFF);
> + wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF);
It's part of the context?
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH] drm/i915/gen11: Add Wa_1604278689:icl,ehl
2019-08-15 22:19 ` Chris Wilson
@ 2019-08-15 22:24 ` Matt Roper
0 siblings, 0 replies; 12+ messages in thread
From: Matt Roper @ 2019-08-15 22:24 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Thu, Aug 15, 2019 at 11:19:36PM +0100, Chris Wilson wrote:
> Quoting Matt Roper (2019-08-15 22:58:59)
> > From the bspec:
> >
> > "SW must always program the FBC_RT_BASE_ADDR_REGISTER_* register
> > in Render Engine to a reserved value (0xFFFF_FFFF) such that the
> > programmed value doesn’t match the render target surface address
> > programmed. This would disable render engine from generating
> > modify messages to FBC unit in display."
> >
> > Bspec: 11388
> > Bspec: 33451
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > 2 files changed, 7 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 704ace01e7f5..29b50e2c0627 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -567,6 +567,12 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > /* allow headerless messages for preemptible GPGPU context */
> > WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE,
> > GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
> > +
> > + /* Wa_1604278689:icl,ehl */
> > + wa_write_masked_or(wal, IVB_FBC_RT_BASE_UPPER,
> > + 0, /* write-only register; skip validation */
> > + 0xFFFFFFFF);
> > + wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF);
>
> It's part of the context?
> -Chris
The register definitions say "This Register is saved and restored as
part of Context" so I think so? But that does seem to be different than
how we used to program this register back before commit b339088d8
("drm/i915: Don't write IVB_FBC_RT_BASE") so maybe I'm misinterpreting?
Matt
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915/gen11: Add Wa_1604278689:icl,ehl
2019-08-15 21:58 [PATCH] drm/i915/gen11: Add Wa_1604278689:icl,ehl Matt Roper
2019-08-15 22:19 ` Chris Wilson
@ 2019-08-15 23:52 ` Patchwork
2019-08-16 7:07 ` Chris Wilson
2019-08-19 16:13 ` [PATCH] " Ville Syrjälä
` (2 subsequent siblings)
4 siblings, 1 reply; 12+ messages in thread
From: Patchwork @ 2019-08-15 23:52 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gen11: Add Wa_1604278689:icl,ehl
URL : https://patchwork.freedesktop.org/series/65276/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6714 -> Patchwork_14040
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_14040 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14040, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14040/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14040:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14040/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_hangcheck:
- {fi-icl-dsi}: [PASS][3] -> [DMESG-FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14040/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
- {fi-icl-u4}: [PASS][5] -> [DMESG-FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14040/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
Known issues
------------
Here are the changes found in Patchwork_14040 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_create@basic-files:
- fi-icl-u2: [PASS][7] -> [INCOMPLETE][8] ([fdo#107713] / [fdo#109100])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/fi-icl-u2/igt@gem_ctx_create@basic-files.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14040/fi-icl-u2/igt@gem_ctx_create@basic-files.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-apl-guc: [PASS][9] -> [DMESG-WARN][10] ([fdo#108566])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/fi-apl-guc/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14040/fi-apl-guc/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@prime_vgem@basic-fence-mmap:
- fi-icl-u3: [PASS][11] -> [DMESG-WARN][12] ([fdo#107724])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/fi-icl-u3/igt@prime_vgem@basic-fence-mmap.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14040/fi-icl-u3/igt@prime_vgem@basic-fence-mmap.html
#### Possible fixes ####
* igt@gem_mmap_gtt@basic-small-bo-tiledx:
- fi-icl-u3: [DMESG-WARN][13] ([fdo#107724]) -> [PASS][14] +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/fi-icl-u3/igt@gem_mmap_gtt@basic-small-bo-tiledx.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14040/fi-icl-u3/igt@gem_mmap_gtt@basic-small-bo-tiledx.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-blb-e6850: [INCOMPLETE][15] ([fdo#107718]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/fi-blb-e6850/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14040/fi-blb-e6850/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
Participating hosts (52 -> 44)
------------------------------
Missing (8): fi-kbl-soraka fi-bxt-dsi fi-byt-squawks fi-bsw-cyan fi-icl-y fi-icl-guc fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6714 -> Patchwork_14040
CI-20190529: 20190529
CI_DRM_6714: 9198974f9fa309c4c74197365844971e0940b227 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5138: b9abe0bf6c478c4f6cac56bff286d6926ad8c0ab @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14040: f2eafc49659d86fe33348fb713ef3ae8c51cf17c @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f2eafc49659d drm/i915/gen11: Add Wa_1604278689:icl,ehl
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14040/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: ✗ Fi.CI.BAT: failure for drm/i915/gen11: Add Wa_1604278689:icl,ehl
2019-08-15 23:52 ` ✗ Fi.CI.BAT: failure for " Patchwork
@ 2019-08-16 7:07 ` Chris Wilson
2019-08-16 16:29 ` Matt Roper
0 siblings, 1 reply; 12+ messages in thread
From: Chris Wilson @ 2019-08-16 7:07 UTC (permalink / raw)
To: Matt Roper, Patchwork; +Cc: intel-gfx
Quoting Patchwork (2019-08-16 00:52:20)
> #### Possible regressions ####
>
> * igt@i915_selftest@live_hangcheck:
> - fi-icl-u3: [PASS][1] -> [DMESG-FAIL][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14040/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
> - {fi-icl-dsi}: [PASS][3] -> [DMESG-FAIL][4]
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14040/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
> - {fi-icl-u4}: [PASS][5] -> [DMESG-FAIL][6]
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14040/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
All icl machines suffering a similar failure to reset an engine (not
rcs!). We haven't seen that before, so it does look very suspicious.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: ✗ Fi.CI.BAT: failure for drm/i915/gen11: Add Wa_1604278689:icl,ehl
2019-08-16 7:07 ` Chris Wilson
@ 2019-08-16 16:29 ` Matt Roper
2019-08-16 16:38 ` Chris Wilson
0 siblings, 1 reply; 12+ messages in thread
From: Matt Roper @ 2019-08-16 16:29 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Fri, Aug 16, 2019 at 08:07:18AM +0100, Chris Wilson wrote:
> Quoting Patchwork (2019-08-16 00:52:20)
> > #### Possible regressions ####
> >
> > * igt@i915_selftest@live_hangcheck:
> > - fi-icl-u3: [PASS][1] -> [DMESG-FAIL][2]
> > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
> > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14040/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
> > - {fi-icl-dsi}: [PASS][3] -> [DMESG-FAIL][4]
> > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
> > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14040/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
> > - {fi-icl-u4}: [PASS][5] -> [DMESG-FAIL][6]
> > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
> > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14040/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
>
> All icl machines suffering a similar failure to reset an engine (not
> rcs!). We haven't seen that before, so it does look very suspicious.
> -Chris
Hmm. So for a render engine register that's saved/restored as part of
the context, is there somewhere else I should be setting this value? My
understanding was that the items added in *_ctx_workarounds_init only
applied to the render engine (since __intel_engine_init_ctx_wa bails out
for other engine classes), yet it seems it's the BCS engine that's
failing to reset with this patch?. If I just I915_WRITE to this
register, won't the value only apply to whichever context is currently
executing on the RCS engine and be lost when other contexts switch in?
Matt
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: ✗ Fi.CI.BAT: failure for drm/i915/gen11: Add Wa_1604278689:icl,ehl
2019-08-16 16:29 ` Matt Roper
@ 2019-08-16 16:38 ` Chris Wilson
0 siblings, 0 replies; 12+ messages in thread
From: Chris Wilson @ 2019-08-16 16:38 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
Quoting Matt Roper (2019-08-16 17:29:09)
> On Fri, Aug 16, 2019 at 08:07:18AM +0100, Chris Wilson wrote:
> > Quoting Patchwork (2019-08-16 00:52:20)
> > > #### Possible regressions ####
> > >
> > > * igt@i915_selftest@live_hangcheck:
> > > - fi-icl-u3: [PASS][1] -> [DMESG-FAIL][2]
> > > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
> > > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14040/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
> > > - {fi-icl-dsi}: [PASS][3] -> [DMESG-FAIL][4]
> > > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
> > > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14040/fi-icl-dsi/igt@i915_selftest@live_hangcheck.html
> > > - {fi-icl-u4}: [PASS][5] -> [DMESG-FAIL][6]
> > > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
> > > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14040/fi-icl-u4/igt@i915_selftest@live_hangcheck.html
> >
> > All icl machines suffering a similar failure to reset an engine (not
> > rcs!). We haven't seen that before, so it does look very suspicious.
> > -Chris
>
> Hmm. So for a render engine register that's saved/restored as part of
> the context, is there somewhere else I should be setting this value? My
> understanding was that the items added in *_ctx_workarounds_init only
> applied to the render engine (since __intel_engine_init_ctx_wa bails out
> for other engine classes), yet it seems it's the BCS engine that's
> failing to reset with this patch?. If I just I915_WRITE to this
> register, won't the value only apply to whichever context is currently
> executing on the RCS engine and be lost when other contexts switch in?
The magic is in the ordering. If you put it in the gt_workarounds, it
gets applied before we record the default context image -- and so it
gets copied into all subsequent contexts.
The only reason why we still have ctx_workarounds is that some registers
had to be written via CS, and it's easy for us to apply the rule "if the
spec says it is a context register, put it in the ctx_workarounds". We
also use that to determine whether to use a SRM or mmio verification.
At the end of the day, whatever works :)
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH] drm/i915/gen11: Add Wa_1604278689:icl,ehl
2019-08-15 21:58 [PATCH] drm/i915/gen11: Add Wa_1604278689:icl,ehl Matt Roper
2019-08-15 22:19 ` Chris Wilson
2019-08-15 23:52 ` ✗ Fi.CI.BAT: failure for " Patchwork
@ 2019-08-19 16:13 ` Ville Syrjälä
2019-08-19 16:46 ` Matt Roper
2019-08-19 20:48 ` ✓ Fi.CI.BAT: success for drm/i915/gen11: Add Wa_1604278689:icl,ehl (rev2) Patchwork
2019-08-20 5:06 ` ✓ Fi.CI.IGT: " Patchwork
4 siblings, 1 reply; 12+ messages in thread
From: Ville Syrjälä @ 2019-08-19 16:13 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
On Thu, Aug 15, 2019 at 02:58:59PM -0700, Matt Roper wrote:
> From the bspec:
>
> "SW must always program the FBC_RT_BASE_ADDR_REGISTER_* register
> in Render Engine to a reserved value (0xFFFF_FFFF) such that the
> programmed value doesn’t match the render target surface address
> programmed. This would disable render engine from generating
> modify messages to FBC unit in display."
This looks a bit peculiar. That magic value seems to imply that the
RT_VALID bit no longer functions as intended. I filed a spec issue to
get some clarification on this.
>
> Bspec: 11388
> Bspec: 33451
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 704ace01e7f5..29b50e2c0627 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -567,6 +567,12 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> /* allow headerless messages for preemptible GPGPU context */
> WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE,
> GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
> +
> + /* Wa_1604278689:icl,ehl */
> + wa_write_masked_or(wal, IVB_FBC_RT_BASE_UPPER,
> + 0, /* write-only register; skip validation */
> + 0xFFFFFFFF);
> + wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF);
> }
>
> static void
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index def6dbdc7e2e..14af1b1dc0d3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3214,6 +3214,7 @@ enum i915_power_well_id {
>
> /* Framebuffer compression for Ivybridge */
> #define IVB_FBC_RT_BASE _MMIO(0x7020)
> +#define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024)
That register seems to be BDW+ actually.
>
> #define IPS_CTL _MMIO(0x43408)
> #define IPS_ENABLE (1 << 31)
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH] drm/i915/gen11: Add Wa_1604278689:icl,ehl
2019-08-19 16:13 ` [PATCH] " Ville Syrjälä
@ 2019-08-19 16:46 ` Matt Roper
2019-08-19 18:08 ` [PATCH v2] " Matt Roper
0 siblings, 1 reply; 12+ messages in thread
From: Matt Roper @ 2019-08-19 16:46 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, Aug 19, 2019 at 07:13:56PM +0300, Ville Syrjälä wrote:
> On Thu, Aug 15, 2019 at 02:58:59PM -0700, Matt Roper wrote:
> > From the bspec:
> >
> > "SW must always program the FBC_RT_BASE_ADDR_REGISTER_* register
> > in Render Engine to a reserved value (0xFFFF_FFFF) such that the
> > programmed value doesn’t match the render target surface address
> > programmed. This would disable render engine from generating
> > modify messages to FBC unit in display."
>
> This looks a bit peculiar. That magic value seems to imply that the
> RT_VALID bit no longer functions as intended. I filed a spec issue to
> get some clarification on this.
Yeah, this worried me as well, although I figured their logic was that
turning on the 'valid' bit was okay as long as the address comparisons
always returned a mismatch. However CI starts failing with this
workaround applied, and experimentation with trybot indicates that
the failures go away when I add a "& ~RT_VALID" to the RT_BASE register
value. I'll submit an updated version that turns that bit off in a bit.
Matt
>
> >
> > Bspec: 11388
> > Bspec: 33451
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > 2 files changed, 7 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 704ace01e7f5..29b50e2c0627 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -567,6 +567,12 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > /* allow headerless messages for preemptible GPGPU context */
> > WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE,
> > GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
> > +
> > + /* Wa_1604278689:icl,ehl */
> > + wa_write_masked_or(wal, IVB_FBC_RT_BASE_UPPER,
> > + 0, /* write-only register; skip validation */
> > + 0xFFFFFFFF);
> > + wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF);
> > }
> >
> > static void
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index def6dbdc7e2e..14af1b1dc0d3 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3214,6 +3214,7 @@ enum i915_power_well_id {
> >
> > /* Framebuffer compression for Ivybridge */
> > #define IVB_FBC_RT_BASE _MMIO(0x7020)
> > +#define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024)
>
> That register seems to be BDW+ actually.
>
> >
> > #define IPS_CTL _MMIO(0x43408)
> > #define IPS_ENABLE (1 << 31)
> > --
> > 2.20.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Ville Syrjälä
> Intel
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v2] drm/i915/gen11: Add Wa_1604278689:icl,ehl
2019-08-19 16:46 ` Matt Roper
@ 2019-08-19 18:08 ` Matt Roper
0 siblings, 0 replies; 12+ messages in thread
From: Matt Roper @ 2019-08-19 18:08 UTC (permalink / raw)
To: intel-gfx
From the bspec:
"SW must always program the FBC_RT_BASE_ADDR_REGISTER_* register
in Render Engine to a reserved value (0xFFFF_FFFF) such that the
programmed value doesn’t match the render target surface address
programmed. This would disable render engine from generating
modify messages to FBC unit in display."
This workaround seems a bit questionable as written since using all 1's
to the RT_BASE register implies setting bit 0, which is a flag to
indicate whether the address is valid. Indeed, we start seeing CI
failures when we follow the directions here literally. Let's slightly
deviate from the workaround instructions and set all bits _except_ for
bit 0 of FBC_RT_BASE_ADDR_REGISTER.
v2:
- Mask off the RT_VALID bit. Experimentation with CI trybot indicates
that this is necessary to avoid reset failures on BCS.
Bspec: 11388
Bspec: 33451
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 704ace01e7f5..f70b7a95bc23 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -567,6 +567,12 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
/* allow headerless messages for preemptible GPGPU context */
WA_SET_BIT_MASKED(GEN10_SAMPLER_MODE,
GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
+
+ /* Wa_1604278689:icl,ehl */
+ wa_write_masked_or(wal, IVB_FBC_RT_BASE_UPPER,
+ 0, /* write-only register; skip validation */
+ 0xFFFFFFFF);
+ wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID);
}
static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ea2f0fa2402d..bce7326329db 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3170,6 +3170,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
/* Framebuffer compression for Ivybridge */
#define IVB_FBC_RT_BASE _MMIO(0x7020)
+#define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024)
#define IPS_CTL _MMIO(0x43408)
#define IPS_ENABLE (1 << 31)
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/gen11: Add Wa_1604278689:icl,ehl (rev2)
2019-08-15 21:58 [PATCH] drm/i915/gen11: Add Wa_1604278689:icl,ehl Matt Roper
` (2 preceding siblings ...)
2019-08-19 16:13 ` [PATCH] " Ville Syrjälä
@ 2019-08-19 20:48 ` Patchwork
2019-08-20 5:06 ` ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-08-19 20:48 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gen11: Add Wa_1604278689:icl,ehl (rev2)
URL : https://patchwork.freedesktop.org/series/65276/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6741 -> Patchwork_14085
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/
Known issues
------------
Here are the changes found in Patchwork_14085 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_flink_basic@basic:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/fi-icl-u3/igt@gem_flink_basic@basic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/fi-icl-u3/igt@gem_flink_basic@basic.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cml-u2: [PASS][3] -> [FAIL][4] ([fdo#110627])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/fi-cml-u2/igt@kms_chamelium@dp-crc-fast.html
#### Possible fixes ####
* igt@gem_busy@busy-all:
- fi-icl-u3: [DMESG-WARN][5] ([fdo#107724]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/fi-icl-u3/igt@gem_busy@busy-all.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/fi-icl-u3/igt@gem_busy@busy-all.html
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [INCOMPLETE][7] ([fdo#107718]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
* igt@gem_sync@basic-store-each:
- fi-cfl-8109u: [INCOMPLETE][9] ([fdo#111427]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/fi-cfl-8109u/igt@gem_sync@basic-store-each.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/fi-cfl-8109u/igt@gem_sync@basic-store-each.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#110627]: https://bugs.freedesktop.org/show_bug.cgi?id=110627
[fdo#111427]: https://bugs.freedesktop.org/show_bug.cgi?id=111427
Participating hosts (55 -> 47)
------------------------------
Missing (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6741 -> Patchwork_14085
CI-20190529: 20190529
CI_DRM_6741: 0db9333be821acadbf8c476e13b160522d252d77 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5141: 7102b417fedc2a1ea6f72d768a9f1bd100a34f13 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14085: b0af8ca23655a98a92c45e7e65369994b42c0185 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b0af8ca23655 drm/i915/gen11: Add Wa_1604278689:icl,ehl
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread* ✓ Fi.CI.IGT: success for drm/i915/gen11: Add Wa_1604278689:icl,ehl (rev2)
2019-08-15 21:58 [PATCH] drm/i915/gen11: Add Wa_1604278689:icl,ehl Matt Roper
` (3 preceding siblings ...)
2019-08-19 20:48 ` ✓ Fi.CI.BAT: success for drm/i915/gen11: Add Wa_1604278689:icl,ehl (rev2) Patchwork
@ 2019-08-20 5:06 ` Patchwork
4 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2019-08-20 5:06 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gen11: Add Wa_1604278689:icl,ehl (rev2)
URL : https://patchwork.freedesktop.org/series/65276/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6741_full -> Patchwork_14085_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_14085_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@drm_read@empty-block:
- shard-snb: [PASS][1] -> [SKIP][2] ([fdo#109271])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-snb4/igt@drm_read@empty-block.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/shard-snb7/igt@drm_read@empty-block.html
* igt@gem_exec_schedule@out-order-bsd2:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276]) +14 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb4/igt@gem_exec_schedule@out-order-bsd2.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/shard-iclb8/igt@gem_exec_schedule@out-order-bsd2.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#111325]) +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb7/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/shard-iclb1/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@kms_cursor_edge_walk@pipe-a-128x128-left-edge:
- shard-snb: [PASS][7] -> [SKIP][8] ([fdo#109271] / [fdo#109278])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-snb4/igt@kms_cursor_edge_walk@pipe-a-128x128-left-edge.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/shard-snb7/igt@kms_cursor_edge_walk@pipe-a-128x128-left-edge.html
* igt@kms_flip@bo-too-big-interruptible:
- shard-apl: [PASS][9] -> [INCOMPLETE][10] ([fdo#103927]) +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-apl4/igt@kms_flip@bo-too-big-interruptible.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/shard-apl2/igt@kms_flip@bo-too-big-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-skl: [PASS][11] -> [INCOMPLETE][12] ([fdo#109507])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl3/igt@kms_flip@flip-vs-suspend-interruptible.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/shard-skl1/igt@kms_flip@flip-vs-suspend-interruptible.html
- shard-snb: [PASS][13] -> [DMESG-WARN][14] ([fdo#102365])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-snb2/igt@kms_flip@flip-vs-suspend-interruptible.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/shard-snb4/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip_tiling@flip-to-x-tiled:
- shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108134])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl4/igt@kms_flip_tiling@flip-to-x-tiled.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/shard-skl7/igt@kms_flip_tiling@flip-to-x-tiled.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [PASS][17] -> [DMESG-WARN][18] ([fdo#108566]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-apl2/igt@kms_frontbuffer_tracking@fbc-suspend.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/shard-apl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
- shard-iclb: [PASS][19] -> [FAIL][20] ([fdo#103167])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/shard-iclb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-iclb: [PASS][21] -> [INCOMPLETE][22] ([fdo#106978] / [fdo#107713])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/shard-iclb7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][23] -> [FAIL][24] ([fdo#108145])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
#### Possible fixes ####
* igt@gem_mmap_gtt@forked-big-copy:
- shard-apl: [INCOMPLETE][25] ([fdo#103927]) -> [PASS][26] +2 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-apl4/igt@gem_mmap_gtt@forked-big-copy.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/shard-apl4/igt@gem_mmap_gtt@forked-big-copy.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [DMESG-WARN][27] ([fdo#108566]) -> [PASS][28] +3 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-apl3/igt@i915_suspend@sysfs-reader.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/shard-apl5/igt@i915_suspend@sysfs-reader.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
- shard-hsw: [FAIL][29] ([fdo#103355]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/shard-hsw1/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-skl: [FAIL][31] ([fdo#102670]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt:
- shard-iclb: [FAIL][33] ([fdo#103167]) -> [PASS][34] +2 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-skl: [INCOMPLETE][35] ([fdo#104108]) -> [PASS][36] +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/shard-skl8/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][37] ([fdo#108145] / [fdo#110403]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-iclb: [SKIP][39] ([fdo#109441]) -> [PASS][40] +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb8/igt@kms_psr@psr2_cursor_plane_onoff.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html
* igt@perf@blocking:
- shard-skl: [FAIL][41] ([fdo#110728]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-skl5/igt@perf@blocking.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/shard-skl1/igt@perf@blocking.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [SKIP][43] ([fdo#109276]) -> [PASS][44] +11 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-iclb7/igt@prime_busy@hang-bsd2.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/shard-iclb1/igt@prime_busy@hang-bsd2.html
#### Warnings ####
* igt@kms_vblank@pipe-c-query-forked:
- shard-snb: [SKIP][45] ([fdo#109271] / [fdo#109278]) -> [SKIP][46] ([fdo#109271])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6741/shard-snb4/igt@kms_vblank@pipe-c-query-forked.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/shard-snb7/igt@kms_vblank@pipe-c-query-forked.html
[fdo#102365]: https://bugs.freedesktop.org/show_bug.cgi?id=102365
[fdo#102670]: https://bugs.freedesktop.org/show_bug.cgi?id=102670
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#106978]: https://bugs.freedesktop.org/show_bug.cgi?id=106978
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108134]: https://bugs.freedesktop.org/show_bug.cgi?id=108134
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6741 -> Patchwork_14085
CI-20190529: 20190529
CI_DRM_6741: 0db9333be821acadbf8c476e13b160522d252d77 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5141: 7102b417fedc2a1ea6f72d768a9f1bd100a34f13 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14085: b0af8ca23655a98a92c45e7e65369994b42c0185 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14085/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread