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From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Nanley G Chery <nanley.g.chery@intel.com>,
	Lucas De Marchi <lucas.demarchi@intel.com>,
	Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Subject: [RFC v3 1/9] drm/framebuffer: Format modifier for Intel Gen-12 render compression
Date: Mon, 23 Sep 2019 03:29:27 -0700	[thread overview]
Message-ID: <20190923102935.5860-2-dhinakaran.pandiyan@intel.com> (raw)
In-Reply-To: <20190923102935.5860-1-dhinakaran.pandiyan@intel.com>

Gen-12 has a new compression format, add a new modifier to indicate that.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Nanley G Chery <nanley.g.chery@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 include/uapi/drm/drm_fourcc.h | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 3feeaa3f987a..1f0fbf0398f6 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -410,6 +410,17 @@ extern "C" {
 #define I915_FORMAT_MOD_Y_TILED_CCS	fourcc_mod_code(INTEL, 4)
 #define I915_FORMAT_MOD_Yf_TILED_CCS	fourcc_mod_code(INTEL, 5)
 
+/*
+ * Intel color control surfaces (CCS) for Gen-12 render compression.
+ *
+ * The main surface is Y-tiled and at plane index 0, the CCS is linear and
+ * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
+ * main surface. In other words, 4 bits in CCS map to a main surface cache
+ * line pair. The main surface pitch is required to be a multiple of four
+ * Y-tile widths.
+ */
+#define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.17.1

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  reply	other threads:[~2019-09-23 10:30 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-23 10:29 [RFC v3 0/9] Gen12 E2E compression Dhinakaran Pandiyan
2019-09-23 10:29 ` Dhinakaran Pandiyan [this message]
2019-09-23 10:29 ` [RFC v3 2/9] drm/i915: Use intel_tile_height() instead of re-implementing Dhinakaran Pandiyan
2019-10-02 22:29   ` Matt Roper
2019-09-23 10:29 ` [RFC v3 3/9] drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment Dhinakaran Pandiyan
2019-10-02 22:29   ` Matt Roper
2019-10-03 21:29     ` Pandiyan, Dhinakaran
2019-09-23 10:29 ` [RFC v3 4/9] drm/i915/tgl: Gen-12 render decompression Dhinakaran Pandiyan
2019-10-02 22:32   ` Matt Roper
2019-10-03 12:00     ` Ville Syrjälä
2019-09-23 10:29 ` [RFC v3 5/9] drm/i915: Extract framebufer CCS offset checks into a function Dhinakaran Pandiyan
2019-10-04 15:10   ` Ville Syrjälä
2019-10-04 20:33   ` Matt Roper
2019-09-23 10:29 ` [RFC v3 6/9] drm/framebuffer: Format modifier for Intel Gen-12 media compression Dhinakaran Pandiyan
2019-09-26  6:42   ` Pandiyan, Dhinakaran
2019-09-23 10:29 ` [RFC v3 7/9] drm/i915: Skip rotated offset adjustment for unsupported modifiers Dhinakaran Pandiyan
2019-10-03 21:18   ` Dhinakaran Pandiyan
2019-09-23 10:29 ` [RFC v3 8/9] drm/fb: Extend format_info member arrays to handle four planes Dhinakaran Pandiyan
2019-09-23 10:29 ` [RFC v3 9/9] Gen-12 display can decompress surfaces compressed by the media engine Dhinakaran Pandiyan
2019-09-26 10:55   ` [PATCH v4 " Dhinakaran Pandiyan
2019-10-04 15:36     ` Ville Syrjälä
2019-10-04 23:54       ` Dhinakaran Pandiyan
2019-10-04 20:27     ` Matt Roper
2019-10-04 23:20       ` Dhinakaran Pandiyan
2019-09-23 13:53 ` ✗ Fi.CI.CHECKPATCH: warning for Gen12 E2E compression Patchwork
2019-09-23 14:16 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-09-26 11:01 ` ✗ Fi.CI.CHECKPATCH: warning for Gen12 E2E compression (rev2) Patchwork
2019-09-26 11:25 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-10-10 10:14 ` ✗ Fi.CI.CHECKPATCH: warning for Gen12 E2E compression (rev3) Patchwork
2019-10-10 10:39 ` ✗ Fi.CI.BAT: failure " Patchwork

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