Re: [RFC v3 4/9] drm/i915/tgl: Gen-12 render decompression

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Wed, Oct 02, 2019 at 03:32:41PM -0700, Matt Roper wrote:
> On Mon, Sep 23, 2019 at 03:29:30AM -0700, Dhinakaran Pandiyan wrote:
> > Gen-12 display decompression operates on Y-tiled compressed main surface.
> > The CCS is linear
> 
> I'd mention in the commit message that we opt to to treat the
> CCS as if it were a bunch of 64x1 tiles.
> 
> There are a handful of cosmetic changes suggested below, but otherwise,
> 
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> 
> > and has 4 bits of metadata for each main surface cache
> > line pair, a size ratio of 1:256. Gen-12 display decompression is
> > incompatible with buffers compressed by earlier GPUs, so make use of a new
> > modifier to identify gen-12 compression. Another notable change is that
> > render decompression is supported on all planes except cursor and on all
> > pipes. Start by adding render decompression support for [A,X]BGR888 pixel
> > formats.
> > 
> > v2: Fix checkpatch warnings (Lucas)
> > v3:
> > Rebase, disable color clear, styling changes and modify
> > intel_tile_width_bytes and intel_tile_height to handle linear CCS
> > 
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Nanley G Chery <nanley.g.chery@intel.com>
> > Cc: Jason Ekstrand <jason@jlekstrand.net>
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 85 ++++++++++++++++----
> >  drivers/gpu/drm/i915/display/intel_sprite.c  | 23 ++++--
> >  drivers/gpu/drm/i915/i915_reg.h              |  1 +
> >  3 files changed, 84 insertions(+), 25 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index c437f00c2072..6fec43cdddf4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1911,6 +1911,10 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> >  		if (color_plane == 1)
> >  			return 128;
> >  		/* fall through */
> > +	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> > +		if (color_plane == 1)
> > +			return 64;
> > +		/* fall through */

I don't remember off hand if we even need this thing here. Maybe we can
just let it go the same path as normal linear stuff?

-- 
Ville Syrjälä
Intel
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