* [PATCH v9 1/7] drm/i915/tgl: Add DC3CO required register and bits
2019-09-25 18:10 [PATCH v9 0/7] DC3CO Support for TGL Anshuman Gupta
@ 2019-09-25 18:10 ` Anshuman Gupta
2019-09-25 18:10 ` [PATCH v9 2/7] drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask Anshuman Gupta
` (10 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Anshuman Gupta @ 2019-09-25 18:10 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
DC3CO enable bit will be used by driver to make DC3CO
ready for DMC f/w and status bit will be used as DC3CO
entry status.
2. Transcoder EXITLINE register and its bit fields and mask.
Transcoder EXITLINE enable bit represents PSR2 idle frame
reset should be applied at exit line and exitlines mask
represent required number of scanlines at which DC3CO
exit happens.
B.Specs:49196
v1: Use of REG_BIT and using extra space for EXITLINE_ macro
definition. [Animesh]
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf37ecebc82f..6bfebab9a441 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4138,6 +4138,7 @@ enum {
#define _VTOTAL_A 0x6000c
#define _VBLANK_A 0x60010
#define _VSYNC_A 0x60014
+#define _EXITLINE_A 0x60018
#define _PIPEASRC 0x6001c
#define _BCLRPAT_A 0x60020
#define _VSYNCSHIFT_A 0x60028
@@ -4184,11 +4185,16 @@ enum {
#define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A)
#define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A)
#define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A)
+#define EXITLINE(trans) _MMIO_TRANS2(trans, _EXITLINE_A)
#define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A)
#define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
#define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
#define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
+#define EXITLINE_ENABLE REG_BIT(31)
+#define EXITLINE_MASK REG_GENMASK(12, 0)
+#define EXITLINE_SHIFT 0
+
/*
* HSW+ eDP PSR registers
*
@@ -10118,6 +10124,8 @@ enum skl_power_gate {
/* GEN9 DC */
#define DC_STATE_EN _MMIO(0x45504)
#define DC_STATE_DISABLE 0
+#define DC_STATE_EN_DC3CO REG_BIT(30)
+#define DC_STATE_DC3CO_STATUS REG_BIT(29)
#define DC_STATE_EN_UPTO_DC5 (1 << 0)
#define DC_STATE_EN_DC9 (1 << 3)
#define DC_STATE_EN_UPTO_DC6 (2 << 0)
--
2.21.0
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^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v9 2/7] drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
2019-09-25 18:10 [PATCH v9 0/7] DC3CO Support for TGL Anshuman Gupta
2019-09-25 18:10 ` [PATCH v9 1/7] drm/i915/tgl: Add DC3CO required register and bits Anshuman Gupta
@ 2019-09-25 18:10 ` Anshuman Gupta
2019-09-25 18:10 ` [PATCH v9 3/7] drm/i915/tgl: Enable DC3CO state in "DC Off" power well Anshuman Gupta
` (9 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Anshuman Gupta @ 2019-09-25 18:10 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Enable dc3co state in enable_dc module param and add dc3co
enable mask to allowed_dc_mask and gen9_dc_mask.
v1: Adding enable_dc=3,4 options to enable DC3CO with DC5 and DC6
independently. [Animesh]
v2: Using a switch statement for cleaner code. [Animesh]
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
.../drm/i915/display/intel_display_power.c | 29 +++++++++++++++----
drivers/gpu/drm/i915/i915_params.c | 3 +-
2 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index ce88a27229ef..24cd9320ad4c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -698,7 +698,11 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
u32 mask;
mask = DC_STATE_EN_UPTO_DC5;
- if (INTEL_GEN(dev_priv) >= 11)
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
+ | DC_STATE_EN_DC9;
+ else if (IS_GEN(dev_priv, 11))
mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
else if (IS_GEN9_LP(dev_priv))
mask |= DC_STATE_EN_DC9;
@@ -3927,14 +3931,17 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
int requested_dc;
int max_dc;
- if (INTEL_GEN(dev_priv) >= 11) {
- max_dc = 2;
+ if (INTEL_GEN(dev_priv) >= 12) {
+ max_dc = 4;
/*
* DC9 has a separate HW flow from the rest of the DC states,
* not depending on the DMC firmware. It's needed by system
* suspend/resume, so allow it unconditionally.
*/
mask = DC_STATE_EN_DC9;
+ } else if (IS_GEN(dev_priv, 11)) {
+ max_dc = 2;
+ mask = DC_STATE_EN_DC9;
} else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv)) {
max_dc = 2;
mask = 0;
@@ -3953,7 +3960,7 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
requested_dc = enable_dc;
} else if (enable_dc == -1) {
requested_dc = max_dc;
- } else if (enable_dc > max_dc && enable_dc <= 2) {
+ } else if (enable_dc > max_dc && enable_dc <= 4) {
DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
enable_dc, max_dc);
requested_dc = max_dc;
@@ -3962,10 +3969,20 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
requested_dc = max_dc;
}
- if (requested_dc > 1)
+ switch (requested_dc) {
+ case 4:
+ mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6;
+ break;
+ case 3:
+ mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5;
+ break;
+ case 2:
mask |= DC_STATE_EN_UPTO_DC6;
- if (requested_dc > 0)
+ break;
+ case 1:
mask |= DC_STATE_EN_UPTO_DC5;
+ break;
+ }
DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask);
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 296452f9efe4..4f1806f65040 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -46,7 +46,8 @@ i915_param_named(modeset, int, 0400,
i915_param_named_unsafe(enable_dc, int, 0400,
"Enable power-saving display C-states. "
- "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6)");
+ "(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6; "
+ "3=up to DC5 with DC3CO; 4=up to DC6 with DC3CO)");
i915_param_named_unsafe(enable_fbc, int, 0600,
"Enable frame buffer compression for power savings "
--
2.21.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v9 3/7] drm/i915/tgl: Enable DC3CO state in "DC Off" power well
2019-09-25 18:10 [PATCH v9 0/7] DC3CO Support for TGL Anshuman Gupta
2019-09-25 18:10 ` [PATCH v9 1/7] drm/i915/tgl: Add DC3CO required register and bits Anshuman Gupta
2019-09-25 18:10 ` [PATCH v9 2/7] drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask Anshuman Gupta
@ 2019-09-25 18:10 ` Anshuman Gupta
2019-09-26 3:56 ` Anshuman Gupta
2019-09-25 18:10 ` [PATCH v9 4/7] drm/i915/tgl: Do modeset to enable and configure DC3CO exitline Anshuman Gupta
` (8 subsequent siblings)
11 siblings, 1 reply; 14+ messages in thread
From: Anshuman Gupta @ 2019-09-25 18:10 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Add target_dc_state and tgl_set_target_dc_state() API
in order to enable DC3CO state with existing DC states.
target_dc_state will enable/disable the desired DC state in
DC_STATE_EN reg when "DC Off" power well gets disable/enable.
v2: commit log improvement.
v3: Used intel_wait_for_register to wait for DC3CO exit. [Imre]
Used gen9_set_dc_state() to allow/disallow DC3CO. [Imre]
Moved transcoder psr2 exit line enablement from tgl_allow_dc3co()
to a appropriate place haswell_crtc_enable(). [Imre]
Changed the DC3CO power well enabled call back logic as
recommended in review comments. [Imre]
v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
v5: using udelay() instead of waiting for DC3CO exit status.
v6: Fixed minor unwanted change.
v7: Removed DC3CO powerwell and POWER_DOMAIN_VIDEO.
v8: Uniform checks by using only target_dc_state instead of allowed_dc_mask
in "DC off" power well callback. [Imre]
Adding "DC off" power well id to older platforms. [Imre]
Removed psr2_deep_sleep flag from tgl_set_target_dc_state. [Imre]
v9: Used switch case for target DC state in gen9_dc_off_power_well_disable().
Checking DC3CO state against allowed DC mask, using WARN_ON()
in tgl_set_target_dc_state(). [Imre]
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
.../drm/i915/display/intel_display_power.c | 110 ++++++++++++++++--
.../drm/i915/display/intel_display_power.h | 2 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
3 files changed, 104 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 24cd9320ad4c..c4a6c7638d92 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -772,6 +772,38 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
dev_priv->csr.dc_state = val & mask;
}
+static void
+allowed_dc_mask_to_target_dc_state(struct drm_i915_private *dev_priv)
+{
+ if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
+ dev_priv->csr.target_dc_state = DC_STATE_EN_UPTO_DC6;
+ else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
+ dev_priv->csr.target_dc_state = DC_STATE_EN_UPTO_DC5;
+ else
+ dev_priv->csr.target_dc_state = DC_STATE_DISABLE;
+}
+
+static void tgl_enable_dc3co(struct drm_i915_private *dev_priv)
+{
+ DRM_DEBUG_KMS("Enabling DC3CO\n");
+ gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
+}
+
+static void tgl_disable_dc3co(struct drm_i915_private *dev_priv)
+{
+ u32 val;
+
+ DRM_DEBUG_KMS("Disabling DC3CO\n");
+ val = I915_READ(DC_STATE_EN);
+ val &= ~DC_STATE_DC3CO_STATUS;
+ I915_WRITE(DC_STATE_EN, val);
+ gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ /*
+ * Delay of 200us DC3CO Exit time B.Spec 49196
+ */
+ udelay(200);
+}
+
static void bxt_enable_dc9(struct drm_i915_private *dev_priv)
{
assert_can_enable_dc9(dev_priv);
@@ -939,7 +971,8 @@ static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
+ return ((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
+ (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
}
static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
@@ -955,6 +988,11 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
{
struct intel_cdclk_state cdclk_state = {};
+ if (dev_priv->csr.target_dc_state == DC_STATE_EN_DC3CO) {
+ tgl_disable_dc3co(dev_priv);
+ return;
+ }
+
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
dev_priv->display.get_cdclk(dev_priv, &cdclk_state);
@@ -987,10 +1025,63 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
if (!dev_priv->csr.dmc_payload)
return;
- if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
+ switch (dev_priv->csr.target_dc_state) {
+ case DC_STATE_EN_DC3CO:
+ tgl_enable_dc3co(dev_priv);
+ break;
+ case DC_STATE_EN_UPTO_DC6:
skl_enable_dc6(dev_priv);
- else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
+ break;
+ case DC_STATE_EN_UPTO_DC5:
gen9_enable_dc5(dev_priv);
+ break;
+ }
+}
+
+void tgl_set_target_dc_state(struct drm_i915_private *dev_priv, u32 state)
+{
+ struct i915_power_well *power_well;
+ bool dc_off_enabled;
+ struct i915_power_domains *power_domains = &dev_priv->power_domains;
+
+ mutex_lock(&power_domains->lock);
+ power_well = lookup_power_well(dev_priv, SKL_DISP_DC_OFF);
+
+ if (WARN_ON(!power_well))
+ goto unlock;
+
+ /*
+ * Compute the adjusted state wrt to the permisisble allowed dc mask.
+ */
+ if (state != DC_STATE_EN_DC3CO ||
+ !(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)) {
+ if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
+ state = DC_STATE_EN_UPTO_DC6;
+ else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
+ state = DC_STATE_EN_UPTO_DC5;
+ else
+ state = DC_STATE_DISABLE;
+ }
+
+ if (state == dev_priv->csr.target_dc_state)
+ goto unlock;
+
+ dc_off_enabled = power_well->desc->ops->is_enabled(dev_priv,
+ power_well);
+ /*
+ * If DC off power well is disabled, need to enable and disable the
+ * DC off power well to effect target DC state.
+ */
+ if (!dc_off_enabled)
+ power_well->desc->ops->enable(dev_priv, power_well);
+
+ dev_priv->csr.target_dc_state = state;
+
+ if (!dc_off_enabled)
+ power_well->desc->ops->disable(dev_priv, power_well);
+
+unlock:
+ mutex_unlock(&power_domains->lock);
}
static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
@@ -2938,7 +3029,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.name = "DC off",
.domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
- .id = DISP_PW_ID_NONE,
+ .id = SKL_DISP_DC_OFF,
},
{
.name = "power well 2",
@@ -3020,7 +3111,7 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
.name = "DC off",
.domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
- .id = DISP_PW_ID_NONE,
+ .id = SKL_DISP_DC_OFF,
},
{
.name = "power well 2",
@@ -3080,7 +3171,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.name = "DC off",
.domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
- .id = DISP_PW_ID_NONE,
+ .id = SKL_DISP_DC_OFF,
},
{
.name = "power well 2",
@@ -3249,7 +3340,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = {
.name = "DC off",
.domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
- .id = DISP_PW_ID_NONE,
+ .id = SKL_DISP_DC_OFF,
},
{
.name = "power well 2",
@@ -3377,7 +3468,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.name = "DC off",
.domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
- .id = DISP_PW_ID_NONE,
+ .id = SKL_DISP_DC_OFF,
},
{
.name = "power well 2",
@@ -3610,7 +3701,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.name = "DC off",
.domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
- .id = DISP_PW_ID_NONE,
+ .id = SKL_DISP_DC_OFF,
},
{
.name = "power well 2",
@@ -4043,6 +4134,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
dev_priv->csr.allowed_dc_mask =
get_allowed_dc_mask(dev_priv, i915_modparams.enable_dc);
+ allowed_dc_mask_to_target_dc_state(dev_priv);
BUILD_BUG_ON(POWER_DOMAIN_NUM > 64);
mutex_init(&power_domains->lock);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 737b5def7fc6..13fc705799fd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -100,6 +100,7 @@ enum i915_power_well_id {
SKL_DISP_PW_MISC_IO,
SKL_DISP_PW_1,
SKL_DISP_PW_2,
+ SKL_DISP_DC_OFF,
};
#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
@@ -256,6 +257,7 @@ void intel_display_power_suspend_late(struct drm_i915_private *i915);
void intel_display_power_resume_early(struct drm_i915_private *i915);
void intel_display_power_suspend(struct drm_i915_private *i915);
void intel_display_power_resume(struct drm_i915_private *i915);
+void tgl_set_target_dc_state(struct drm_i915_private *dev_priv, u32 state);
const char *
intel_display_power_domain_str(enum intel_display_power_domain domain);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bf600888b3f1..b3544705af9b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -337,6 +337,7 @@ struct intel_csr {
i915_reg_t mmioaddr[20];
u32 mmiodata[20];
u32 dc_state;
+ u32 target_dc_state;
u32 allowed_dc_mask;
intel_wakeref_t wakeref;
};
--
2.21.0
_______________________________________________
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^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v9 3/7] drm/i915/tgl: Enable DC3CO state in "DC Off" power well
2019-09-25 18:10 ` [PATCH v9 3/7] drm/i915/tgl: Enable DC3CO state in "DC Off" power well Anshuman Gupta
@ 2019-09-26 3:56 ` Anshuman Gupta
0 siblings, 0 replies; 14+ messages in thread
From: Anshuman Gupta @ 2019-09-26 3:56 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Add target_dc_state and tgl_set_target_dc_state() API
in order to enable DC3CO state with existing DC states.
target_dc_state will enable/disable the desired DC state in
DC_STATE_EN reg when "DC Off" power well gets disable/enable.
v2: commit log improvement.
v3: Used intel_wait_for_register to wait for DC3CO exit. [Imre]
Used gen9_set_dc_state() to allow/disallow DC3CO. [Imre]
Moved transcoder psr2 exit line enablement from tgl_allow_dc3co()
to a appropriate place haswell_crtc_enable(). [Imre]
Changed the DC3CO power well enabled call back logic as
recommended in review comments. [Imre]
v4: Used wait_for_us() instead of intel_wait_for_reg(). [Imre (IRC)]
v5: using udelay() instead of waiting for DC3CO exit status.
v6: Fixed minor unwanted change.
v7: Removed DC3CO powerwell and POWER_DOMAIN_VIDEO.
v8: Uniform checks by using only target_dc_state instead of allowed_dc_mask
in "DC off" power well callback. [Imre]
Adding "DC off" power well id to older platforms. [Imre]
Removed psr2_deep_sleep flag from tgl_set_target_dc_state. [Imre]
v9: Used switch case for target DC state in gen9_dc_off_power_well_disable().
Checking DC3CO state against allowed DC mask, using WARN_ON()
in tgl_set_target_dc_state(). [Imre]
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
.../drm/i915/display/intel_display_power.c | 110 ++++++++++++++++--
.../drm/i915/display/intel_display_power.h | 2 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
3 files changed, 104 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 24cd9320ad4c..43f03f2794a1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -772,6 +772,38 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
dev_priv->csr.dc_state = val & mask;
}
+static void
+allowed_dc_mask_to_target_dc_state(struct drm_i915_private *dev_priv)
+{
+ if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
+ dev_priv->csr.target_dc_state = DC_STATE_EN_UPTO_DC6;
+ else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
+ dev_priv->csr.target_dc_state = DC_STATE_EN_UPTO_DC5;
+ else
+ dev_priv->csr.target_dc_state = DC_STATE_DISABLE;
+}
+
+static void tgl_enable_dc3co(struct drm_i915_private *dev_priv)
+{
+ DRM_DEBUG_KMS("Enabling DC3CO\n");
+ gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
+}
+
+static void tgl_disable_dc3co(struct drm_i915_private *dev_priv)
+{
+ u32 val;
+
+ DRM_DEBUG_KMS("Disabling DC3CO\n");
+ val = I915_READ(DC_STATE_EN);
+ val &= ~DC_STATE_DC3CO_STATUS;
+ I915_WRITE(DC_STATE_EN, val);
+ gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ /*
+ * Delay of 200us DC3CO Exit time B.Spec 49196
+ */
+ udelay(200);
+}
+
static void bxt_enable_dc9(struct drm_i915_private *dev_priv)
{
assert_can_enable_dc9(dev_priv);
@@ -939,7 +971,8 @@ static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
+ return ((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
+ (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
}
static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
@@ -955,6 +988,11 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
{
struct intel_cdclk_state cdclk_state = {};
+ if (dev_priv->csr.target_dc_state == DC_STATE_EN_DC3CO) {
+ tgl_disable_dc3co(dev_priv);
+ return;
+ }
+
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
dev_priv->display.get_cdclk(dev_priv, &cdclk_state);
@@ -987,10 +1025,63 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
if (!dev_priv->csr.dmc_payload)
return;
- if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
+ switch (dev_priv->csr.target_dc_state) {
+ case DC_STATE_EN_DC3CO:
+ tgl_enable_dc3co(dev_priv);
+ break;
+ case DC_STATE_EN_UPTO_DC6:
skl_enable_dc6(dev_priv);
- else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
+ break;
+ case DC_STATE_EN_UPTO_DC5:
gen9_enable_dc5(dev_priv);
+ break;
+ }
+}
+
+void tgl_set_target_dc_state(struct drm_i915_private *dev_priv, u32 state)
+{
+ struct i915_power_well *power_well;
+ bool dc_off_enabled;
+ struct i915_power_domains *power_domains = &dev_priv->power_domains;
+
+ mutex_lock(&power_domains->lock);
+ power_well = lookup_power_well(dev_priv, SKL_DISP_DC_OFF);
+
+ if (WARN_ON(!power_well))
+ goto unlock;
+
+ /*
+ * Compute the adjusted state wrt to the permisisble allowed dc mask.
+ */
+ if (state != DC_STATE_EN_DC3CO ||
+ !(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)) {
+ if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
+ state = DC_STATE_EN_UPTO_DC6;
+ else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
+ state = DC_STATE_EN_UPTO_DC5;
+ else
+ state = DC_STATE_DISABLE;
+ }
+
+ if (state == dev_priv->csr.target_dc_state)
+ goto unlock;
+
+ dc_off_enabled = power_well->desc->ops->is_enabled(dev_priv,
+ power_well);
+ /*
+ * If DC off power well is disabled, need to enable and disable the
+ * DC off power well to effect target DC state.
+ */
+ if (!dc_off_enabled)
+ power_well->desc->ops->enable(dev_priv, power_well);
+
+ dev_priv->csr.target_dc_state = state;
+
+ if (!dc_off_enabled)
+ power_well->desc->ops->disable(dev_priv, power_well);
+
+unlock:
+ mutex_unlock(&power_domains->lock);
}
static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
@@ -2938,7 +3029,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.name = "DC off",
.domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
- .id = DISP_PW_ID_NONE,
+ .id = SKL_DISP_DC_OFF,
},
{
.name = "power well 2",
@@ -3020,7 +3111,7 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
.name = "DC off",
.domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
- .id = DISP_PW_ID_NONE,
+ .id = SKL_DISP_DC_OFF,
},
{
.name = "power well 2",
@@ -3080,7 +3171,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.name = "DC off",
.domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
- .id = DISP_PW_ID_NONE,
+ .id = SKL_DISP_DC_OFF,
},
{
.name = "power well 2",
@@ -3249,7 +3340,7 @@ static const struct i915_power_well_desc cnl_power_wells[] = {
.name = "DC off",
.domains = CNL_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
- .id = DISP_PW_ID_NONE,
+ .id = SKL_DISP_DC_OFF,
},
{
.name = "power well 2",
@@ -3377,7 +3468,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.name = "DC off",
.domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
- .id = DISP_PW_ID_NONE,
+ .id = SKL_DISP_DC_OFF,
},
{
.name = "power well 2",
@@ -3610,7 +3701,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.name = "DC off",
.domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
- .id = DISP_PW_ID_NONE,
+ .id = SKL_DISP_DC_OFF,
},
{
.name = "power well 2",
@@ -4043,6 +4134,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
dev_priv->csr.allowed_dc_mask =
get_allowed_dc_mask(dev_priv, i915_modparams.enable_dc);
+ allowed_dc_mask_to_target_dc_state(dev_priv);
BUILD_BUG_ON(POWER_DOMAIN_NUM > 64);
mutex_init(&power_domains->lock);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 737b5def7fc6..13fc705799fd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -100,6 +100,7 @@ enum i915_power_well_id {
SKL_DISP_PW_MISC_IO,
SKL_DISP_PW_1,
SKL_DISP_PW_2,
+ SKL_DISP_DC_OFF,
};
#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
@@ -256,6 +257,7 @@ void intel_display_power_suspend_late(struct drm_i915_private *i915);
void intel_display_power_resume_early(struct drm_i915_private *i915);
void intel_display_power_suspend(struct drm_i915_private *i915);
void intel_display_power_resume(struct drm_i915_private *i915);
+void tgl_set_target_dc_state(struct drm_i915_private *dev_priv, u32 state);
const char *
intel_display_power_domain_str(enum intel_display_power_domain domain);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bf600888b3f1..b3544705af9b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -337,6 +337,7 @@ struct intel_csr {
i915_reg_t mmioaddr[20];
u32 mmiodata[20];
u32 dc_state;
+ u32 target_dc_state;
u32 allowed_dc_mask;
intel_wakeref_t wakeref;
};
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v9 4/7] drm/i915/tgl: Do modeset to enable and configure DC3CO exitline
2019-09-25 18:10 [PATCH v9 0/7] DC3CO Support for TGL Anshuman Gupta
` (2 preceding siblings ...)
2019-09-25 18:10 ` [PATCH v9 3/7] drm/i915/tgl: Enable DC3CO state in "DC Off" power well Anshuman Gupta
@ 2019-09-25 18:10 ` Anshuman Gupta
2019-09-25 18:10 ` [PATCH v9 5/7] drm/i915/tgl: DC3CO PSR2 helper Anshuman Gupta
` (7 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Anshuman Gupta @ 2019-09-25 18:10 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
DC3CO enabling B.Specs sequence requires to enable end configure
exit scanlines to TRANS_EXITLINE register, programming this register
has to be part of modeset sequence as this can't be change when
transcoder or port is enabled.
When system boots with only eDP panel there may not be real
modeset as BIOS has already programmed the necessary registers,
therefore it needs to force a modeset to enable and configure
DC3CO exitline.
v1: Computing dc3co_exitline crtc state from a DP encoder
compute config. [Imre]
Enabling and disabling DC3CO PSR2 transcoder exitline from
encoder pre_enable and post_disable hooks. [Imre]
Computing dc3co_exitline instead of has_dc3co_exitline bool. [Imre]
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 7 ++
drivers/gpu/drm/i915/display/intel_display.c | 1 +
.../drm/i915/display/intel_display_power.c | 100 ++++++++++++++++++
.../drm/i915/display/intel_display_power.h | 7 ++
.../drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 2 +
6 files changed, 118 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 3e6394139964..87669e516cc9 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3212,6 +3212,8 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
int level = intel_ddi_dp_level(intel_dp);
enum transcoder transcoder = crtc_state->cpu_transcoder;
+ /* Program the dc3co psr2 transcoder exitline */
+ tgl_set_psr2_transcoder_exitline(crtc_state);
intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
crtc_state->lane_count, is_mst);
@@ -3521,6 +3523,8 @@ static void intel_ddi_post_disable_dp(struct intel_encoder *encoder,
dig_port->ddi_io_power_domain);
intel_ddi_clk_disable(encoder);
+ /* Disable the dc3co psr2 transcoder exitline */
+ tgl_clear_psr2_transcoder_exitline(old_crtc_state);
}
static void intel_ddi_post_disable_hdmi(struct intel_encoder *encoder,
@@ -4050,6 +4054,9 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
break;
}
+ if (encoder->type == INTEL_OUTPUT_EDP)
+ tgl_dc3co_exitline_get_config(pipe_config);
+
pipe_config->has_audio =
intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a19f8c73f2e0..38efdd392556 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -12739,6 +12739,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_I(pixel_multiplier);
PIPE_CONF_CHECK_I(output_format);
+ PIPE_CONF_CHECK_I(dc3co_exitline);
PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index c4a6c7638d92..3fcee8f3ae67 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -19,6 +19,7 @@
#include "intel_hotplug.h"
#include "intel_sideband.h"
#include "intel_tc.h"
+#include "intel_pm.h"
bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
enum i915_power_well_id power_well_id);
@@ -772,6 +773,105 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
dev_priv->csr.dc_state = val & mask;
}
+int intel_get_scan_linetime_us(const struct drm_display_mode *adjusted_mode)
+{
+ /* paranoia */
+ if (WARN_ON(!adjusted_mode->crtc_clock))
+ return 0;
+
+ return DIV_ROUND_UP(1000 * adjusted_mode->crtc_htotal,
+ adjusted_mode->crtc_clock);
+}
+
+void tgl_clear_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
+{
+ struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
+ u32 val;
+
+ if (!cstate->dc3co_exitline)
+ return;
+
+ val = I915_READ(EXITLINE(cstate->cpu_transcoder));
+ val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
+ I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
+}
+
+void tgl_set_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
+{
+ u32 val, exit_scanlines;
+ struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
+
+ if (!cstate->dc3co_exitline)
+ return;
+
+ exit_scanlines = cstate->dc3co_exitline;
+ exit_scanlines <<= EXITLINE_SHIFT;
+ val = I915_READ(EXITLINE(cstate->cpu_transcoder));
+ val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
+ val |= exit_scanlines;
+ val |= EXITLINE_ENABLE;
+ I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
+}
+
+/*
+ * DC3CO requires to enable exitline and program DC3CO requires
+ * exit scanlines to TRANS_EXITLINE register, which should only
+ * change before transcoder or port are enabled.
+ * This requires to disable the fastset at boot for eDP output.
+ */
+void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state)
+{
+ u32 linetime_us, exit_scanlines;
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+ u32 crtc_vdisplay = crtc_state->base.adjusted_mode.crtc_vdisplay;
+
+ if (!IS_TIGERLAKE(dev_priv))
+ return;
+
+ if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
+ return;
+
+ /* B.Specs:49196 DC3CO only works with pipeA and DDIA.*/
+ if (encoder->port != PORT_A)
+ return;
+
+ if (!crtc_state->has_psr2 || !crtc_state->base.active)
+ return;
+
+ linetime_us =
+ intel_get_scan_linetime_us(&crtc_state->base.adjusted_mode);
+
+ if (WARN_ON(!linetime_us))
+ return;
+ /*
+ * DC3CO Exit time 200us B.Spec 49196
+ * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
+ */
+ exit_scanlines = DIV_ROUND_UP(200, linetime_us) + 1;
+ if (WARN_ON(exit_scanlines > crtc_vdisplay))
+ return;
+
+ crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines;
+}
+
+void tgl_dc3co_exitline_get_config(struct intel_crtc_state *crtc_state)
+{
+ u32 val;
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
+
+ if (!IS_TIGERLAKE(dev_priv))
+ return;
+
+ if (!(dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO))
+ return;
+
+ val = I915_READ(EXITLINE(crtc_state->cpu_transcoder));
+
+ if (val & EXITLINE_ENABLE)
+ crtc_state->dc3co_exitline = val & EXITLINE_MASK;
+}
+
static void
allowed_dc_mask_to_target_dc_state(struct drm_i915_private *dev_priv)
{
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 13fc705799fd..981b6a52d192 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -12,6 +12,8 @@
struct drm_i915_private;
struct intel_encoder;
+struct intel_crtc_state;
+struct intel_atomic_state;
enum intel_display_power_domain {
POWER_DOMAIN_DISPLAY_CORE,
@@ -258,6 +260,11 @@ void intel_display_power_resume_early(struct drm_i915_private *i915);
void intel_display_power_suspend(struct drm_i915_private *i915);
void intel_display_power_resume(struct drm_i915_private *i915);
void tgl_set_target_dc_state(struct drm_i915_private *dev_priv, u32 state);
+void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *crtc_state);
+void tgl_dc3co_exitline_get_config(struct intel_crtc_state *crtc_state);
+void tgl_clear_psr2_transcoder_exitline(const struct intel_crtc_state *state);
+void tgl_set_psr2_transcoder_exitline(const struct intel_crtc_state *state);
const char *
intel_display_power_domain_str(enum intel_display_power_domain domain);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index d5cc4b810d9e..46573fb5a152 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -871,6 +871,7 @@ struct intel_crtc_state {
bool has_psr;
bool has_psr2;
+ u32 dc3co_exitline;
/*
* Frequence the dpll for the port should run at. Differs from the
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index d09133a958e1..68bfaf13daf1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2267,6 +2267,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
intel_psr_compute_config(intel_dp, pipe_config);
+ tgl_dc3co_exitline_compute_config(encoder, pipe_config);
+
intel_hdcp_transcoder_config(intel_connector,
pipe_config->cpu_transcoder);
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v9 5/7] drm/i915/tgl: DC3CO PSR2 helper
2019-09-25 18:10 [PATCH v9 0/7] DC3CO Support for TGL Anshuman Gupta
` (3 preceding siblings ...)
2019-09-25 18:10 ` [PATCH v9 4/7] drm/i915/tgl: Do modeset to enable and configure DC3CO exitline Anshuman Gupta
@ 2019-09-25 18:10 ` Anshuman Gupta
2019-09-25 18:10 ` [PATCH v9 6/7] drm/i915/tgl: switch between dc3co and dc5 based on display idleness Anshuman Gupta
` (6 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Anshuman Gupta @ 2019-09-25 18:10 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Disallow DC3CO state before PSR2 exit.
Store dc3co_exitline from crtc state to psr dev_priv
structure to use it easily whenever it requires.
v1: Moved calling of tgl_enable_psr2_transcoder_exitline() to
intel_psr_enable(). [Imre]
v2: Moved tgl_psr2_deep_sleep_enable/disable function to
the patches where they are getting used and used dc3co_exitline
check instead of TGL check. [Imre]
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 8 ++++++++
drivers/gpu/drm/i915/i915_drv.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index b3c7eef53bf3..bf0b741d3243 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -534,6 +534,12 @@ transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans)
return trans == TRANSCODER_EDP;
}
+static void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv)
+{
+ if (!dev_priv->psr.dc3co_exitline)
+ return;
+}
+
static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state)
{
@@ -746,6 +752,7 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv,
dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state);
dev_priv->psr.busy_frontbuffer_bits = 0;
dev_priv->psr.pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
+ dev_priv->psr.dc3co_exitline = crtc_state->dc3co_exitline;
dev_priv->psr.transcoder = crtc_state->cpu_transcoder;
/*
@@ -829,6 +836,7 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
}
if (dev_priv->psr.psr2_enabled) {
+ tgl_disallow_dc3co_on_psr2_exit(dev_priv);
val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder));
WARN_ON(!(val & EDP_PSR2_ENABLE));
val &= ~EDP_PSR2_ENABLE;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b3544705af9b..b86b5bd1b70a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -500,6 +500,7 @@ struct i915_psr {
bool sink_not_reliable;
bool irq_aux_error;
u16 su_x_granularity;
+ u32 dc3co_exitline;
};
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
--
2.21.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v9 6/7] drm/i915/tgl: switch between dc3co and dc5 based on display idleness
2019-09-25 18:10 [PATCH v9 0/7] DC3CO Support for TGL Anshuman Gupta
` (4 preceding siblings ...)
2019-09-25 18:10 ` [PATCH v9 5/7] drm/i915/tgl: DC3CO PSR2 helper Anshuman Gupta
@ 2019-09-25 18:10 ` Anshuman Gupta
2019-09-25 18:10 ` [PATCH v9 7/7] drm/i915/tgl: Add DC3CO counter in i915_dmc_info Anshuman Gupta
` (5 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Anshuman Gupta @ 2019-09-25 18:10 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
DC3CO is useful power state, when DMC detects PSR2 idle frame
while an active video playback, playing 30fps video on 60hz panel
is the classic example of this use case.
B.Specs:49196 has a restriction to enable DC3CO only for Video Playback.
It will be worthy to enable DC3CO after completion of each pageflip
and switch back to DC5 when display is idle because driver doesn't
differentiate between video playback and a normal pageflip.
We will use Frontbuffer flush call tgl_dc3co_flush() to enable DC3CO
state only for ORIGIN_FLIP flush call, because DC3CO state has primarily
targeted for VPB use case. We are not interested here for frontbuffer
invalidates calls because that triggers PSR2 exit, which will
explicitly disable DC3CO.
DC5 and DC6 saves more power, but can't be entered during video
playback because there are not enough idle frames in a row to meet
most PSR2 panel deep sleep entry requirement typically 4 frames.
As PSR2 existing implementation is using minimum 6 idle frames for
deep sleep, it is safer to enable DC5/6 after 6 idle frames
(By scheduling a delayed work of 6 idle frames, once DC3CO has been
enabled after a pageflip).
After manually waiting for 6 idle frames DC5/6 will be enabled and
PSR2 deep sleep idle frames will be restored to 6 idle frames, at this
point DMC will triggers DC5/6 once PSR2 enters to deep sleep after
6 idle frames.
In future when we will enable S/W PSR2 tracking, we can change the
PSR2 required deep sleep idle frames to 1 so DMC can trigger the
DC5/6 immediately after S/W manual waiting of 6 idle frames get
complete.
v2: calculated s/w state to switch over dc3co when there is an
update. [Imre]
Used cancel_delayed_work_sync() in order to avoid any race
with already scheduled delayed work. [Imre]
v3: Cancel_delayed_work_sync() may blocked the commit work.
hence dropping it, dc5_idle_thread() checks the valid wakeref before
putting the reference count, which avoids any chances of dropping
a zero wakeref. [Imre (IRC)]
v4: Used frontbuffer flush mechanism. [Imre]
v5: Used psr.pipe to extract frontbuffer busy bits. [Imre]
Used cancel_delayed_work_sync() in encoder disable path. [Imre]
Used mod_delayed_work() instead of cancelling and scheduling a
delayed work. [Imre]
Used psr.lock in tgl_dc5_idle_thread() to enable psr2 deep
sleep. [Imre]
Removed DC5_REQ_IDLE_FRAMES macro. [Imre]
v6: Inited the busy_frontbuffer_bits, used dc3co_exitline check instead
of TGL and dc3co allowed_dc_mask checks, used delayed_work_pending
with the psr lock and removed the psr2_deep_slp_disabled flag. [Imre]
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
.../drm/i915/display/intel_display_power.c | 97 +++++++++++++++++++
.../drm/i915/display/intel_display_power.h | 4 +
.../gpu/drm/i915/display/intel_frontbuffer.c | 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 34 +++++++
drivers/gpu/drm/i915/display/intel_psr.h | 2 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
6 files changed, 139 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 3fcee8f3ae67..1ae8f499a5d4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -20,6 +20,7 @@
#include "intel_sideband.h"
#include "intel_tc.h"
#include "intel_pm.h"
+#include "intel_psr.h"
bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
enum i915_power_well_id power_well_id);
@@ -794,6 +795,9 @@ void tgl_clear_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
val = I915_READ(EXITLINE(cstate->cpu_transcoder));
val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
+
+ /* As psr2 encoder has disabled, cancel the dc5 idle delayed work */
+ cancel_delayed_work_sync(&dev_priv->csr.idle_work);
}
void tgl_set_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
@@ -813,6 +817,27 @@ void tgl_set_psr2_transcoder_exitline(const struct intel_crtc_state *cstate)
I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
}
+static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate)
+{
+ u32 pixel_rate, crtc_htotal, crtc_vtotal;
+ u32 frametime_us;
+
+ if (!cstate || !cstate->base.active)
+ return 0;
+
+ pixel_rate = cstate->pixel_rate;
+
+ if (WARN_ON(pixel_rate == 0))
+ return 0;
+
+ crtc_htotal = cstate->base.adjusted_mode.crtc_htotal;
+ crtc_vtotal = cstate->base.adjusted_mode.crtc_vtotal;
+ frametime_us = DIV_ROUND_UP(crtc_htotal * crtc_vtotal * 1000ULL,
+ pixel_rate);
+
+ return frametime_us;
+}
+
/*
* DC3CO requires to enable exitline and program DC3CO requires
* exit scanlines to TRANS_EXITLINE register, which should only
@@ -872,6 +897,77 @@ void tgl_dc3co_exitline_get_config(struct intel_crtc_state *crtc_state)
crtc_state->dc3co_exitline = val & EXITLINE_MASK;
}
+/*
+ * When we will enable manual PSR2 S/W tracking in future
+ * we will implement this entire DC3CO flush logic in
+ * intel_psr_flush().
+ */
+void tgl_dc3co_flush(struct drm_i915_private *dev_priv,
+ unsigned int frontbuffer_bits, enum fb_op_origin origin)
+{
+ struct intel_crtc_state *cstate;
+ struct intel_crtc *crtc;
+ u32 delay;
+ unsigned int busy_frontbuffer_bits = 0;
+
+ if (origin != ORIGIN_FLIP)
+ return;
+
+ mutex_lock(&dev_priv->psr.lock);
+
+ if (!dev_priv->psr.dc3co_exitline)
+ goto unlock;
+
+ crtc = intel_get_crtc_for_pipe(dev_priv, dev_priv->psr.pipe);
+ cstate = to_intel_crtc_state(crtc->base.state);
+
+ frontbuffer_bits &=
+ INTEL_FRONTBUFFER_ALL_MASK(dev_priv->psr.pipe);
+
+ busy_frontbuffer_bits &= ~frontbuffer_bits;
+
+ if (!dev_priv->psr.psr2_enabled || !dev_priv->psr.active)
+ goto unlock;
+
+ /*
+ * At every flip frontbuffer flush modified delay of delayed work,
+ * when delayed schedules that means display has been idle.
+ */
+ if (!busy_frontbuffer_bits) {
+ tgl_psr2_deep_sleep_disable(dev_priv);
+ tgl_set_target_dc_state(dev_priv, DC_STATE_EN_DC3CO);
+ /* DC5/DC6 required idle frames = 6 */
+ delay = 6 * intel_get_frame_time_us(cstate);
+ mod_delayed_work(system_wq, &dev_priv->csr.idle_work,
+ usecs_to_jiffies(delay));
+ }
+
+unlock:
+ mutex_unlock(&dev_priv->psr.lock);
+}
+
+void tgl_enable_psr2_deep_sleep_dc6(struct drm_i915_private *dev_priv)
+{
+ tgl_set_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
+ tgl_psr2_deep_sleep_enable(dev_priv);
+}
+
+static void tgl_dc5_idle_thread(struct work_struct *work)
+{
+ struct drm_i915_private *dev_priv =
+ container_of(work, typeof(*dev_priv), csr.idle_work.work);
+
+ mutex_lock(&dev_priv->psr.lock);
+ /* If delayed work is pending, it is not idle */
+ if (delayed_work_pending(&dev_priv->csr.idle_work))
+ goto unlock;
+
+ DRM_DEBUG_KMS("DC5/6 idle thread\n");
+ tgl_enable_psr2_deep_sleep_dc6(dev_priv);
+unlock:
+ mutex_unlock(&dev_priv->psr.lock);
+}
+
static void
allowed_dc_mask_to_target_dc_state(struct drm_i915_private *dev_priv)
{
@@ -4241,6 +4337,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
INIT_DELAYED_WORK(&power_domains->async_put_work,
intel_display_power_put_async_work);
+ INIT_DELAYED_WORK(&dev_priv->csr.idle_work, tgl_dc5_idle_thread);
/*
* The enabling order will be from lower to higher indexed wells,
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 981b6a52d192..5f5caea857af 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -9,6 +9,7 @@
#include "intel_display.h"
#include "intel_runtime_pm.h"
#include "i915_reg.h"
+#include "intel_frontbuffer.h"
struct drm_i915_private;
struct intel_encoder;
@@ -265,6 +266,9 @@ void tgl_dc3co_exitline_compute_config(struct intel_encoder *encoder,
void tgl_dc3co_exitline_get_config(struct intel_crtc_state *crtc_state);
void tgl_clear_psr2_transcoder_exitline(const struct intel_crtc_state *state);
void tgl_set_psr2_transcoder_exitline(const struct intel_crtc_state *state);
+void tgl_dc3co_flush(struct drm_i915_private *dev_priv,
+ unsigned int frontbuffer_bits, enum fb_op_origin origin);
+void tgl_enable_psr2_deep_sleep_dc6(struct drm_i915_private *dev_priv);
const char *
intel_display_power_domain_str(enum intel_display_power_domain domain);
diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
index fc40dc1fdbcc..c3b10f6e4382 100644
--- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c
+++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c
@@ -90,6 +90,7 @@ static void frontbuffer_flush(struct drm_i915_private *i915,
might_sleep();
intel_edp_drrs_flush(i915, frontbuffer_bits);
intel_psr_flush(i915, frontbuffer_bits, origin);
+ tgl_dc3co_flush(i915, frontbuffer_bits, origin);
intel_fbc_flush(i915, frontbuffer_bits, origin);
}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index bf0b741d3243..5faaf35ba4ff 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -534,10 +534,44 @@ transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder trans)
return trans == TRANSCODER_EDP;
}
+static void psr2_program_idle_frames(struct drm_i915_private *dev_priv,
+ u32 idle_frames)
+{
+ u32 val;
+
+ idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT;
+ val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder));
+ val &= ~EDP_PSR2_IDLE_FRAME_MASK;
+ val |= idle_frames;
+ I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val);
+}
+
+void tgl_psr2_deep_sleep_disable(struct drm_i915_private *dev_priv)
+{
+ psr2_program_idle_frames(dev_priv, 0);
+}
+
+void tgl_psr2_deep_sleep_enable(struct drm_i915_private *dev_priv)
+{
+ int idle_frames;
+
+ /*
+ * Let's use 6 as the minimum to cover all known cases including the
+ * off-by-one issue that HW has in some cases.
+ */
+ idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
+ idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
+ psr2_program_idle_frames(dev_priv, idle_frames);
+}
+
static void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv)
{
if (!dev_priv->psr.dc3co_exitline)
return;
+
+ cancel_delayed_work(&dev_priv->csr.idle_work);
+ /* Before PSR2 exit disallow dc3co*/
+ tgl_enable_psr2_deep_sleep_dc6(dev_priv);
}
static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 46e4de8b8cd5..75a9862f36fd 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -35,5 +35,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp);
int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
u32 *out_value);
bool intel_psr_enabled(struct intel_dp *intel_dp);
+void tgl_psr2_deep_sleep_disable(struct drm_i915_private *dev_priv);
+void tgl_psr2_deep_sleep_enable(struct drm_i915_private *dev_priv);
#endif /* __INTEL_PSR_H__ */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b86b5bd1b70a..087c13cb26b2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -339,6 +339,7 @@ struct intel_csr {
u32 dc_state;
u32 target_dc_state;
u32 allowed_dc_mask;
+ struct delayed_work idle_work;
intel_wakeref_t wakeref;
};
--
2.21.0
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v9 7/7] drm/i915/tgl: Add DC3CO counter in i915_dmc_info
2019-09-25 18:10 [PATCH v9 0/7] DC3CO Support for TGL Anshuman Gupta
` (5 preceding siblings ...)
2019-09-25 18:10 ` [PATCH v9 6/7] drm/i915/tgl: switch between dc3co and dc5 based on display idleness Anshuman Gupta
@ 2019-09-25 18:10 ` Anshuman Gupta
2019-09-25 19:04 ` ✗ Fi.CI.BUILD: failure for DC3CO Support for TGL (rev10) Patchwork
` (4 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Anshuman Gupta @ 2019-09-25 18:10 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Adding DC3CO counter in i915_dmc_info debugfs will be
useful for DC3CO validation.
DMC firmware uses DMC_DEBUG3 register as DC3CO counter
register on TGL, as per B.Specs DMC_DEBUG3 is general
purpose register.
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 ++++++
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 43db50095257..8dde0a09b7dd 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2407,6 +2407,12 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
CSR_VERSION_MINOR(csr->version));
+ /*
+ * TGL DMC f/w uses DMC_DEBUG3 register for DC3CO counter.
+ */
+ if (IS_TIGERLAKE(dev_priv))
+ seq_printf(m, "DC3CO count: %d\n", I915_READ(DMC_DEBUG3));
+
if (INTEL_GEN(dev_priv) >= 12) {
dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6bfebab9a441..3ad75d0fb71a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7255,6 +7255,8 @@ enum {
#define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084)
#define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088)
+#define DMC_DEBUG3 _MMIO(0x101090)
+
/* interrupts */
#define DE_MASTER_IRQ_CONTROL (1 << 31)
#define DE_SPRITEB_FLIP_DONE (1 << 29)
--
2.21.0
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread* ✗ Fi.CI.BUILD: failure for DC3CO Support for TGL (rev10)
2019-09-25 18:10 [PATCH v9 0/7] DC3CO Support for TGL Anshuman Gupta
` (6 preceding siblings ...)
2019-09-25 18:10 ` [PATCH v9 7/7] drm/i915/tgl: Add DC3CO counter in i915_dmc_info Anshuman Gupta
@ 2019-09-25 19:04 ` Patchwork
2019-09-26 4:40 ` ✗ Fi.CI.CHECKPATCH: warning for DC3CO Support for TGL (rev11) Patchwork
` (3 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2019-09-25 19:04 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
== Series Details ==
Series: DC3CO Support for TGL (rev10)
URL : https://patchwork.freedesktop.org/series/64923/
State : failure
== Summary ==
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
AR drivers/gpu/drm/i915/built-in.a
CC [M] drivers/gpu/drm/i915/display/intel_display_power.o
drivers/gpu/drm/i915/display/intel_display_power.c: In function ‘tgl_set_target_dc_state’:
drivers/gpu/drm/i915/display/intel_display_power.c:1284:2: error: this ‘if’ clause does not guard... [-Werror=misleading-indentation]
if (!dc_off_enabled)
^~
drivers/gpu/drm/i915/display/intel_display_power.c:1287:3: note: ...this statement, but the latter is misleadingly indented as if it were guarded by the ‘if’
dev_priv->csr.target_dc_state = state;
^~~~~~~~
cc1: all warnings being treated as errors
scripts/Makefile.build:280: recipe for target 'drivers/gpu/drm/i915/display/intel_display_power.o' failed
make[4]: *** [drivers/gpu/drm/i915/display/intel_display_power.o] Error 1
scripts/Makefile.build:497: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:497: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:497: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1087: recipe for target 'drivers' failed
make: *** [drivers] Error 2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread* ✗ Fi.CI.CHECKPATCH: warning for DC3CO Support for TGL (rev11)
2019-09-25 18:10 [PATCH v9 0/7] DC3CO Support for TGL Anshuman Gupta
` (7 preceding siblings ...)
2019-09-25 19:04 ` ✗ Fi.CI.BUILD: failure for DC3CO Support for TGL (rev10) Patchwork
@ 2019-09-26 4:40 ` Patchwork
2019-09-26 4:44 ` ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2019-09-26 4:40 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
== Series Details ==
Series: DC3CO Support for TGL (rev11)
URL : https://patchwork.freedesktop.org/series/64923/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
805a6f5f1e23 drm/i915/tgl: Add DC3CO required register and bits
5e43f1ddfa09 drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
b94f1a7b1d4a drm/i915/tgl: Enable DC3CO state in "DC Off" power well
-:26: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#26:
v9: Used switch case for target DC state in gen9_dc_off_power_well_disable().
-:72: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst
#72: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:817:
+ udelay(200);
total: 0 errors, 1 warnings, 1 checks, 199 lines checked
c413c301cf16 drm/i915/tgl: Do modeset to enable and configure DC3CO exitline
525848d6a4b1 drm/i915/tgl: DC3CO PSR2 helper
fc92420beb0e drm/i915/tgl: switch between dc3co and dc5 based on display idleness
5823e8625389 drm/i915/tgl: Add DC3CO counter in i915_dmc_info
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread* ✗ Fi.CI.SPARSE: warning for DC3CO Support for TGL (rev11)
2019-09-25 18:10 [PATCH v9 0/7] DC3CO Support for TGL Anshuman Gupta
` (8 preceding siblings ...)
2019-09-26 4:40 ` ✗ Fi.CI.CHECKPATCH: warning for DC3CO Support for TGL (rev11) Patchwork
@ 2019-09-26 4:44 ` Patchwork
2019-09-26 5:02 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-09-26 5:02 ` ✗ Fi.CI.BUILD: warning " Patchwork
11 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2019-09-26 4:44 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
== Series Details ==
Series: DC3CO Support for TGL (rev11)
URL : https://patchwork.freedesktop.org/series/64923/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/tgl: Add DC3CO required register and bits
Okay!
Commit: drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
Okay!
Commit: drm/i915/tgl: Enable DC3CO state in "DC Off" power well
Okay!
Commit: drm/i915/tgl: Do modeset to enable and configure DC3CO exitline
+drivers/gpu/drm/i915/display/intel_display_power.c:789:5: warning: symbol 'intel_get_scan_linetime_us' was not declared. Should it be static?
Commit: drm/i915/tgl: DC3CO PSR2 helper
Okay!
Commit: drm/i915/tgl: switch between dc3co and dc5 based on display idleness
Okay!
Commit: drm/i915/tgl: Add DC3CO counter in i915_dmc_info
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread* ✗ Fi.CI.BAT: failure for DC3CO Support for TGL (rev11)
2019-09-25 18:10 [PATCH v9 0/7] DC3CO Support for TGL Anshuman Gupta
` (9 preceding siblings ...)
2019-09-26 4:44 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2019-09-26 5:02 ` Patchwork
2019-09-26 5:02 ` ✗ Fi.CI.BUILD: warning " Patchwork
11 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2019-09-26 5:02 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
== Series Details ==
Series: DC3CO Support for TGL (rev11)
URL : https://patchwork.freedesktop.org/series/64923/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6963 -> Patchwork_14548
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_14548 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14548, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14548/
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14548:
### IGT changes ###
#### Possible regressions ####
* igt@kms_force_connector_basic@force-connector-state:
- fi-kbl-guc: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-kbl-guc/igt@kms_force_connector_basic@force-connector-state.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14548/fi-kbl-guc/igt@kms_force_connector_basic@force-connector-state.html
* igt@runner@aborted:
- fi-ilk-650: NOTRUN -> [FAIL][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14548/fi-ilk-650/igt@runner@aborted.html
- fi-bdw-gvtdvm: NOTRUN -> [FAIL][4]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14548/fi-bdw-gvtdvm/igt@runner@aborted.html
- fi-gdg-551: NOTRUN -> [FAIL][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14548/fi-gdg-551/igt@runner@aborted.html
- fi-snb-2520m: NOTRUN -> [FAIL][6]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14548/fi-snb-2520m/igt@runner@aborted.html
- fi-ivb-3770: NOTRUN -> [FAIL][7]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14548/fi-ivb-3770/igt@runner@aborted.html
- fi-bsw-n3050: NOTRUN -> [FAIL][8]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14548/fi-bsw-n3050/igt@runner@aborted.html
- fi-blb-e6850: NOTRUN -> [FAIL][9]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14548/fi-blb-e6850/igt@runner@aborted.html
- fi-bsw-kefka: NOTRUN -> [FAIL][10]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14548/fi-bsw-kefka/igt@runner@aborted.html
- fi-apl-guc: NOTRUN -> [FAIL][11]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14548/fi-apl-guc/igt@runner@aborted.html
- fi-bdw-5557u: NOTRUN -> [FAIL][12]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14548/fi-bdw-5557u/igt@runner@aborted.html
- fi-kbl-guc: NOTRUN -> [FAIL][13]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14548/fi-kbl-guc/igt@runner@aborted.html
- fi-elk-e7500: NOTRUN -> [FAIL][14]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14548/fi-elk-e7500/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_14548 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_switch@rcs0:
- fi-icl-u2: [PASS][15] -> [INCOMPLETE][16] ([fdo#107713])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-icl-u2/igt@gem_ctx_switch@rcs0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14548/fi-icl-u2/igt@gem_ctx_switch@rcs0.html
#### Possible fixes ####
* igt@i915_selftest@live_gtt:
- {fi-tgl-u2}: [INCOMPLETE][17] -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6963/fi-tgl-u2/igt@i915_selftest@live_gtt.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14548/fi-tgl-u2/igt@i915_selftest@live_gtt.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
Participating hosts (50 -> 42)
------------------------------
Additional (1): fi-kbl-soraka
Missing (9): fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-pnv-d510 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6963 -> Patchwork_14548
CI-20190529: 20190529
CI_DRM_6963: 364bf33c246115063174fa2a07e9f5a6bddc9f72 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5203: 82326332f7af336d390e00ae87187bc207fd33dd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14548: 5823e8625389568de0dc05708cb8c62047a21f9f @ git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/Patchwork_14548/build_32bit.log
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 117 modules
ERROR: "__udivdi3" [drivers/gpu/drm/i915/i915.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/i915/i915.ko] undefined!
scripts/Makefile.modpost:103: recipe for target 'modules-modpost' failed
make[1]: *** [modules-modpost] Error 1
Makefile:1305: recipe for target 'modules' failed
make: *** [modules] Error 2
== Linux commits ==
5823e8625389 drm/i915/tgl: Add DC3CO counter in i915_dmc_info
fc92420beb0e drm/i915/tgl: switch between dc3co and dc5 based on display idleness
525848d6a4b1 drm/i915/tgl: DC3CO PSR2 helper
c413c301cf16 drm/i915/tgl: Do modeset to enable and configure DC3CO exitline
b94f1a7b1d4a drm/i915/tgl: Enable DC3CO state in "DC Off" power well
5e43f1ddfa09 drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
805a6f5f1e23 drm/i915/tgl: Add DC3CO required register and bits
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14548/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread* ✗ Fi.CI.BUILD: warning for DC3CO Support for TGL (rev11)
2019-09-25 18:10 [PATCH v9 0/7] DC3CO Support for TGL Anshuman Gupta
` (10 preceding siblings ...)
2019-09-26 5:02 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2019-09-26 5:02 ` Patchwork
11 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2019-09-26 5:02 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
== Series Details ==
Series: DC3CO Support for TGL (rev11)
URL : https://patchwork.freedesktop.org/series/64923/
State : warning
== Summary ==
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
CHK include/generated/compile.h
Kernel: arch/x86/boot/bzImage is ready (#1)
Building modules, stage 2.
MODPOST 117 modules
ERROR: "__udivdi3" [drivers/gpu/drm/i915/i915.ko] undefined!
ERROR: "__divdi3" [drivers/gpu/drm/i915/i915.ko] undefined!
scripts/Makefile.modpost:103: recipe for target 'modules-modpost' failed
make[1]: *** [modules-modpost] Error 1
Makefile:1305: recipe for target 'modules' failed
make: *** [modules] Error 2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14548/build_32bit.log
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread