Add support for TGL in SAGV code paths

Add support for TGL in SAGV code paths

[James Ausmus]

Even though we can't actually turn on SAGV for TGL until HSDES
1409542895 is resolved, these patches prepare the code for enabling
SAGV, so that once the HSDES is resolved, all we have to do is revert
8ffa4392a32e ("drm/i915/tgl: disable SAGV temporarily") to turn it on.


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[PATCH 1/3] drm/i915: Extract SAGV block time function

[James Ausmus]

In prep for newer platforms having more complicated ways to determine
the SAGV block time, extract the setting to a separate function. While
we're at it, update the if ladder to follow the new gen -> old gen order
preference, and warn on any non-specified gen.

Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: James Ausmus <james.ausmus@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 24 ++++++++++++++++++------
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6bed2ed14574..5ad72dcb0faa 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3662,6 +3662,23 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
 		dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
 }
 
+static int
+intel_get_sagv_block_time_us(struct drm_i915_private *dev_priv)
+{
+	int sagv_block_time_us = 1000; /* Default to unusable block time */
+
+	if (IS_GEN(dev_priv, 11))
+		sagv_block_time_us = 10;
+	else if (IS_GEN(dev_priv, 10))
+		sagv_block_time_us = 20;
+	else if (IS_GEN(dev_priv, 9))
+		sagv_block_time_us = 30;
+	else
+		MISSING_CASE(INTEL_GEN(dev_priv));
+
+	return sagv_block_time_us;
+}
+
 /*
  * SAGV dynamically adjusts the system agent voltage and clock frequencies
  * depending on power and performance requirements. The display engine access
@@ -3755,12 +3772,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
 	if (!intel_has_sagv(dev_priv))
 		return false;
 
-	if (IS_GEN(dev_priv, 9))
-		sagv_block_time_us = 30;
-	else if (IS_GEN(dev_priv, 10))
-		sagv_block_time_us = 20;
-	else
-		sagv_block_time_us = 10;
+	sagv_block_time_us = intel_get_sagv_block_time_us(dev_priv);
 
 	/*
 	 * If there are no active CRTCs, no additional checks need be performed
-- 
2.22.1

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[PATCH 2/3] drm/i915/tgl: Read SAGV block time from PCODE

[James Ausmus]

Starting from TGL, we now need to read the SAGV block time via a PCODE
mailbox, rather than having a static value.

BSpec: 49326

Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: James Ausmus <james.ausmus@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c | 20 +++++++++++++++-----
 2 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e752de9470bd..84ae6553485b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8865,6 +8865,7 @@ enum {
 #define     GEN9_SAGV_DISABLE			0x0
 #define     GEN9_SAGV_IS_DISABLED		0x1
 #define     GEN9_SAGV_ENABLE			0x3
+#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
 #define GEN6_PCODE_DATA				_MMIO(0x138128)
 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5ad72dcb0faa..ca2bec09edb5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3665,16 +3665,26 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
 static int
 intel_get_sagv_block_time_us(struct drm_i915_private *dev_priv)
 {
-	int sagv_block_time_us = 1000; /* Default to unusable block time */
+	uint val = 0;
+	int ret, sagv_block_time_us = 1000; /* Default to unusable block time */
 
-	if (IS_GEN(dev_priv, 11))
+	if (INTEL_GEN(dev_priv) >= 12) {
+		ret = sandybridge_pcode_read(dev_priv,
+					     GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
+					     &val, NULL);
+		if (!ret)
+			sagv_block_time_us = val;
+		else
+			DRM_DEBUG_DRIVER("Couldn't read SAGV block time!\n");
+	} else if (IS_GEN(dev_priv, 11)) {
 		sagv_block_time_us = 10;
-	else if (IS_GEN(dev_priv, 10))
+	} else if (IS_GEN(dev_priv, 10)) {
 		sagv_block_time_us = 20;
-	else if (IS_GEN(dev_priv, 9))
+	} else if (IS_GEN(dev_priv, 9)) {
 		sagv_block_time_us = 30;
-	else
+	} else {
 		MISSING_CASE(INTEL_GEN(dev_priv));
+	}
 
 	return sagv_block_time_us;
 }
-- 
2.22.1

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[PATCH 3/3] drm/i915/tgl: Remove single pipe restriction from SAGV

[James Ausmus]

For Gen12, BSpec no longer tells us to disable SAGV when > 1 pipe is
active. Update intel_can_enable_sagv to allow this, and loop through all
active planes on all active crtcs to check against the interlaced and
latency restrictions.

BSpec: 49325

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: James Ausmus <james.ausmus@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 63 +++++++++++++++++----------------
 1 file changed, 32 insertions(+), 31 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ca2bec09edb5..cb50c697a6b8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3775,7 +3775,6 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
 	struct intel_crtc *crtc;
 	struct intel_plane *plane;
 	struct intel_crtc_state *crtc_state;
-	enum pipe pipe;
 	int level, latency;
 	int sagv_block_time_us;
 
@@ -3791,47 +3790,49 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
 		return true;
 
 	/*
-	 * SKL+ workaround: bspec recommends we disable SAGV when we have
+	 * SKL-ICL workaround: bspec recommends we disable SAGV when we have
 	 * more then one pipe enabled
 	 */
-	if (hweight8(state->active_pipes) > 1)
+	if (INTEL_GEN(dev_priv) < 12 && hweight8(state->active_pipes) > 1)
 		return false;
 
-	/* Since we're now guaranteed to only have one active CRTC... */
-	pipe = ffs(state->active_pipes) - 1;
-	crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
-	crtc_state = to_intel_crtc_state(crtc->base.state);
+	for_each_intel_crtc(&dev_priv->drm, crtc) {
+		crtc_state = to_intel_crtc_state(crtc->base.state);
+		if (!crtc_state->base.active)
+			continue;
 
-	if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
-		return false;
+		if (crtc->base.state->adjusted_mode.flags &
+		    DRM_MODE_FLAG_INTERLACE)
+			return false;
 
-	for_each_intel_plane_on_crtc(dev, crtc, plane) {
-		struct skl_plane_wm *wm =
-			&crtc_state->wm.skl.optimal.planes[plane->id];
+		for_each_intel_plane_on_crtc(dev, crtc, plane) {
+			struct skl_plane_wm *wm =
+				&crtc_state->wm.skl.optimal.planes[plane->id];
 
-		/* Skip this plane if it's not enabled */
-		if (!wm->wm[0].plane_en)
-			continue;
+			/* Skip this plane if it's not enabled */
+			if (!wm->wm[0].plane_en)
+				continue;
 
-		/* Find the highest enabled wm level for this plane */
-		for (level = ilk_wm_max_level(dev_priv);
-		     !wm->wm[level].plane_en; --level)
-		     { }
+			/* Find the highest enabled wm level for this plane */
+			for (level = ilk_wm_max_level(dev_priv);
+			     !wm->wm[level].plane_en; --level)
+			     { }
 
-		latency = dev_priv->wm.skl_latency[level];
+			latency = dev_priv->wm.skl_latency[level];
 
-		if (skl_needs_memory_bw_wa(dev_priv) &&
-		    plane->base.state->fb->modifier ==
-		    I915_FORMAT_MOD_X_TILED)
-			latency += 15;
+			if (skl_needs_memory_bw_wa(dev_priv) &&
+			    plane->base.state->fb->modifier ==
+			    I915_FORMAT_MOD_X_TILED)
+				latency += 15;
 
-		/*
-		 * If any of the planes on this pipe don't enable wm levels that
-		 * incur memory latencies higher than sagv_block_time_us we
-		 * can't enable SAGV.
-		 */
-		if (latency < sagv_block_time_us)
-			return false;
+			/*
+			 * If any of the planes on this pipe don't enable wm
+			 * levels that incur memory latencies higher than
+			 * sagv_block_time_us we can't enable SAGV.
+			 */
+			if (latency < sagv_block_time_us)
+				return false;
+		}
 	}
 
 	return true;
-- 
2.22.1

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✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915: Extract SAGV block time function

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: Extract SAGV block time function
URL   : https://patchwork.freedesktop.org/series/67240/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
45bac93b7379 drm/i915: Extract SAGV block time function
fffc1235b9c0 drm/i915/tgl: Read SAGV block time from PCODE
56a9c538a831 drm/i915/tgl: Remove single pipe restriction from SAGV
-:79: ERROR:OPEN_BRACE: that open brace { should be on the previous line
#79: FILE: drivers/gpu/drm/i915/intel_pm.c:3817:
+			for (level = ilk_wm_max_level(dev_priv);
+			     !wm->wm[level].plane_en; --level)
+			     { }

total: 1 errors, 0 warnings, 0 checks, 86 lines checked

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✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915: Extract SAGV block time function

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: Extract SAGV block time function
URL   : https://patchwork.freedesktop.org/series/67240/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6958 -> Patchwork_14539
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/

Known issues
------------

  Here are the changes found in Patchwork_14539 that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@gem_ctx_switch@rcs0:
    - {fi-icl-guc}:       [INCOMPLETE][1] ([fdo#107713]) -> [PASS][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/fi-icl-guc/igt@gem_ctx_switch@rcs0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/fi-icl-guc/igt@gem_ctx_switch@rcs0.html

  * igt@gem_exec_suspend@basic-s3:
    - fi-blb-e6850:       [INCOMPLETE][3] ([fdo#107718]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-hsw-peppy:       [DMESG-WARN][5] ([fdo#102614]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html

  
#### Warnings ####

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][7] ([fdo#111045] / [fdo#111096]) -> [FAIL][8] ([fdo#111407])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407


Participating hosts (50 -> 44)
------------------------------

  Additional (1): fi-tgl-u2 
  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6958 -> Patchwork_14539

  CI-20190529: 20190529
  CI_DRM_6958: d5c4d0bc1c0570ba9128e7afb419d5d5a8ebd4bc @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5203: 82326332f7af336d390e00ae87187bc207fd33dd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14539: 56a9c538a831b886c0c2c4b018fec50767d257cc @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

56a9c538a831 drm/i915/tgl: Remove single pipe restriction from SAGV
fffc1235b9c0 drm/i915/tgl: Read SAGV block time from PCODE
45bac93b7379 drm/i915: Extract SAGV block time function

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/index.html
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Re: [PATCH 3/3] drm/i915/tgl: Remove single pipe restriction from SAGV

[Ville Syrjälä]

On Wed, Sep 25, 2019 at 01:33:52PM -0700, James Ausmus wrote:
> For Gen12, BSpec no longer tells us to disable SAGV when > 1 pipe is
> active. Update intel_can_enable_sagv to allow this, and loop through all
> active planes on all active crtcs to check against the interlaced and
> latency restrictions.
> 
> BSpec: 49325
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: James Ausmus <james.ausmus@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 63 +++++++++++++++++----------------
>  1 file changed, 32 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index ca2bec09edb5..cb50c697a6b8 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3775,7 +3775,6 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
>  	struct intel_crtc *crtc;
>  	struct intel_plane *plane;
>  	struct intel_crtc_state *crtc_state;
> -	enum pipe pipe;
>  	int level, latency;
>  	int sagv_block_time_us;
>  
> @@ -3791,47 +3790,49 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
>  		return true;
>  
>  	/*
> -	 * SKL+ workaround: bspec recommends we disable SAGV when we have
> +	 * SKL-ICL workaround: bspec recommends we disable SAGV when we have
>  	 * more then one pipe enabled
>  	 */
> -	if (hweight8(state->active_pipes) > 1)
> +	if (INTEL_GEN(dev_priv) < 12 && hweight8(state->active_pipes) > 1)
>  		return false;
>  
> -	/* Since we're now guaranteed to only have one active CRTC... */
> -	pipe = ffs(state->active_pipes) - 1;
> -	crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> -	crtc_state = to_intel_crtc_state(crtc->base.state);
> +	for_each_intel_crtc(&dev_priv->drm, crtc) {
> +		crtc_state = to_intel_crtc_state(crtc->base.state);
> +		if (!crtc_state->base.active)
> +			continue;
>  
> -	if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> -		return false;
> +		if (crtc->base.state->adjusted_mode.flags &
> +		    DRM_MODE_FLAG_INTERLACE)
> +			return false;
>  
> -	for_each_intel_plane_on_crtc(dev, crtc, plane) {
> -		struct skl_plane_wm *wm =
> -			&crtc_state->wm.skl.optimal.planes[plane->id];
> +		for_each_intel_plane_on_crtc(dev, crtc, plane) {
> +			struct skl_plane_wm *wm =
> +				&crtc_state->wm.skl.optimal.planes[plane->id];

This whole loop is bothering me. I'd much rather we move to a scheme
where each plane computes it's SAGV friendlyness when computing the
watermarks. We'll anyway need that since we need to caclulate the
watermarks differently for the SAGV on vs. off cases.

>  
> -		/* Skip this plane if it's not enabled */
> -		if (!wm->wm[0].plane_en)
> -			continue;
> +			/* Skip this plane if it's not enabled */
> +			if (!wm->wm[0].plane_en)
> +				continue;
>  
> -		/* Find the highest enabled wm level for this plane */
> -		for (level = ilk_wm_max_level(dev_priv);
> -		     !wm->wm[level].plane_en; --level)
> -		     { }
> +			/* Find the highest enabled wm level for this plane */
> +			for (level = ilk_wm_max_level(dev_priv);
> +			     !wm->wm[level].plane_en; --level)
> +			     { }
>  
> -		latency = dev_priv->wm.skl_latency[level];
> +			latency = dev_priv->wm.skl_latency[level];
>  
> -		if (skl_needs_memory_bw_wa(dev_priv) &&
> -		    plane->base.state->fb->modifier ==
> -		    I915_FORMAT_MOD_X_TILED)
> -			latency += 15;
> +			if (skl_needs_memory_bw_wa(dev_priv) &&
> +			    plane->base.state->fb->modifier ==
> +			    I915_FORMAT_MOD_X_TILED)
> +				latency += 15;
>  
> -		/*
> -		 * If any of the planes on this pipe don't enable wm levels that
> -		 * incur memory latencies higher than sagv_block_time_us we
> -		 * can't enable SAGV.
> -		 */
> -		if (latency < sagv_block_time_us)
> -			return false;
> +			/*
> +			 * If any of the planes on this pipe don't enable wm
> +			 * levels that incur memory latencies higher than
> +			 * sagv_block_time_us we can't enable SAGV.
> +			 */
> +			if (latency < sagv_block_time_us)
> +				return false;
> +		}
>  	}
>  
>  	return true;
> -- 
> 2.22.1

-- 
Ville Syrjälä
Intel
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✓ Fi.CI.IGT: success for series starting with [1/3] drm/i915: Extract SAGV block time function

[Patchwork]

== Series Details ==

Series: series starting with [1/3] drm/i915: Extract SAGV block time function
URL   : https://patchwork.freedesktop.org/series/67240/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6958_full -> Patchwork_14539_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_14539_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_schedule@preemptive-hang-bsd:
    - shard-iclb:         [PASS][1] -> [SKIP][2] ([fdo#111325]) +5 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-iclb6/igt@gem_exec_schedule@preemptive-hang-bsd.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-skl:          [PASS][3] -> [FAIL][4] ([fdo#105363])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@plain-flip-ts-check-interruptible:
    - shard-skl:          [PASS][5] -> [FAIL][6] ([fdo#100368])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-skl1/igt@kms_flip@plain-flip-ts-check-interruptible.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/shard-skl6/igt@kms_flip@plain-flip-ts-check-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render:
    - shard-iclb:         [PASS][7] -> [FAIL][8] ([fdo#103167]) +3 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-apl:          [PASS][9] -> [DMESG-WARN][10] ([fdo#108566]) +5 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-apl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/shard-apl7/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
    - shard-skl:          [PASS][11] -> [FAIL][12] ([fdo#103191])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-skl9/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/shard-skl6/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
    - shard-kbl:          [PASS][13] -> [DMESG-WARN][14] ([fdo#108566])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
    - shard-skl:          [PASS][15] -> [INCOMPLETE][16] ([fdo#104108])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-skl9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/shard-skl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html

  * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
    - shard-skl:          [PASS][17] -> [FAIL][18] ([fdo#108145]) +2 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html

  * igt@kms_psr@psr2_sprite_mmap_gtt:
    - shard-iclb:         [PASS][19] -> [SKIP][20] ([fdo#109441]) +2 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/shard-iclb7/igt@kms_psr@psr2_sprite_mmap_gtt.html

  * igt@kms_vblank@pipe-a-query-forked:
    - shard-snb:          [PASS][21] -> [SKIP][22] ([fdo#109271])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-snb7/igt@kms_vblank@pipe-a-query-forked.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/shard-snb7/igt@kms_vblank@pipe-a-query-forked.html

  * igt@perf@blocking:
    - shard-skl:          [PASS][23] -> [FAIL][24] ([fdo#110728])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-skl7/igt@perf@blocking.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/shard-skl5/igt@perf@blocking.html

  * igt@prime_busy@hang-bsd2:
    - shard-iclb:         [PASS][25] -> [SKIP][26] ([fdo#109276]) +22 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-iclb1/igt@prime_busy@hang-bsd2.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/shard-iclb5/igt@prime_busy@hang-bsd2.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@rcs0-s3:
    - shard-skl:          [INCOMPLETE][27] ([fdo#104108]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-skl4/igt@gem_ctx_isolation@rcs0-s3.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/shard-skl8/igt@gem_ctx_isolation@rcs0-s3.html

  * igt@gem_exec_schedule@reorder-wide-bsd:
    - shard-iclb:         [SKIP][29] ([fdo#111325]) -> [PASS][30] +7 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-iclb4/igt@gem_exec_schedule@reorder-wide-bsd.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/shard-iclb6/igt@gem_exec_schedule@reorder-wide-bsd.html

  * igt@gem_softpin@noreloc-s3:
    - shard-apl:          [DMESG-WARN][31] ([fdo#108566]) -> [PASS][32] +3 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-apl8/igt@gem_softpin@noreloc-s3.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/shard-apl2/igt@gem_softpin@noreloc-s3.html

  * igt@gem_workarounds@suspend-resume-context:
    - shard-apl:          [INCOMPLETE][33] ([fdo#103927]) -> [PASS][34] +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-apl6/igt@gem_workarounds@suspend-resume-context.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/shard-apl7/igt@gem_workarounds@suspend-resume-context.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-glk:          [FAIL][35] ([fdo#105363]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-glk1/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
    - shard-iclb:         [FAIL][37] ([fdo#103167]) -> [PASS][38] +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - shard-iclb:         [INCOMPLETE][39] ([fdo#107713]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-iclb7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/shard-iclb3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
    - shard-skl:          [FAIL][41] ([fdo#108145] / [fdo#110403]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html

  * igt@kms_rotation_crc@sprite-rotation-90:
    - shard-iclb:         [INCOMPLETE][43] ([fdo#107713] / [fdo#110026]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-iclb7/igt@kms_rotation_crc@sprite-rotation-90.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/shard-iclb1/igt@kms_rotation_crc@sprite-rotation-90.html

  * igt@kms_setmode@basic:
    - shard-kbl:          [FAIL][45] ([fdo#99912]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-kbl2/igt@kms_setmode@basic.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/shard-kbl7/igt@kms_setmode@basic.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-kbl:          [DMESG-WARN][47] ([fdo#108566]) -> [PASS][48] +1 similar issue
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  * igt@prime_vgem@fence-wait-bsd2:
    - shard-iclb:         [SKIP][49] ([fdo#109276]) -> [PASS][50] +27 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-iclb5/igt@prime_vgem@fence-wait-bsd2.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/shard-iclb4/igt@prime_vgem@fence-wait-bsd2.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs1-nonpriv:
    - shard-iclb:         [FAIL][51] ([fdo#111329]) -> [SKIP][52] ([fdo#109276])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-iclb2/igt@gem_ctx_isolation@vcs1-nonpriv.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/shard-iclb7/igt@gem_ctx_isolation@vcs1-nonpriv.html

  * igt@gem_mocs_settings@mocs-rc6-bsd2:
    - shard-iclb:         [SKIP][53] ([fdo#109276]) -> [FAIL][54] ([fdo#111330])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6958/shard-iclb6/igt@gem_mocs_settings@mocs-rc6-bsd2.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/shard-iclb2/igt@gem_mocs_settings@mocs-rc6-bsd2.html

  
  [fdo#100368]: https://bugs.freedesktop.org/show_bug.cgi?id=100368
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#110026]: https://bugs.freedesktop.org/show_bug.cgi?id=110026
  [fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
  [fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
  [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
  [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
  [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (9 -> 9)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6958 -> Patchwork_14539

  CI-20190529: 20190529
  CI_DRM_6958: d5c4d0bc1c0570ba9128e7afb419d5d5a8ebd4bc @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5203: 82326332f7af336d390e00ae87187bc207fd33dd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14539: 56a9c538a831b886c0c2c4b018fec50767d257cc @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14539/
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Re: [PATCH 3/3] drm/i915/tgl: Remove single pipe restriction from SAGV

[James Ausmus]

On Thu, Sep 26, 2019 at 03:34:35PM +0300, Ville Syrjälä wrote:
> On Wed, Sep 25, 2019 at 01:33:52PM -0700, James Ausmus wrote:
> > For Gen12, BSpec no longer tells us to disable SAGV when > 1 pipe is
> > active. Update intel_can_enable_sagv to allow this, and loop through all
> > active planes on all active crtcs to check against the interlaced and
> > latency restrictions.
> > 
> > BSpec: 49325
> > 
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Signed-off-by: James Ausmus <james.ausmus@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_pm.c | 63 +++++++++++++++++----------------
> >  1 file changed, 32 insertions(+), 31 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index ca2bec09edb5..cb50c697a6b8 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3775,7 +3775,6 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
> >  	struct intel_crtc *crtc;
> >  	struct intel_plane *plane;
> >  	struct intel_crtc_state *crtc_state;
> > -	enum pipe pipe;
> >  	int level, latency;
> >  	int sagv_block_time_us;
> >  
> > @@ -3791,47 +3790,49 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
> >  		return true;
> >  
> >  	/*
> > -	 * SKL+ workaround: bspec recommends we disable SAGV when we have
> > +	 * SKL-ICL workaround: bspec recommends we disable SAGV when we have
> >  	 * more then one pipe enabled
> >  	 */
> > -	if (hweight8(state->active_pipes) > 1)
> > +	if (INTEL_GEN(dev_priv) < 12 && hweight8(state->active_pipes) > 1)
> >  		return false;
> >  
> > -	/* Since we're now guaranteed to only have one active CRTC... */
> > -	pipe = ffs(state->active_pipes) - 1;
> > -	crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> > -	crtc_state = to_intel_crtc_state(crtc->base.state);
> > +	for_each_intel_crtc(&dev_priv->drm, crtc) {
> > +		crtc_state = to_intel_crtc_state(crtc->base.state);
> > +		if (!crtc_state->base.active)
> > +			continue;
> >  
> > -	if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> > -		return false;
> > +		if (crtc->base.state->adjusted_mode.flags &
> > +		    DRM_MODE_FLAG_INTERLACE)
> > +			return false;
> >  
> > -	for_each_intel_plane_on_crtc(dev, crtc, plane) {
> > -		struct skl_plane_wm *wm =
> > -			&crtc_state->wm.skl.optimal.planes[plane->id];
> > +		for_each_intel_plane_on_crtc(dev, crtc, plane) {
> > +			struct skl_plane_wm *wm =
> > +				&crtc_state->wm.skl.optimal.planes[plane->id];
> 
> This whole loop is bothering me. I'd much rather we move to a scheme
> where each plane computes it's SAGV friendlyness when computing the
> watermarks. We'll anyway need that since we need to caclulate the
> watermarks differently for the SAGV on vs. off cases.

Hmm, I'll have to look in to this. In the meantime, I'd like to get
patches 1 & 2 of this series moving forward, as those should be what's
really necessary to be able to turn on SAGV for TGL once we're ready, so
I'll send those as a separate series, and leave relaxing the 1 pipe
restriction as it's own work.

-James

> 
> >  
> > -		/* Skip this plane if it's not enabled */
> > -		if (!wm->wm[0].plane_en)
> > -			continue;
> > +			/* Skip this plane if it's not enabled */
> > +			if (!wm->wm[0].plane_en)
> > +				continue;
> >  
> > -		/* Find the highest enabled wm level for this plane */
> > -		for (level = ilk_wm_max_level(dev_priv);
> > -		     !wm->wm[level].plane_en; --level)
> > -		     { }
> > +			/* Find the highest enabled wm level for this plane */
> > +			for (level = ilk_wm_max_level(dev_priv);
> > +			     !wm->wm[level].plane_en; --level)
> > +			     { }
> >  
> > -		latency = dev_priv->wm.skl_latency[level];
> > +			latency = dev_priv->wm.skl_latency[level];
> >  
> > -		if (skl_needs_memory_bw_wa(dev_priv) &&
> > -		    plane->base.state->fb->modifier ==
> > -		    I915_FORMAT_MOD_X_TILED)
> > -			latency += 15;
> > +			if (skl_needs_memory_bw_wa(dev_priv) &&
> > +			    plane->base.state->fb->modifier ==
> > +			    I915_FORMAT_MOD_X_TILED)
> > +				latency += 15;
> >  
> > -		/*
> > -		 * If any of the planes on this pipe don't enable wm levels that
> > -		 * incur memory latencies higher than sagv_block_time_us we
> > -		 * can't enable SAGV.
> > -		 */
> > -		if (latency < sagv_block_time_us)
> > -			return false;
> > +			/*
> > +			 * If any of the planes on this pipe don't enable wm
> > +			 * levels that incur memory latencies higher than
> > +			 * sagv_block_time_us we can't enable SAGV.
> > +			 */
> > +			if (latency < sagv_block_time_us)
> > +				return false;
> > +		}
> >  	}
> >  
> >  	return true;
> > -- 
> > 2.22.1
> 
> -- 
> Ville Syrjälä
> Intel
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Re: [PATCH 1/3] drm/i915: Extract SAGV block time function

[Ville Syrjälä]

On Wed, Sep 25, 2019 at 01:33:50PM -0700, James Ausmus wrote:
> In prep for newer platforms having more complicated ways to determine
> the SAGV block time, extract the setting to a separate function. While
> we're at it, update the if ladder to follow the new gen -> old gen order
> preference, and warn on any non-specified gen.
> 
> Cc: Ville Syrjälä <ville.syrjala@intel.com>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: James Ausmus <james.ausmus@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 24 ++++++++++++++++++------
>  1 file changed, 18 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6bed2ed14574..5ad72dcb0faa 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3662,6 +3662,23 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
>  		dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
>  }
>  
> +static int
> +intel_get_sagv_block_time_us(struct drm_i915_private *dev_priv)

The "_get_" in the name seems a bit superfluous.

> +{
> +	int sagv_block_time_us = 1000; /* Default to unusable block time */
> +
> +	if (IS_GEN(dev_priv, 11))
> +		sagv_block_time_us = 10;
> +	else if (IS_GEN(dev_priv, 10))
> +		sagv_block_time_us = 20;
> +	else if (IS_GEN(dev_priv, 9))
> +		sagv_block_time_us = 30;
> +	else
> +		MISSING_CASE(INTEL_GEN(dev_priv));
> +
> +	return sagv_block_time_us;

Could just return directly w/o the temp variable.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +}
> +
>  /*
>   * SAGV dynamically adjusts the system agent voltage and clock frequencies
>   * depending on power and performance requirements. The display engine access
> @@ -3755,12 +3772,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
>  	if (!intel_has_sagv(dev_priv))
>  		return false;
>  
> -	if (IS_GEN(dev_priv, 9))
> -		sagv_block_time_us = 30;
> -	else if (IS_GEN(dev_priv, 10))
> -		sagv_block_time_us = 20;
> -	else
> -		sagv_block_time_us = 10;
> +	sagv_block_time_us = intel_get_sagv_block_time_us(dev_priv);
>  
>  	/*
>  	 * If there are no active CRTCs, no additional checks need be performed
> -- 
> 2.22.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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Re: [PATCH 2/3] drm/i915/tgl: Read SAGV block time from PCODE

[Ville Syrjälä]

On Wed, Sep 25, 2019 at 01:33:51PM -0700, James Ausmus wrote:
> Starting from TGL, we now need to read the SAGV block time via a PCODE
> mailbox, rather than having a static value.
> 
> BSpec: 49326
> 
> Cc: Ville Syrjälä <ville.syrjala@intel.com>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: James Ausmus <james.ausmus@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |  1 +
>  drivers/gpu/drm/i915/intel_pm.c | 20 +++++++++++++++-----
>  2 files changed, 16 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e752de9470bd..84ae6553485b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8865,6 +8865,7 @@ enum {
>  #define     GEN9_SAGV_DISABLE			0x0
>  #define     GEN9_SAGV_IS_DISABLED		0x1
>  #define     GEN9_SAGV_ENABLE			0x3
> +#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
>  #define GEN6_PCODE_DATA				_MMIO(0x138128)
>  #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
>  #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5ad72dcb0faa..ca2bec09edb5 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3665,16 +3665,26 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
>  static int
>  intel_get_sagv_block_time_us(struct drm_i915_private *dev_priv)
>  {
> -	int sagv_block_time_us = 1000; /* Default to unusable block time */
> +	uint val = 0;

uint?

> +	int ret, sagv_block_time_us = 1000; /* Default to unusable block time */

val+ret could live in a tighter scope.

>  
> -	if (IS_GEN(dev_priv, 11))
> +	if (INTEL_GEN(dev_priv) >= 12) {
> +		ret = sandybridge_pcode_read(dev_priv,
> +					     GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
> +					     &val, NULL);

We should probably stash this somewhere so we don't have to keep
asking pcode about it every single time.

Magic numbers look correct
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> +		if (!ret)
> +			sagv_block_time_us = val;
> +		else
> +			DRM_DEBUG_DRIVER("Couldn't read SAGV block time!\n");
> +	} else if (IS_GEN(dev_priv, 11)) {
>  		sagv_block_time_us = 10;
> -	else if (IS_GEN(dev_priv, 10))
> +	} else if (IS_GEN(dev_priv, 10)) {
>  		sagv_block_time_us = 20;
> -	else if (IS_GEN(dev_priv, 9))
> +	} else if (IS_GEN(dev_priv, 9)) {
>  		sagv_block_time_us = 30;
> -	else
> +	} else {
>  		MISSING_CASE(INTEL_GEN(dev_priv));
> +	}
>  
>  	return sagv_block_time_us;
>  }
> -- 
> 2.22.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
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Intel
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Re: [PATCH 2/3] drm/i915/tgl: Read SAGV block time from PCODE

[Ville Syrjälä]

On Wed, Sep 25, 2019 at 01:33:51PM -0700, James Ausmus wrote:
> Starting from TGL, we now need to read the SAGV block time via a PCODE
> mailbox, rather than having a static value.
> 
> BSpec: 49326
> 
> Cc: Ville Syrjälä <ville.syrjala@intel.com>

Wrong address. I ignore all patches going there, so it's not doing you
any good.

> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: James Ausmus <james.ausmus@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |  1 +
>  drivers/gpu/drm/i915/intel_pm.c | 20 +++++++++++++++-----
>  2 files changed, 16 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e752de9470bd..84ae6553485b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8865,6 +8865,7 @@ enum {
>  #define     GEN9_SAGV_DISABLE			0x0
>  #define     GEN9_SAGV_IS_DISABLED		0x1
>  #define     GEN9_SAGV_ENABLE			0x3
> +#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
>  #define GEN6_PCODE_DATA				_MMIO(0x138128)
>  #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
>  #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5ad72dcb0faa..ca2bec09edb5 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3665,16 +3665,26 @@ intel_has_sagv(struct drm_i915_private *dev_priv)
>  static int
>  intel_get_sagv_block_time_us(struct drm_i915_private *dev_priv)
>  {
> -	int sagv_block_time_us = 1000; /* Default to unusable block time */
> +	uint val = 0;
> +	int ret, sagv_block_time_us = 1000; /* Default to unusable block time */
>  
> -	if (IS_GEN(dev_priv, 11))
> +	if (INTEL_GEN(dev_priv) >= 12) {
> +		ret = sandybridge_pcode_read(dev_priv,
> +					     GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
> +					     &val, NULL);
> +		if (!ret)
> +			sagv_block_time_us = val;
> +		else
> +			DRM_DEBUG_DRIVER("Couldn't read SAGV block time!\n");
> +	} else if (IS_GEN(dev_priv, 11)) {
>  		sagv_block_time_us = 10;
> -	else if (IS_GEN(dev_priv, 10))
> +	} else if (IS_GEN(dev_priv, 10)) {
>  		sagv_block_time_us = 20;
> -	else if (IS_GEN(dev_priv, 9))
> +	} else if (IS_GEN(dev_priv, 9)) {
>  		sagv_block_time_us = 30;
> -	else
> +	} else {
>  		MISSING_CASE(INTEL_GEN(dev_priv));
> +	}
>  
>  	return sagv_block_time_us;
>  }
> -- 
> 2.22.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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