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From: Anshuman Gupta <anshuman.gupta@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com
Subject: [PATCH v10 6/6] drm/i915/tgl: Add DC3CO counter in i915_dmc_info
Date: Mon, 30 Sep 2019 23:11:37 +0530	[thread overview]
Message-ID: <20190930174137.15233-7-anshuman.gupta@intel.com> (raw)
In-Reply-To: <20190930174137.15233-1-anshuman.gupta@intel.com>

Adding DC3CO counter in i915_dmc_info debugfs will be
useful for DC3CO validation.
DMC firmware uses DMC_DEBUG3 register as DC3CO counter
register on TGL, as per B.Specs DMC_DEBUG3 is general
purpose register.

v1: comment modification for DMC_DBUG3.
    using GEN >= 12 check instead of IS_TIGERLAKE()
    to print DMC_DEBUG3 counter value.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 7 +++++++
 drivers/gpu/drm/i915/i915_reg.h     | 2 ++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index b5b449a88cf1..fcccfd4507bd 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2410,6 +2410,13 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 	if (INTEL_GEN(dev_priv) >= 12) {
 		dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
 		dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
+		/*
+		 * NOTE: DMC_DEBUG3 is a general purpose reg.
+		 * According to B.Specs:49196 DMC f/w reuses DC5/6 counter
+		 * reg for DC3CO debugging and validation,
+		 * but TGL DMC f/w is using DMC_DEBUG3 reg for DC3CO counter.
+		 */
+		seq_printf(m, "DC3CO count: %d\n", I915_READ(DMC_DEBUG3));
 	} else {
 		dc5_reg = IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
 						 SKL_CSR_DC3_DC5_COUNT;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3ee9720af207..af810f6ed652 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7263,6 +7263,8 @@ enum {
 #define TGL_DMC_DEBUG_DC5_COUNT	_MMIO(0x101084)
 #define TGL_DMC_DEBUG_DC6_COUNT	_MMIO(0x101088)
 
+#define DMC_DEBUG3		_MMIO(0x101090)
+
 /* interrupts */
 #define DE_MASTER_IRQ_CONTROL   (1 << 31)
 #define DE_SPRITEB_FLIP_DONE    (1 << 29)
-- 
2.21.0

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  parent reply	other threads:[~2019-09-30 17:48 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-30 17:41 [PATCH v10 0/6] DC3CO Support for TGL Anshuman Gupta
2019-09-30 17:41 ` [PATCH v10 1/6] drm/i915/tgl: Add DC3CO required register and bits Anshuman Gupta
2019-09-30 17:41 ` [PATCH v10 2/6] drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask Anshuman Gupta
2019-09-30 17:41 ` [PATCH v10 3/6] drm/i915/tgl: Enable DC3CO state in "DC Off" power well Anshuman Gupta
2019-09-30 17:41 ` [PATCH v10 4/6] drm/i915/tgl: Do modeset to enable and configure DC3CO exitline Anshuman Gupta
2019-10-01  9:17   ` Imre Deak
2019-09-30 17:41 ` [PATCH v10 5/6] drm/i915/tgl: Switch between dc3co and dc5 based on display idleness Anshuman Gupta
2019-10-01  9:32   ` Imre Deak
2019-10-01  9:54   ` Imre Deak
2019-09-30 17:41 ` Anshuman Gupta [this message]
2019-09-30 19:13 ` ✓ Fi.CI.BAT: success for DC3CO Support for TGL (rev13) Patchwork
2019-10-01  0:15 ` ✓ Fi.CI.IGT: " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2019-10-01 14:16 [PATCH v10 0/6] DC3CO Support for TGL Anshuman Gupta
2019-10-01 14:16 ` [PATCH v10 6/6] drm/i915/tgl: Add DC3CO counter in i915_dmc_info Anshuman Gupta
2019-10-03  8:17 [PATCH v10 RESEND 0/6] DC3CO Support for TGL test with DC3CO IGT Anshuman Gupta
2019-10-03  8:17 ` [PATCH v10 6/6] drm/i915/tgl: Add DC3CO counter in i915_dmc_info Anshuman Gupta

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