From: Manasi Navare <manasi.d.navare@intel.com>
To: Animesh Manna <animesh.manna@intel.com>
Cc: jani.nikula@intel.com, intel-gfx@lists.freedesktop.org
Subject: Re: [RFC 6/6] drm/i915/dp: Program vswing, pre-emphasis, test-pattern
Date: Mon, 21 Oct 2019 16:47:12 -0700 [thread overview]
Message-ID: <20191021234712.GD29989@intel.com> (raw)
In-Reply-To: <20191003150653.15881-7-animesh.manna@intel.com>
On Thu, Oct 03, 2019 at 08:36:53PM +0530, Animesh Manna wrote:
> This patch process phy compliance request by programming requested
> vswing, pre-emphasis and test pattern.
So the design of this whole patch will need to be changed to work with the whole kms infrastructure
Basically what you are doing here is handling the HPD test request, getting the test patterns.
populating the intel_dp_compliance phytest struct and also writing the I915 regs right then and there.
This model does not fit the atomic KMS infrastructure, IMO this is how it should look like:
1. Handle the test request
2. Prepare the PHY patterns where you erad the test patterns from DPCD and populate
the intel_dp_compliance phytest struct
3. set test_active = true
4. Now in atomic_commit_tail somewhere just before enabling pipe, is where
based on if intel_dp_compliance.phytest not NULL you will need to call ddi_disable, enable,
set_signal_levels, phy_update on the other hand all teh functions that write data to the
I915 registers will need to happen here.
Clint, Jani N any thoughts here?
Regards
Manasi
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 62 +++++++++++++++++++++++++
> 1 file changed, 62 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 93b1ce80c174..dd4c3a81c11d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4817,14 +4817,76 @@ static inline void intel_dp_phy_pattern_update(struct intel_dp *intel_dp)
> }
> }
>
> +static void
> +intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp)
> +{
> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> + struct drm_device *dev = intel_dig_port->base.base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + enum port port = intel_dig_port->base.port;
> + u32 ddi_buf_ctl_value, dp_tp_ctl_value, trans_ddi_func_ctl_value;
> +
> + ddi_buf_ctl_value = I915_READ(DDI_BUF_CTL(port));
> + dp_tp_ctl_value = I915_READ(DP_TP_CTL(port));
> + trans_ddi_func_ctl_value = I915_READ(TRANS_DDI_FUNC_CTL(port));
> +
> + ddi_buf_ctl_value &= ~(DDI_BUF_CTL_ENABLE | DDI_PORT_WIDTH_MASK);
> + dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
> + trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
> + DDI_PORT_WIDTH_MASK);
> +
> + I915_WRITE(DDI_BUF_CTL(port), ddi_buf_ctl_value);
> + I915_WRITE(DP_TP_CTL(port), dp_tp_ctl_value);
> + I915_WRITE(TRANS_DDI_FUNC_CTL(port), trans_ddi_func_ctl_value);
> +}
> +
> +static void
> +intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, uint8_t lane_cnt)
> +{
> + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> + struct drm_device *dev = intel_dig_port->base.base.dev;
> + struct drm_i915_private *dev_priv = to_i915(dev);
> + enum port port = intel_dig_port->base.port;
> + u32 ddi_buf_ctl_value, dp_tp_ctl_value, trans_ddi_func_ctl_value;
> +
> + ddi_buf_ctl_value = I915_READ(DDI_BUF_CTL(port));
> + dp_tp_ctl_value = I915_READ(DP_TP_CTL(port));
> + trans_ddi_func_ctl_value = I915_READ(TRANS_DDI_FUNC_CTL(port));
> +
> + ddi_buf_ctl_value |= DDI_BUF_CTL_ENABLE |
> + DDI_PORT_WIDTH(lane_cnt);
> + dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
> + trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
> + DDI_PORT_WIDTH(lane_cnt);
> +
> + I915_WRITE(TRANS_DDI_FUNC_CTL(port), trans_ddi_func_ctl_value);
> + I915_WRITE(DP_TP_CTL(port), dp_tp_ctl_value);
> + I915_WRITE(DDI_BUF_CTL(port), ddi_buf_ctl_value);
> +}
> +
> static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
> {
> u8 test_result = DP_TEST_NAK;
> + struct drm_dp_phy_test_params *data =
> + &intel_dp->compliance.test_data.phytest;
>
> test_result = intel_dp_prepare_phytest(intel_dp);
> if (test_result != DP_TEST_ACK)
> DRM_ERROR("Phy test preparation failed\n");
>
> + intel_dp_autotest_phy_ddi_disable(intel_dp);
> +
> + intel_dp_set_signal_levels(intel_dp);
> +
> + intel_dp_phy_pattern_update(intel_dp);
> +
> + intel_dp_autotest_phy_ddi_enable(intel_dp, data->link.num_lanes);
> +
> + drm_dp_set_phy_test_pattern(&intel_dp->aux, data);
> +
> + /* Set test active flag here so userspace doesn't interrupt things */
> + intel_dp->compliance.test_active = 1;
> +
> return test_result;
> }
>
> --
> 2.22.0
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-10-21 23:44 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-03 15:06 [RFC 0/6] DP Phy compliace auto test Animesh Manna
2019-10-03 15:06 ` [RFC 1/6] drm/dp: get/set phy compliance pattern Animesh Manna
2019-10-21 23:27 ` Manasi Navare
2019-10-22 13:29 ` Animesh Manna
2019-11-05 23:12 ` Manasi Navare
2019-11-05 23:12 ` [Intel-gfx] " Manasi Navare
2019-10-03 15:06 ` [RFC 2/6] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation Animesh Manna
2019-10-21 22:57 ` Manasi Navare
2019-10-22 14:04 ` Animesh Manna
2019-10-22 17:40 ` Manasi Navare
2019-10-24 11:45 ` Animesh Manna
2019-10-24 11:45 ` [Intel-gfx] " Animesh Manna
2019-10-03 15:06 ` [RFC 3/6] drm/i915/dp: Preparation for DP phy compliance auto test Animesh Manna
2019-10-21 23:29 ` Manasi Navare
2019-10-22 14:12 ` Animesh Manna
2019-10-03 15:06 ` [RFC 4/6] drm/i915/dp: Register definition for DP compliance register Animesh Manna
2019-10-03 15:06 ` [RFC 5/6] drm/i915/dp: Update the pattern as per request Animesh Manna
2019-10-03 15:06 ` [RFC 6/6] drm/i915/dp: Program vswing, pre-emphasis, test-pattern Animesh Manna
2019-10-21 23:47 ` Manasi Navare [this message]
2019-10-22 15:07 ` Animesh Manna
2019-10-22 18:41 ` Manasi Navare
2019-10-03 17:36 ` ✓ Fi.CI.BAT: success for DP Phy compliace auto test Patchwork
2019-10-04 3:07 ` ✗ Fi.CI.IGT: failure " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20191021234712.GD29989@intel.com \
--to=manasi.d.navare@intel.com \
--cc=animesh.manna@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=jani.nikula@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox