From: Animesh Manna <animesh.manna@intel.com>
To: Manasi Navare <manasi.d.navare@intel.com>
Cc: jani.nikula@intel.com, intel-gfx@lists.freedesktop.org
Subject: Re: [RFC 1/6] drm/dp: get/set phy compliance pattern.
Date: Tue, 22 Oct 2019 18:59:30 +0530 [thread overview]
Message-ID: <f9d7f82e-be76-a35e-efed-fd5303f5b4ef@intel.com> (raw)
In-Reply-To: <20191021232701.GB29989@intel.com>
On 10/22/2019 4:57 AM, Manasi Navare wrote:
> On Thu, Oct 03, 2019 at 08:36:48PM +0530, Animesh Manna wrote:
>> During phy complaince auto test mode source need to read
>> requested test pattern from sink through DPCD. After processing
>> the request source need to set the pattern. So set/get method
>> added in drm layer as it is DP protocol.
>>
>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>> ---
>> drivers/gpu/drm/drm_dp_helper.c | 77 +++++++++++++++++++++++++++++++++
>> include/drm/drm_dp_helper.h | 28 ++++++++++++
>> 2 files changed, 105 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
>> index f373798d82f6..3cb7170e55f4 100644
>> --- a/drivers/gpu/drm/drm_dp_helper.c
>> +++ b/drivers/gpu/drm/drm_dp_helper.c
>> @@ -1484,3 +1484,80 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
>> return num_bpc;
>> }
>> EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
>> +
>> +/**
>> + * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
>> + * @aux: DisplayPort AUX channel
>> + * @data: DP phy compliance test parameters.
>> + *
>> + * Returns 0 on success or a negative error code on failure.
>> + */
>> +int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
>> + struct drm_dp_phy_test_params *data)
>> +{
>> + int err;
>> +
>> + err = drm_dp_link_probe(aux, &data->link);
>> + if (err < 0)
>> + return err;
>> +
>> + err = drm_dp_dpcd_read(aux, DP_TEST_PHY_PATTERN, &data->phy_pattern, 1);
> Just use drm_dp_dpcd_readb
Thanks Manasi for code review.
Will add all suggested changes here.
Regards,
Animesh
>
>> + if (err < 0)
>> + return err;
>> +
>> + switch (data->phy_pattern) {
>> + case DP_TEST_PHY_PATTERN_80BIT_CUSTOM:
>> + err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
>> + &data->custom80, 10);
>> + if (err < 0)
>> + return err;
>> +
>> + break;
>> + case DP_TEST_PHY_PATTERN_CP2520:
>> + err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
>> + &data->hbr2_reset, 2);
>> + if (err < 0)
>> + return err;
>> + }
>> +
>> + return 0;
>> +}
>> +EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
>> +
>> +/**
>> + * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
>> + * @aux: DisplayPort AUX channel
>> + * @data: DP phy compliance test parameters.
>> + *
>> + * Returns 0 on success or a negative error code on failure.
>> + */
>> +int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
>> + struct drm_dp_phy_test_params *data)
>> +{
>> + int err, i;
>> + u8 test_pattern;
>> +
>> + err = drm_dp_link_configure(aux, &data->link);
>> + if (err < 0)
>> + return err;
>> +
>> + test_pattern = data->phy_pattern;
>> + if (data->link.revision < 0x12) {
>> + test_pattern = (test_pattern << 2) &
>> + DP_LINK_QUAL_PATTERN_11_MASK;
>> + err = drm_dp_dpcd_write(aux, DP_TRAINING_PATTERN_SET,
>> + &test_pattern, 1);
> Same, just use drm_dp_dpcd_writeb
>
>> + if (err < 0)
>> + return err;
>> + } else {
>> + for (i = 0; i < data->link.num_lanes; i++) {
>> + err = drm_dp_dpcd_write(aux, DP_LINK_QUAL_LANE0_SET + i,
>> + &test_pattern, 1);
>> + if (err < 0)
>> + return err;
>> + }
>> + }
>> +
>> + return 0;
>> +}
>> +EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
>> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
>> index ed1a985745ba..77dcf5879beb 100644
>> --- a/include/drm/drm_dp_helper.h
>> +++ b/include/drm/drm_dp_helper.h
>> @@ -691,6 +691,14 @@
>> # define DP_TEST_COUNT_MASK 0xf
>>
>> #define DP_TEST_PHY_PATTERN 0x248
> This should be consistent with spec name DP_PHY_TEST_PATTERN
>
> And since the bits below are part of the 2:0 PATTERN_SEL, I would prefer
> having DP_PHY_TEST_PATTERN_SEL_MASK 0x7
>
>> +# define DP_TEST_PHY_PATTERN_NONE 0
> ^ 0x0
>> +# define DP_TEST_PHY_PATTERN_D10_2 1
> ^ 0x1 (to be consistent with other bit defs in .h file)
>
> Manasi
>
>> +# define DP_TEST_PHY_PATTERN_ERROR_COUNT 2
>> +# define DP_TEST_PHY_PATTERN_PRBS7 3
>> +# define DP_TEST_PHY_PATTERN_80BIT_CUSTOM 4
>> +# define DP_TEST_PHY_PATTERN_CP2520 5
>> +
>> +#define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
>> #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
>> #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
>> #define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252
>> @@ -1523,4 +1531,24 @@ static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
>>
>> #endif
>>
>> +/**
>> + * struct drm_dp_phy_test_params - DP Phy Compliance parameters
>> + * @link: Link information.
>> + * @phy_pattern: DP Phy test pattern from DPCD 0x248 (sink)
>> + * @hb2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD
>> + * 0x24A and 0x24B (sink)
>> + * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250
>> + * through 0x259.
>> + */
>> +struct drm_dp_phy_test_params {
>> + struct drm_dp_link link;
>> + u8 phy_pattern;
>> + u8 hbr2_reset[2];
>> + u8 custom80[10];
>> +};
>> +
>> +int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
>> + struct drm_dp_phy_test_params *data);
>> +int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
>> + struct drm_dp_phy_test_params *data);
>> #endif /* _DRM_DP_HELPER_H_ */
>> --
>> 2.22.0
>>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-10-22 13:29 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-03 15:06 [RFC 0/6] DP Phy compliace auto test Animesh Manna
2019-10-03 15:06 ` [RFC 1/6] drm/dp: get/set phy compliance pattern Animesh Manna
2019-10-21 23:27 ` Manasi Navare
2019-10-22 13:29 ` Animesh Manna [this message]
2019-11-05 23:12 ` Manasi Navare
2019-11-05 23:12 ` [Intel-gfx] " Manasi Navare
2019-10-03 15:06 ` [RFC 2/6] drm/i915/dp: Move vswing/pre-emphasis adjustment calculation Animesh Manna
2019-10-21 22:57 ` Manasi Navare
2019-10-22 14:04 ` Animesh Manna
2019-10-22 17:40 ` Manasi Navare
2019-10-24 11:45 ` Animesh Manna
2019-10-24 11:45 ` [Intel-gfx] " Animesh Manna
2019-10-03 15:06 ` [RFC 3/6] drm/i915/dp: Preparation for DP phy compliance auto test Animesh Manna
2019-10-21 23:29 ` Manasi Navare
2019-10-22 14:12 ` Animesh Manna
2019-10-03 15:06 ` [RFC 4/6] drm/i915/dp: Register definition for DP compliance register Animesh Manna
2019-10-03 15:06 ` [RFC 5/6] drm/i915/dp: Update the pattern as per request Animesh Manna
2019-10-03 15:06 ` [RFC 6/6] drm/i915/dp: Program vswing, pre-emphasis, test-pattern Animesh Manna
2019-10-21 23:47 ` Manasi Navare
2019-10-22 15:07 ` Animesh Manna
2019-10-22 18:41 ` Manasi Navare
2019-10-03 17:36 ` ✓ Fi.CI.BAT: success for DP Phy compliace auto test Patchwork
2019-10-04 3:07 ` ✗ Fi.CI.IGT: failure " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=f9d7f82e-be76-a35e-efed-fd5303f5b4ef@intel.com \
--to=animesh.manna@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=jani.nikula@intel.com \
--cc=manasi.d.navare@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox