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From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 2/2] drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
Date: Thu, 24 Oct 2019 13:38:58 +0300	[thread overview]
Message-ID: <20191024103858.28113-2-mika.kuoppala@linux.intel.com> (raw)
In-Reply-To: <20191024103858.28113-1-mika.kuoppala@linux.intel.com>

From: Tapani Pälli <tapani.palli@intel.com>

As with commit 3fe0107e45ab, this change fixes multiple tests that are
using the invocation counts. Documentation doesn't list the workaround
for TGL but applying it fixes the tests.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index af8a8183154a..86ded203b2dd 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1215,6 +1215,26 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
 
 static void tgl_whitelist_build(struct intel_engine_cs *engine)
 {
+	struct i915_wa_list *w = &engine->whitelist;
+
+	switch (engine->class) {
+	case RENDER_CLASS:
+		/*
+		 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl
+		 *
+		 * This covers 4 registers which are next to one another :
+		 *   - PS_INVOCATION_COUNT
+		 *   - PS_INVOCATION_COUNT_UDW
+		 *   - PS_DEPTH_COUNT
+		 *   - PS_DEPTH_COUNT_UDW
+		 */
+		whitelist_reg_ext(w, PS_INVOCATION_COUNT,
+				  RING_FORCE_TO_NONPRIV_ACCESS_RD |
+				  RING_FORCE_TO_NONPRIV_RANGE_4);
+		break;
+	default:
+		break;
+	}
 }
 
 void intel_engine_init_whitelist(struct intel_engine_cs *engine)
-- 
2.17.1

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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 2/2] drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT
Date: Thu, 24 Oct 2019 13:38:58 +0300	[thread overview]
Message-ID: <20191024103858.28113-2-mika.kuoppala@linux.intel.com> (raw)
Message-ID: <20191024103858.zqY0g9YSo3fAU9ihfXJbquFgSyMKLo-kYgFxOSsdzcY@z> (raw)
In-Reply-To: <20191024103858.28113-1-mika.kuoppala@linux.intel.com>

From: Tapani Pälli <tapani.palli@intel.com>

As with commit 3fe0107e45ab, this change fixes multiple tests that are
using the invocation counts. Documentation doesn't list the workaround
for TGL but applying it fixes the tests.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index af8a8183154a..86ded203b2dd 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1215,6 +1215,26 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
 
 static void tgl_whitelist_build(struct intel_engine_cs *engine)
 {
+	struct i915_wa_list *w = &engine->whitelist;
+
+	switch (engine->class) {
+	case RENDER_CLASS:
+		/*
+		 * WaAllowPMDepthAndInvocationCountAccessFromUMD:tgl
+		 *
+		 * This covers 4 registers which are next to one another :
+		 *   - PS_INVOCATION_COUNT
+		 *   - PS_INVOCATION_COUNT_UDW
+		 *   - PS_DEPTH_COUNT
+		 *   - PS_DEPTH_COUNT_UDW
+		 */
+		whitelist_reg_ext(w, PS_INVOCATION_COUNT,
+				  RING_FORCE_TO_NONPRIV_ACCESS_RD |
+				  RING_FORCE_TO_NONPRIV_RANGE_4);
+		break;
+	default:
+		break;
+	}
 }
 
 void intel_engine_init_whitelist(struct intel_engine_cs *engine)
-- 
2.17.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2019-10-24 10:39 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-24 10:38 [PATCH 1/2] drm/i915: Remove nonpriv flags when srm/lrm Mika Kuoppala
2019-10-24 10:38 ` [Intel-gfx] " Mika Kuoppala
2019-10-24 10:38 ` Mika Kuoppala [this message]
2019-10-24 10:38   ` [Intel-gfx] [PATCH 2/2] drm/i915/tgl: whitelist PS_(DEPTH|INVOCATION)_COUNT Mika Kuoppala
2019-10-24 10:52 ` [PATCH 1/2] drm/i915: Remove nonpriv flags when srm/lrm Lionel Landwerlin
2019-10-24 10:52   ` [Intel-gfx] " Lionel Landwerlin
2019-10-24 11:03 ` Mika Kuoppala
2019-10-24 11:03   ` [Intel-gfx] " Mika Kuoppala
2019-10-24 11:37   ` Chris Wilson
2019-10-24 11:37     ` [Intel-gfx] " Chris Wilson
2019-10-24 15:23     ` Lionel Landwerlin
2019-10-24 15:23       ` [Intel-gfx] " Lionel Landwerlin
2019-10-24 22:36       ` Chris Wilson
2019-10-24 22:36         ` [Intel-gfx] " Chris Wilson
2019-10-24 15:29 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Remove nonpriv flags when srm/lrm (rev2) Patchwork
2019-10-24 15:29   ` [Intel-gfx] " Patchwork
2019-10-24 15:58 ` ✓ Fi.CI.BAT: success " Patchwork
2019-10-24 15:58   ` [Intel-gfx] " Patchwork
2019-10-25 23:17 ` ✓ Fi.CI.IGT: " Patchwork
2019-10-25 23:17   ` [Intel-gfx] " Patchwork

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