* [Intel-gfx] [PATCH 02/20] drm/i915/perf: Mark up the racy use of perf->exclusive_stream
2020-02-27 8:57 [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits Chris Wilson
@ 2020-02-27 8:57 ` Chris Wilson
2020-02-27 8:57 ` [Intel-gfx] [PATCH 03/20] drm/i915/perf: Manually acquire engine-wakeref around use of kernel_context Chris Wilson
` (24 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Chris Wilson @ 2020-02-27 8:57 UTC (permalink / raw)
To: intel-gfx
Inside the general i915_oa_init_reg_state() we avoid using the
perf->mutex. However, we rely on perf->exclusive_stream being valid to
access at that point, and for that we have to control the race with
disabling perf. This relies on the disabling being a heavy barrier that
inspects all active contexts, after marking the perf->exclusive_stream
as not available. This should ensure that there are no more concurrent
accesses to the perf->exclusive_stream as we destroy it.
Mark up the races around the perf->exclusive_stream so that they stand
out much more. (And hopefully we will be running kcsan to start
validating that the only races we have are carefully controlled.)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/i915_perf.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index e34c79df6ebc..0838a12e2dc5 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1405,8 +1405,10 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
/*
* Unset exclusive_stream first, it will be checked while disabling
* the metric set on gen8+.
+ *
+ * See i915_oa_init_reg_state() and lrc_configure_all_contexts()
*/
- perf->exclusive_stream = NULL;
+ WRITE_ONCE(perf->exclusive_stream, NULL);
perf->ops.disable_metric_set(stream);
free_oa_buffer(stream);
@@ -2847,7 +2849,7 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
goto err_oa_buf_alloc;
stream->ops = &i915_oa_stream_ops;
- perf->exclusive_stream = stream;
+ WRITE_ONCE(perf->exclusive_stream, stream);
ret = perf->ops.enable_metric_set(stream);
if (ret) {
@@ -2867,7 +2869,7 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
return 0;
err_enable:
- perf->exclusive_stream = NULL;
+ WRITE_ONCE(perf->exclusive_stream, NULL);
perf->ops.disable_metric_set(stream);
free_oa_buffer(stream);
@@ -2893,12 +2895,11 @@ void i915_oa_init_reg_state(const struct intel_context *ce,
{
struct i915_perf_stream *stream;
- /* perf.exclusive_stream serialised by lrc_configure_all_contexts() */
-
if (engine->class != RENDER_CLASS)
return;
- stream = engine->i915->perf.exclusive_stream;
+ /* perf.exclusive_stream serialised by lrc_configure_all_contexts() */
+ stream = READ_ONCE(engine->i915->perf.exclusive_stream);
/*
* For gen12, only CTX_R_PWR_CLK_STATE needs update, but the caller
* is already doing that, so nothing to be done for gen12 here.
--
2.25.1
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^ permalink raw reply related [flat|nested] 51+ messages in thread* [Intel-gfx] [PATCH 03/20] drm/i915/perf: Manually acquire engine-wakeref around use of kernel_context
2020-02-27 8:57 [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits Chris Wilson
2020-02-27 8:57 ` [Intel-gfx] [PATCH 02/20] drm/i915/perf: Mark up the racy use of perf->exclusive_stream Chris Wilson
@ 2020-02-27 8:57 ` Chris Wilson
2020-02-28 11:53 ` Mika Kuoppala
2020-02-27 8:57 ` [Intel-gfx] [PATCH 04/20] drm/i915/perf: Wait for lrc_reconfigure on disable Chris Wilson
` (23 subsequent siblings)
25 siblings, 1 reply; 51+ messages in thread
From: Chris Wilson @ 2020-02-27 8:57 UTC (permalink / raw)
To: intel-gfx
The engine->kernel_context is a special case for request emission. Since
it is used as the barrier within the engine's wakeref, we must acquire the
wakeref before submitting a request to the kernel_context.
Reported-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/i915_perf.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 0838a12e2dc5..2334c45f1d08 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2196,7 +2196,9 @@ static int gen8_modify_self(struct intel_context *ce,
struct i915_request *rq;
int err;
+ intel_engine_pm_get(ce->engine);
rq = i915_request_create(ce);
+ intel_engine_pm_put(ce->engine);
if (IS_ERR(rq))
return PTR_ERR(rq);
--
2.25.1
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^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH 03/20] drm/i915/perf: Manually acquire engine-wakeref around use of kernel_context
2020-02-27 8:57 ` [Intel-gfx] [PATCH 03/20] drm/i915/perf: Manually acquire engine-wakeref around use of kernel_context Chris Wilson
@ 2020-02-28 11:53 ` Mika Kuoppala
2020-02-28 11:56 ` Chris Wilson
0 siblings, 1 reply; 51+ messages in thread
From: Mika Kuoppala @ 2020-02-28 11:53 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> The engine->kernel_context is a special case for request emission. Since
> it is used as the barrier within the engine's wakeref, we must acquire the
> wakeref before submitting a request to the kernel_context.
I am a bit surprised that the kernel ctx is used in this capacity...
>
> Reported-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_perf.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 0838a12e2dc5..2334c45f1d08 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -2196,7 +2196,9 @@ static int gen8_modify_self(struct intel_context *ce,
> struct i915_request *rq;
> int err;
>
> + intel_engine_pm_get(ce->engine);
> rq = i915_request_create(ce);
> + intel_engine_pm_put(ce->engine);
> if (IS_ERR(rq))
> return PTR_ERR(rq);
>
> --
> 2.25.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [Intel-gfx] [PATCH 03/20] drm/i915/perf: Manually acquire engine-wakeref around use of kernel_context
2020-02-28 11:53 ` Mika Kuoppala
@ 2020-02-28 11:56 ` Chris Wilson
2020-02-28 12:18 ` Mika Kuoppala
0 siblings, 1 reply; 51+ messages in thread
From: Chris Wilson @ 2020-02-28 11:56 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2020-02-28 11:53:06)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
>
> > The engine->kernel_context is a special case for request emission. Since
> > it is used as the barrier within the engine's wakeref, we must acquire the
> > wakeref before submitting a request to the kernel_context.
>
> I am a bit surprised that the kernel ctx is used in this capacity...
I am happy that you are surprised, and I hope you quickly forget and
return to your happy innocence. :)
-Chris
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 51+ messages in thread
* Re: [Intel-gfx] [PATCH 03/20] drm/i915/perf: Manually acquire engine-wakeref around use of kernel_context
2020-02-28 11:56 ` Chris Wilson
@ 2020-02-28 12:18 ` Mika Kuoppala
0 siblings, 0 replies; 51+ messages in thread
From: Mika Kuoppala @ 2020-02-28 12:18 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Quoting Mika Kuoppala (2020-02-28 11:53:06)
>> Chris Wilson <chris@chris-wilson.co.uk> writes:
>>
>> > The engine->kernel_context is a special case for request emission. Since
>> > it is used as the barrier within the engine's wakeref, we must acquire the
>> > wakeref before submitting a request to the kernel_context.
>>
>> I am a bit surprised that the kernel ctx is used in this capacity...
>
> I am happy that you are surprised, and I hope you quickly forget and
> return to your happy innocence. :)
I am surprised in a same way when looking at people who enjoys playing
games with other elemental building blocks...like for example hydrogen.
Yes I am happy to leave the premises. Good luck.
-Mika
> -Chris
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 51+ messages in thread
* [Intel-gfx] [PATCH 04/20] drm/i915/perf: Wait for lrc_reconfigure on disable
2020-02-27 8:57 [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits Chris Wilson
2020-02-27 8:57 ` [Intel-gfx] [PATCH 02/20] drm/i915/perf: Mark up the racy use of perf->exclusive_stream Chris Wilson
2020-02-27 8:57 ` [Intel-gfx] [PATCH 03/20] drm/i915/perf: Manually acquire engine-wakeref around use of kernel_context Chris Wilson
@ 2020-02-27 8:57 ` Chris Wilson
2020-02-27 11:17 ` [Intel-gfx] [PATCH] " Chris Wilson
2020-02-27 8:57 ` [Intel-gfx] [PATCH 05/20] drm/i915/gem: Consolidate ctx->engines[] release Chris Wilson
` (22 subsequent siblings)
25 siblings, 1 reply; 51+ messages in thread
From: Chris Wilson @ 2020-02-27 8:57 UTC (permalink / raw)
To: intel-gfx
Wait for the last request (and so waits for all context updates) when
disabling OA. This prevents a rather bizarre error seen on Skylake
where the context is subsequently corrupted. Let's play safe and assume
it may impact all.
Reported-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/i915_perf.c | 23 +++++++++++++++++------
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2334c45f1d08..20c68b5dea63 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2191,7 +2191,8 @@ static int gen8_modify_context(struct intel_context *ce,
}
static int gen8_modify_self(struct intel_context *ce,
- const struct flex *flex, unsigned int count)
+ const struct flex *flex, unsigned int count,
+ bool sync)
{
struct i915_request *rq;
int err;
@@ -2204,7 +2205,12 @@ static int gen8_modify_self(struct intel_context *ce,
err = gen8_load_flex(rq, ce, flex, count);
+ i915_request_get(rq);
i915_request_add(rq);
+ if (sync && i915_request_wait(rq, 0, HZ) < 0)
+ err = -ETIME;
+ i915_request_put(rq);
+
return err;
}
@@ -2281,7 +2287,7 @@ static int gen12_configure_oar_context(struct i915_perf_stream *stream, bool ena
return err;
/* Apply regs_lri using LRI with pinned context */
- return gen8_modify_self(ce, regs_lri, ARRAY_SIZE(regs_lri));
+ return gen8_modify_self(ce, regs_lri, ARRAY_SIZE(regs_lri), false);
}
/*
@@ -2311,7 +2317,8 @@ static int gen12_configure_oar_context(struct i915_perf_stream *stream, bool ena
*/
static int oa_configure_all_contexts(struct i915_perf_stream *stream,
struct flex *regs,
- size_t num_regs)
+ size_t num_regs,
+ bool enable)
{
struct drm_i915_private *i915 = stream->perf->i915;
struct intel_engine_cs *engine;
@@ -2368,7 +2375,7 @@ static int oa_configure_all_contexts(struct i915_perf_stream *stream,
regs[0].value = intel_sseu_make_rpcs(i915, &ce->sseu);
- err = gen8_modify_self(ce, regs, num_regs);
+ err = gen8_modify_self(ce, regs, num_regs, !enable);
if (err)
return err;
}
@@ -2386,7 +2393,9 @@ static int gen12_configure_all_contexts(struct i915_perf_stream *stream,
},
};
- return oa_configure_all_contexts(stream, regs, ARRAY_SIZE(regs));
+ return oa_configure_all_contexts(stream,
+ regs, ARRAY_SIZE(regs),
+ oa_config);
}
static int lrc_configure_all_contexts(struct i915_perf_stream *stream,
@@ -2423,7 +2432,9 @@ static int lrc_configure_all_contexts(struct i915_perf_stream *stream,
for (i = 2; i < ARRAY_SIZE(regs); i++)
regs[i].value = oa_config_flex_reg(oa_config, regs[i].reg);
- return oa_configure_all_contexts(stream, regs, ARRAY_SIZE(regs));
+ return oa_configure_all_contexts(stream,
+ regs, ARRAY_SIZE(regs),
+ oa_config);
}
static int gen8_enable_metric_set(struct i915_perf_stream *stream)
--
2.25.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 51+ messages in thread* [Intel-gfx] [PATCH] drm/i915/perf: Wait for lrc_reconfigure on disable
2020-02-27 8:57 ` [Intel-gfx] [PATCH 04/20] drm/i915/perf: Wait for lrc_reconfigure on disable Chris Wilson
@ 2020-02-27 11:17 ` Chris Wilson
0 siblings, 0 replies; 51+ messages in thread
From: Chris Wilson @ 2020-02-27 11:17 UTC (permalink / raw)
To: intel-gfx
Wait for the last request (and so waits for all context updates) when
disabling OA. This prevents a rather bizarre error seen on Skylake
where the context is subsequently corrupted. Let's play safe and assume
it may impact all.
Reported-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
Drop the notion of timeout, waiting appears critical.
---
drivers/gpu/drm/i915/i915_perf.c | 23 +++++++++++++++++------
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 2334c45f1d08..bb380b0c4501 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2191,7 +2191,8 @@ static int gen8_modify_context(struct intel_context *ce,
}
static int gen8_modify_self(struct intel_context *ce,
- const struct flex *flex, unsigned int count)
+ const struct flex *flex, unsigned int count,
+ bool sync)
{
struct i915_request *rq;
int err;
@@ -2204,7 +2205,12 @@ static int gen8_modify_self(struct intel_context *ce,
err = gen8_load_flex(rq, ce, flex, count);
+ i915_request_get(rq);
i915_request_add(rq);
+ if (sync && i915_request_wait(rq, 0, MAX_SCHEDULE_TIMEOUT) < 0)
+ err = -ETIME;
+ i915_request_put(rq);
+
return err;
}
@@ -2281,7 +2287,7 @@ static int gen12_configure_oar_context(struct i915_perf_stream *stream, bool ena
return err;
/* Apply regs_lri using LRI with pinned context */
- return gen8_modify_self(ce, regs_lri, ARRAY_SIZE(regs_lri));
+ return gen8_modify_self(ce, regs_lri, ARRAY_SIZE(regs_lri), false);
}
/*
@@ -2311,7 +2317,8 @@ static int gen12_configure_oar_context(struct i915_perf_stream *stream, bool ena
*/
static int oa_configure_all_contexts(struct i915_perf_stream *stream,
struct flex *regs,
- size_t num_regs)
+ size_t num_regs,
+ bool enable)
{
struct drm_i915_private *i915 = stream->perf->i915;
struct intel_engine_cs *engine;
@@ -2368,7 +2375,7 @@ static int oa_configure_all_contexts(struct i915_perf_stream *stream,
regs[0].value = intel_sseu_make_rpcs(i915, &ce->sseu);
- err = gen8_modify_self(ce, regs, num_regs);
+ err = gen8_modify_self(ce, regs, num_regs, !enable);
if (err)
return err;
}
@@ -2386,7 +2393,9 @@ static int gen12_configure_all_contexts(struct i915_perf_stream *stream,
},
};
- return oa_configure_all_contexts(stream, regs, ARRAY_SIZE(regs));
+ return oa_configure_all_contexts(stream,
+ regs, ARRAY_SIZE(regs),
+ oa_config);
}
static int lrc_configure_all_contexts(struct i915_perf_stream *stream,
@@ -2423,7 +2432,9 @@ static int lrc_configure_all_contexts(struct i915_perf_stream *stream,
for (i = 2; i < ARRAY_SIZE(regs); i++)
regs[i].value = oa_config_flex_reg(oa_config, regs[i].reg);
- return oa_configure_all_contexts(stream, regs, ARRAY_SIZE(regs));
+ return oa_configure_all_contexts(stream,
+ regs, ARRAY_SIZE(regs),
+ oa_config);
}
static int gen8_enable_metric_set(struct i915_perf_stream *stream)
--
2.25.1
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^ permalink raw reply related [flat|nested] 51+ messages in thread
* [Intel-gfx] [PATCH 05/20] drm/i915/gem: Consolidate ctx->engines[] release
2020-02-27 8:57 [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits Chris Wilson
` (2 preceding siblings ...)
2020-02-27 8:57 ` [Intel-gfx] [PATCH 04/20] drm/i915/perf: Wait for lrc_reconfigure on disable Chris Wilson
@ 2020-02-27 8:57 ` Chris Wilson
2020-02-27 9:51 ` [Intel-gfx] [PATCH] " Chris Wilson
2020-02-27 11:01 ` Chris Wilson
2020-02-27 8:57 ` [Intel-gfx] [PATCH 06/20] drm/i915/gt: Prevent allocation on a banned context Chris Wilson
` (21 subsequent siblings)
25 siblings, 2 replies; 51+ messages in thread
From: Chris Wilson @ 2020-02-27 8:57 UTC (permalink / raw)
To: intel-gfx
Use the same engine_idle_release() routine for cleaning all old
ctx->engine[] state, closing any potential races with concurrent execbuf
submission.
v2ish: Use the ce->pin_count to close the execbuf gap.
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1241
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 189 ++++++++++----------
drivers/gpu/drm/i915/gem/i915_gem_context.h | 1 -
2 files changed, 98 insertions(+), 92 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index e525ead073f7..46e5e6116b7f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -242,7 +242,6 @@ static void __free_engines(struct i915_gem_engines *e, unsigned int count)
if (!e->engines[count])
continue;
- RCU_INIT_POINTER(e->engines[count]->gem_context, NULL);
intel_context_put(e->engines[count]);
}
kfree(e);
@@ -255,7 +254,11 @@ static void free_engines(struct i915_gem_engines *e)
static void free_engines_rcu(struct rcu_head *rcu)
{
- free_engines(container_of(rcu, struct i915_gem_engines, rcu));
+ struct i915_gem_engines *engines =
+ container_of(rcu, struct i915_gem_engines, rcu);
+
+ i915_sw_fence_fini(&engines->fence);
+ free_engines(engines);
}
static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx)
@@ -269,8 +272,6 @@ static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx)
if (!e)
return ERR_PTR(-ENOMEM);
- e->ctx = ctx;
-
for_each_engine(engine, gt, id) {
struct intel_context *ce;
@@ -304,7 +305,6 @@ static void i915_gem_context_free(struct i915_gem_context *ctx)
list_del(&ctx->link);
spin_unlock(&ctx->i915->gem.contexts.lock);
- free_engines(rcu_access_pointer(ctx->engines));
mutex_destroy(&ctx->engines_mutex);
if (ctx->timeline)
@@ -491,30 +491,100 @@ static void kill_engines(struct i915_gem_engines *engines)
static void kill_stale_engines(struct i915_gem_context *ctx)
{
struct i915_gem_engines *pos, *next;
- unsigned long flags;
- spin_lock_irqsave(&ctx->stale.lock, flags);
+ spin_lock_irq(&ctx->stale.lock);
+ GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
list_for_each_entry_safe(pos, next, &ctx->stale.engines, link) {
- if (!i915_sw_fence_await(&pos->fence))
+ if (!i915_sw_fence_await(&pos->fence)) {
+ list_del_init(&pos->link);
continue;
+ }
- spin_unlock_irqrestore(&ctx->stale.lock, flags);
+ spin_unlock_irq(&ctx->stale.lock);
kill_engines(pos);
- spin_lock_irqsave(&ctx->stale.lock, flags);
+ spin_lock_irq(&ctx->stale.lock);
+ GEM_BUG_ON(i915_sw_fence_signaled(&pos->fence));
list_safe_reset_next(pos, next, link);
list_del_init(&pos->link); /* decouple from FENCE_COMPLETE */
i915_sw_fence_complete(&pos->fence);
}
- spin_unlock_irqrestore(&ctx->stale.lock, flags);
+ spin_unlock_irq(&ctx->stale.lock);
}
static void kill_context(struct i915_gem_context *ctx)
{
kill_stale_engines(ctx);
- kill_engines(__context_engines_static(ctx));
+}
+
+static int engines_notify(struct i915_sw_fence *fence,
+ enum i915_sw_fence_notify state)
+{
+ struct i915_gem_engines *engines =
+ container_of(fence, typeof(*engines), fence);
+
+ switch (state) {
+ case FENCE_COMPLETE:
+ if (!list_empty(&engines->link)) {
+ struct i915_gem_context *ctx = engines->ctx;
+ unsigned long flags;
+
+ spin_lock_irqsave(&ctx->stale.lock, flags);
+ list_del(&engines->link);
+ spin_unlock_irqrestore(&ctx->stale.lock, flags);
+ }
+ i915_gem_context_put(engines->ctx);
+ break;
+
+ case FENCE_FREE:
+ init_rcu_head(&engines->rcu);
+ call_rcu(&engines->rcu, free_engines_rcu);
+ break;
+ }
+
+ return NOTIFY_DONE;
+}
+
+static void engines_idle_release(struct i915_gem_context *ctx,
+ struct i915_gem_engines *engines)
+{
+ struct i915_gem_engines_iter it;
+ struct intel_context *ce;
+
+ i915_sw_fence_init(&engines->fence, engines_notify);
+ INIT_LIST_HEAD(&engines->link);
+
+ engines->ctx = i915_gem_context_get(ctx);
+
+ for_each_gem_engine(ce, engines, it) {
+ struct dma_fence *fence;
+ int err = 0;
+
+ /* serialises with execbuf */
+ RCU_INIT_POINTER(ce->gem_context, NULL);
+ fence = i915_active_fence_get(&ce->timeline->last_request);
+ if (fence) {
+ err = i915_sw_fence_await_dma_fence(&engines->fence,
+ fence, 0,
+ GFP_KERNEL);
+ dma_fence_put(fence);
+ }
+ if (err < 0)
+ goto kill;
+ }
+
+ spin_lock_irq(&engines->ctx->stale.lock);
+ if (!i915_gem_context_is_closed(engines->ctx))
+ list_add_tail(&engines->link, &engines->ctx->stale.engines);
+ spin_unlock_irq(&engines->ctx->stale.lock);
+
+kill:
+ if (list_empty(&engines->link)) /* raced, already closed */
+ kill_engines(engines);
+
+ i915_sw_fence_commit(&engines->fence);
}
static void set_closed_name(struct i915_gem_context *ctx)
@@ -538,11 +608,16 @@ static void context_close(struct i915_gem_context *ctx)
{
struct i915_address_space *vm;
+ /* Flush any concurrent set_engines() */
+ mutex_lock(&ctx->engines_mutex);
+ engines_idle_release(ctx, rcu_replace_pointer(ctx->engines, NULL, 1));
i915_gem_context_set_closed(ctx);
- set_closed_name(ctx);
+ mutex_unlock(&ctx->engines_mutex);
mutex_lock(&ctx->mutex);
+ set_closed_name(ctx);
+
vm = i915_gem_context_vm(ctx);
if (vm)
i915_vm_close(vm);
@@ -1626,77 +1701,6 @@ static const i915_user_extension_fn set_engines__extensions[] = {
[I915_CONTEXT_ENGINES_EXT_BOND] = set_engines__bond,
};
-static int engines_notify(struct i915_sw_fence *fence,
- enum i915_sw_fence_notify state)
-{
- struct i915_gem_engines *engines =
- container_of(fence, typeof(*engines), fence);
-
- switch (state) {
- case FENCE_COMPLETE:
- if (!list_empty(&engines->link)) {
- struct i915_gem_context *ctx = engines->ctx;
- unsigned long flags;
-
- spin_lock_irqsave(&ctx->stale.lock, flags);
- list_del(&engines->link);
- spin_unlock_irqrestore(&ctx->stale.lock, flags);
- }
- break;
-
- case FENCE_FREE:
- init_rcu_head(&engines->rcu);
- call_rcu(&engines->rcu, free_engines_rcu);
- break;
- }
-
- return NOTIFY_DONE;
-}
-
-static void engines_idle_release(struct i915_gem_engines *engines)
-{
- struct i915_gem_engines_iter it;
- struct intel_context *ce;
- unsigned long flags;
-
- GEM_BUG_ON(!engines);
- i915_sw_fence_init(&engines->fence, engines_notify);
-
- INIT_LIST_HEAD(&engines->link);
- spin_lock_irqsave(&engines->ctx->stale.lock, flags);
- if (!i915_gem_context_is_closed(engines->ctx))
- list_add(&engines->link, &engines->ctx->stale.engines);
- spin_unlock_irqrestore(&engines->ctx->stale.lock, flags);
- if (list_empty(&engines->link)) /* raced, already closed */
- goto kill;
-
- for_each_gem_engine(ce, engines, it) {
- struct dma_fence *fence;
- int err;
-
- if (!ce->timeline)
- continue;
-
- fence = i915_active_fence_get(&ce->timeline->last_request);
- if (!fence)
- continue;
-
- err = i915_sw_fence_await_dma_fence(&engines->fence,
- fence, 0,
- GFP_KERNEL);
-
- dma_fence_put(fence);
- if (err < 0)
- goto kill;
- }
- goto out;
-
-kill:
- kill_engines(engines);
-out:
- i915_sw_fence_commit(&engines->fence);
-}
-
static int
set_engines(struct i915_gem_context *ctx,
const struct drm_i915_gem_context_param *args)
@@ -1739,8 +1743,6 @@ set_engines(struct i915_gem_context *ctx,
if (!set.engines)
return -ENOMEM;
- set.engines->ctx = ctx;
-
for (n = 0; n < num_engines; n++) {
struct i915_engine_class_instance ci;
struct intel_engine_cs *engine;
@@ -1793,6 +1795,11 @@ set_engines(struct i915_gem_context *ctx,
replace:
mutex_lock(&ctx->engines_mutex);
+ if (i915_gem_context_is_closed(ctx)) {
+ mutex_unlock(&ctx->engines_mutex);
+ free_engines(set.engines);
+ return -ENOENT;
+ }
if (args->size)
i915_gem_context_set_user_engines(ctx);
else
@@ -1801,7 +1808,7 @@ set_engines(struct i915_gem_context *ctx,
mutex_unlock(&ctx->engines_mutex);
/* Keep track of old engine sets for kill_context() */
- engines_idle_release(set.engines);
+ engines_idle_release(ctx, set.engines);
return 0;
}
@@ -2077,8 +2084,6 @@ static int clone_engines(struct i915_gem_context *dst,
if (!clone)
goto err_unlock;
- clone->ctx = dst;
-
for (n = 0; n < e->num_engines; n++) {
struct intel_engine_cs *engine;
@@ -2121,8 +2126,7 @@ static int clone_engines(struct i915_gem_context *dst,
i915_gem_context_unlock_engines(src);
/* Serialised by constructor */
- free_engines(__context_engines_static(dst));
- RCU_INIT_POINTER(dst->engines, clone);
+ engines_idle_release(dst, rcu_replace_pointer(dst->engines, clone, 1));
if (user_engines)
i915_gem_context_set_user_engines(dst);
else
@@ -2553,6 +2557,9 @@ i915_gem_engines_iter_next(struct i915_gem_engines_iter *it)
const struct i915_gem_engines *e = it->engines;
struct intel_context *ctx;
+ if (unlikely(!e))
+ return NULL;
+
do {
if (it->idx >= e->num_engines)
return NULL;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index 3ae61a355d87..57b7ae2893e1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -207,7 +207,6 @@ static inline void
i915_gem_engines_iter_init(struct i915_gem_engines_iter *it,
struct i915_gem_engines *engines)
{
- GEM_BUG_ON(!engines);
it->engines = engines;
it->idx = 0;
}
--
2.25.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 51+ messages in thread* [Intel-gfx] [PATCH] drm/i915/gem: Consolidate ctx->engines[] release
2020-02-27 8:57 ` [Intel-gfx] [PATCH 05/20] drm/i915/gem: Consolidate ctx->engines[] release Chris Wilson
@ 2020-02-27 9:51 ` Chris Wilson
2020-02-27 11:01 ` Chris Wilson
1 sibling, 0 replies; 51+ messages in thread
From: Chris Wilson @ 2020-02-27 9:51 UTC (permalink / raw)
To: intel-gfx
Use the same engine_idle_release() routine for cleaning all old
ctx->engine[] state, closing any potential races with concurrent execbuf
submission.
v2ish: Use the ce->pin_count to close the execbuf gap.
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1241
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
Put the pin_if_active check back!
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 193 +++++++++++---------
drivers/gpu/drm/i915/gem/i915_gem_context.h | 1 -
2 files changed, 102 insertions(+), 92 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index e525ead073f7..8e2f8ab8ce6e 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -242,7 +242,6 @@ static void __free_engines(struct i915_gem_engines *e, unsigned int count)
if (!e->engines[count])
continue;
- RCU_INIT_POINTER(e->engines[count]->gem_context, NULL);
intel_context_put(e->engines[count]);
}
kfree(e);
@@ -255,7 +254,11 @@ static void free_engines(struct i915_gem_engines *e)
static void free_engines_rcu(struct rcu_head *rcu)
{
- free_engines(container_of(rcu, struct i915_gem_engines, rcu));
+ struct i915_gem_engines *engines =
+ container_of(rcu, struct i915_gem_engines, rcu);
+
+ i915_sw_fence_fini(&engines->fence);
+ free_engines(engines);
}
static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx)
@@ -269,8 +272,6 @@ static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx)
if (!e)
return ERR_PTR(-ENOMEM);
- e->ctx = ctx;
-
for_each_engine(engine, gt, id) {
struct intel_context *ce;
@@ -304,7 +305,6 @@ static void i915_gem_context_free(struct i915_gem_context *ctx)
list_del(&ctx->link);
spin_unlock(&ctx->i915->gem.contexts.lock);
- free_engines(rcu_access_pointer(ctx->engines));
mutex_destroy(&ctx->engines_mutex);
if (ctx->timeline)
@@ -491,30 +491,104 @@ static void kill_engines(struct i915_gem_engines *engines)
static void kill_stale_engines(struct i915_gem_context *ctx)
{
struct i915_gem_engines *pos, *next;
- unsigned long flags;
- spin_lock_irqsave(&ctx->stale.lock, flags);
+ spin_lock_irq(&ctx->stale.lock);
+ GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
list_for_each_entry_safe(pos, next, &ctx->stale.engines, link) {
- if (!i915_sw_fence_await(&pos->fence))
+ if (!i915_sw_fence_await(&pos->fence)) {
+ list_del_init(&pos->link);
continue;
+ }
- spin_unlock_irqrestore(&ctx->stale.lock, flags);
+ spin_unlock_irq(&ctx->stale.lock);
kill_engines(pos);
- spin_lock_irqsave(&ctx->stale.lock, flags);
+ spin_lock_irq(&ctx->stale.lock);
+ GEM_BUG_ON(i915_sw_fence_signaled(&pos->fence));
list_safe_reset_next(pos, next, link);
list_del_init(&pos->link); /* decouple from FENCE_COMPLETE */
i915_sw_fence_complete(&pos->fence);
}
- spin_unlock_irqrestore(&ctx->stale.lock, flags);
+ spin_unlock_irq(&ctx->stale.lock);
}
static void kill_context(struct i915_gem_context *ctx)
{
kill_stale_engines(ctx);
- kill_engines(__context_engines_static(ctx));
+}
+
+static int engines_notify(struct i915_sw_fence *fence,
+ enum i915_sw_fence_notify state)
+{
+ struct i915_gem_engines *engines =
+ container_of(fence, typeof(*engines), fence);
+
+ switch (state) {
+ case FENCE_COMPLETE:
+ if (!list_empty(&engines->link)) {
+ struct i915_gem_context *ctx = engines->ctx;
+ unsigned long flags;
+
+ spin_lock_irqsave(&ctx->stale.lock, flags);
+ list_del(&engines->link);
+ spin_unlock_irqrestore(&ctx->stale.lock, flags);
+ }
+ i915_gem_context_put(engines->ctx);
+ break;
+
+ case FENCE_FREE:
+ init_rcu_head(&engines->rcu);
+ call_rcu(&engines->rcu, free_engines_rcu);
+ break;
+ }
+
+ return NOTIFY_DONE;
+}
+
+static void engines_idle_release(struct i915_gem_context *ctx,
+ struct i915_gem_engines *engines)
+{
+ struct i915_gem_engines_iter it;
+ struct intel_context *ce;
+
+ i915_sw_fence_init(&engines->fence, engines_notify);
+ INIT_LIST_HEAD(&engines->link);
+
+ engines->ctx = i915_gem_context_get(ctx);
+
+ for_each_gem_engine(ce, engines, it) {
+ struct dma_fence *fence;
+ int err = 0;
+
+ /* serialises with execbuf */
+ RCU_INIT_POINTER(ce->gem_context, NULL);
+ if (!intel_context_pin_if_active(ce))
+ continue;
+
+ fence = i915_active_fence_get(&ce->timeline->last_request);
+ if (fence) {
+ err = i915_sw_fence_await_dma_fence(&engines->fence,
+ fence, 0,
+ GFP_KERNEL);
+ dma_fence_put(fence);
+ }
+ intel_context_unpin(ce);
+ if (err < 0)
+ goto kill;
+ }
+
+ spin_lock_irq(&engines->ctx->stale.lock);
+ if (!i915_gem_context_is_closed(engines->ctx))
+ list_add_tail(&engines->link, &engines->ctx->stale.engines);
+ spin_unlock_irq(&engines->ctx->stale.lock);
+
+kill:
+ if (list_empty(&engines->link)) /* raced, already closed */
+ kill_engines(engines);
+
+ i915_sw_fence_commit(&engines->fence);
}
static void set_closed_name(struct i915_gem_context *ctx)
@@ -538,11 +612,16 @@ static void context_close(struct i915_gem_context *ctx)
{
struct i915_address_space *vm;
+ /* Flush any concurrent set_engines() */
+ mutex_lock(&ctx->engines_mutex);
+ engines_idle_release(ctx, rcu_replace_pointer(ctx->engines, NULL, 1));
i915_gem_context_set_closed(ctx);
- set_closed_name(ctx);
+ mutex_unlock(&ctx->engines_mutex);
mutex_lock(&ctx->mutex);
+ set_closed_name(ctx);
+
vm = i915_gem_context_vm(ctx);
if (vm)
i915_vm_close(vm);
@@ -1626,77 +1705,6 @@ static const i915_user_extension_fn set_engines__extensions[] = {
[I915_CONTEXT_ENGINES_EXT_BOND] = set_engines__bond,
};
-static int engines_notify(struct i915_sw_fence *fence,
- enum i915_sw_fence_notify state)
-{
- struct i915_gem_engines *engines =
- container_of(fence, typeof(*engines), fence);
-
- switch (state) {
- case FENCE_COMPLETE:
- if (!list_empty(&engines->link)) {
- struct i915_gem_context *ctx = engines->ctx;
- unsigned long flags;
-
- spin_lock_irqsave(&ctx->stale.lock, flags);
- list_del(&engines->link);
- spin_unlock_irqrestore(&ctx->stale.lock, flags);
- }
- break;
-
- case FENCE_FREE:
- init_rcu_head(&engines->rcu);
- call_rcu(&engines->rcu, free_engines_rcu);
- break;
- }
-
- return NOTIFY_DONE;
-}
-
-static void engines_idle_release(struct i915_gem_engines *engines)
-{
- struct i915_gem_engines_iter it;
- struct intel_context *ce;
- unsigned long flags;
-
- GEM_BUG_ON(!engines);
- i915_sw_fence_init(&engines->fence, engines_notify);
-
- INIT_LIST_HEAD(&engines->link);
- spin_lock_irqsave(&engines->ctx->stale.lock, flags);
- if (!i915_gem_context_is_closed(engines->ctx))
- list_add(&engines->link, &engines->ctx->stale.engines);
- spin_unlock_irqrestore(&engines->ctx->stale.lock, flags);
- if (list_empty(&engines->link)) /* raced, already closed */
- goto kill;
-
- for_each_gem_engine(ce, engines, it) {
- struct dma_fence *fence;
- int err;
-
- if (!ce->timeline)
- continue;
-
- fence = i915_active_fence_get(&ce->timeline->last_request);
- if (!fence)
- continue;
-
- err = i915_sw_fence_await_dma_fence(&engines->fence,
- fence, 0,
- GFP_KERNEL);
-
- dma_fence_put(fence);
- if (err < 0)
- goto kill;
- }
- goto out;
-
-kill:
- kill_engines(engines);
-out:
- i915_sw_fence_commit(&engines->fence);
-}
-
static int
set_engines(struct i915_gem_context *ctx,
const struct drm_i915_gem_context_param *args)
@@ -1739,8 +1747,6 @@ set_engines(struct i915_gem_context *ctx,
if (!set.engines)
return -ENOMEM;
- set.engines->ctx = ctx;
-
for (n = 0; n < num_engines; n++) {
struct i915_engine_class_instance ci;
struct intel_engine_cs *engine;
@@ -1793,6 +1799,11 @@ set_engines(struct i915_gem_context *ctx,
replace:
mutex_lock(&ctx->engines_mutex);
+ if (i915_gem_context_is_closed(ctx)) {
+ mutex_unlock(&ctx->engines_mutex);
+ free_engines(set.engines);
+ return -ENOENT;
+ }
if (args->size)
i915_gem_context_set_user_engines(ctx);
else
@@ -1801,7 +1812,7 @@ set_engines(struct i915_gem_context *ctx,
mutex_unlock(&ctx->engines_mutex);
/* Keep track of old engine sets for kill_context() */
- engines_idle_release(set.engines);
+ engines_idle_release(ctx, set.engines);
return 0;
}
@@ -2077,8 +2088,6 @@ static int clone_engines(struct i915_gem_context *dst,
if (!clone)
goto err_unlock;
- clone->ctx = dst;
-
for (n = 0; n < e->num_engines; n++) {
struct intel_engine_cs *engine;
@@ -2121,8 +2130,7 @@ static int clone_engines(struct i915_gem_context *dst,
i915_gem_context_unlock_engines(src);
/* Serialised by constructor */
- free_engines(__context_engines_static(dst));
- RCU_INIT_POINTER(dst->engines, clone);
+ engines_idle_release(dst, rcu_replace_pointer(dst->engines, clone, 1));
if (user_engines)
i915_gem_context_set_user_engines(dst);
else
@@ -2553,6 +2561,9 @@ i915_gem_engines_iter_next(struct i915_gem_engines_iter *it)
const struct i915_gem_engines *e = it->engines;
struct intel_context *ctx;
+ if (unlikely(!e))
+ return NULL;
+
do {
if (it->idx >= e->num_engines)
return NULL;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index 3ae61a355d87..57b7ae2893e1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -207,7 +207,6 @@ static inline void
i915_gem_engines_iter_init(struct i915_gem_engines_iter *it,
struct i915_gem_engines *engines)
{
- GEM_BUG_ON(!engines);
it->engines = engines;
it->idx = 0;
}
--
2.25.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 51+ messages in thread* [Intel-gfx] [PATCH] drm/i915/gem: Consolidate ctx->engines[] release
2020-02-27 8:57 ` [Intel-gfx] [PATCH 05/20] drm/i915/gem: Consolidate ctx->engines[] release Chris Wilson
2020-02-27 9:51 ` [Intel-gfx] [PATCH] " Chris Wilson
@ 2020-02-27 11:01 ` Chris Wilson
2020-02-28 12:08 ` Tvrtko Ursulin
1 sibling, 1 reply; 51+ messages in thread
From: Chris Wilson @ 2020-02-27 11:01 UTC (permalink / raw)
To: intel-gfx
Use the same engine_idle_release() routine for cleaning all old
ctx->engine[] state, closing any potential races with concurrent execbuf
submission.
v2ish: Use the ce->pin_count to close the execbuf gap.
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1241
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
Remember to initialise the mock_context as well.
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 193 +++++++++---------
drivers/gpu/drm/i915/gem/i915_gem_context.h | 1 -
.../gpu/drm/i915/gem/selftests/mock_context.c | 3 +
3 files changed, 105 insertions(+), 92 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index e525ead073f7..cb6b6be48978 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -242,7 +242,6 @@ static void __free_engines(struct i915_gem_engines *e, unsigned int count)
if (!e->engines[count])
continue;
- RCU_INIT_POINTER(e->engines[count]->gem_context, NULL);
intel_context_put(e->engines[count]);
}
kfree(e);
@@ -255,7 +254,11 @@ static void free_engines(struct i915_gem_engines *e)
static void free_engines_rcu(struct rcu_head *rcu)
{
- free_engines(container_of(rcu, struct i915_gem_engines, rcu));
+ struct i915_gem_engines *engines =
+ container_of(rcu, struct i915_gem_engines, rcu);
+
+ i915_sw_fence_fini(&engines->fence);
+ free_engines(engines);
}
static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx)
@@ -269,8 +272,6 @@ static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx)
if (!e)
return ERR_PTR(-ENOMEM);
- e->ctx = ctx;
-
for_each_engine(engine, gt, id) {
struct intel_context *ce;
@@ -304,7 +305,6 @@ static void i915_gem_context_free(struct i915_gem_context *ctx)
list_del(&ctx->link);
spin_unlock(&ctx->i915->gem.contexts.lock);
- free_engines(rcu_access_pointer(ctx->engines));
mutex_destroy(&ctx->engines_mutex);
if (ctx->timeline)
@@ -491,30 +491,104 @@ static void kill_engines(struct i915_gem_engines *engines)
static void kill_stale_engines(struct i915_gem_context *ctx)
{
struct i915_gem_engines *pos, *next;
- unsigned long flags;
- spin_lock_irqsave(&ctx->stale.lock, flags);
+ spin_lock_irq(&ctx->stale.lock);
+ GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
list_for_each_entry_safe(pos, next, &ctx->stale.engines, link) {
- if (!i915_sw_fence_await(&pos->fence))
+ if (!i915_sw_fence_await(&pos->fence)) {
+ list_del_init(&pos->link);
continue;
+ }
- spin_unlock_irqrestore(&ctx->stale.lock, flags);
+ spin_unlock_irq(&ctx->stale.lock);
kill_engines(pos);
- spin_lock_irqsave(&ctx->stale.lock, flags);
+ spin_lock_irq(&ctx->stale.lock);
+ GEM_BUG_ON(i915_sw_fence_signaled(&pos->fence));
list_safe_reset_next(pos, next, link);
list_del_init(&pos->link); /* decouple from FENCE_COMPLETE */
i915_sw_fence_complete(&pos->fence);
}
- spin_unlock_irqrestore(&ctx->stale.lock, flags);
+ spin_unlock_irq(&ctx->stale.lock);
}
static void kill_context(struct i915_gem_context *ctx)
{
kill_stale_engines(ctx);
- kill_engines(__context_engines_static(ctx));
+}
+
+static int engines_notify(struct i915_sw_fence *fence,
+ enum i915_sw_fence_notify state)
+{
+ struct i915_gem_engines *engines =
+ container_of(fence, typeof(*engines), fence);
+
+ switch (state) {
+ case FENCE_COMPLETE:
+ if (!list_empty(&engines->link)) {
+ struct i915_gem_context *ctx = engines->ctx;
+ unsigned long flags;
+
+ spin_lock_irqsave(&ctx->stale.lock, flags);
+ list_del(&engines->link);
+ spin_unlock_irqrestore(&ctx->stale.lock, flags);
+ }
+ i915_gem_context_put(engines->ctx);
+ break;
+
+ case FENCE_FREE:
+ init_rcu_head(&engines->rcu);
+ call_rcu(&engines->rcu, free_engines_rcu);
+ break;
+ }
+
+ return NOTIFY_DONE;
+}
+
+static void engines_idle_release(struct i915_gem_context *ctx,
+ struct i915_gem_engines *engines)
+{
+ struct i915_gem_engines_iter it;
+ struct intel_context *ce;
+
+ i915_sw_fence_init(&engines->fence, engines_notify);
+ INIT_LIST_HEAD(&engines->link);
+
+ engines->ctx = i915_gem_context_get(ctx);
+
+ for_each_gem_engine(ce, engines, it) {
+ struct dma_fence *fence;
+ int err = 0;
+
+ /* serialises with execbuf */
+ RCU_INIT_POINTER(ce->gem_context, NULL);
+ if (!intel_context_pin_if_active(ce))
+ continue;
+
+ fence = i915_active_fence_get(&ce->timeline->last_request);
+ if (fence) {
+ err = i915_sw_fence_await_dma_fence(&engines->fence,
+ fence, 0,
+ GFP_KERNEL);
+ dma_fence_put(fence);
+ }
+ intel_context_unpin(ce);
+ if (err < 0)
+ goto kill;
+ }
+
+ spin_lock_irq(&ctx->stale.lock);
+ if (!i915_gem_context_is_closed(ctx))
+ list_add_tail(&engines->link, &ctx->stale.engines);
+ spin_unlock_irq(&ctx->stale.lock);
+
+kill:
+ if (list_empty(&engines->link)) /* raced, already closed */
+ kill_engines(engines);
+
+ i915_sw_fence_commit(&engines->fence);
}
static void set_closed_name(struct i915_gem_context *ctx)
@@ -538,11 +612,16 @@ static void context_close(struct i915_gem_context *ctx)
{
struct i915_address_space *vm;
+ /* Flush any concurrent set_engines() */
+ mutex_lock(&ctx->engines_mutex);
+ engines_idle_release(ctx, rcu_replace_pointer(ctx->engines, NULL, 1));
i915_gem_context_set_closed(ctx);
- set_closed_name(ctx);
+ mutex_unlock(&ctx->engines_mutex);
mutex_lock(&ctx->mutex);
+ set_closed_name(ctx);
+
vm = i915_gem_context_vm(ctx);
if (vm)
i915_vm_close(vm);
@@ -1626,77 +1705,6 @@ static const i915_user_extension_fn set_engines__extensions[] = {
[I915_CONTEXT_ENGINES_EXT_BOND] = set_engines__bond,
};
-static int engines_notify(struct i915_sw_fence *fence,
- enum i915_sw_fence_notify state)
-{
- struct i915_gem_engines *engines =
- container_of(fence, typeof(*engines), fence);
-
- switch (state) {
- case FENCE_COMPLETE:
- if (!list_empty(&engines->link)) {
- struct i915_gem_context *ctx = engines->ctx;
- unsigned long flags;
-
- spin_lock_irqsave(&ctx->stale.lock, flags);
- list_del(&engines->link);
- spin_unlock_irqrestore(&ctx->stale.lock, flags);
- }
- break;
-
- case FENCE_FREE:
- init_rcu_head(&engines->rcu);
- call_rcu(&engines->rcu, free_engines_rcu);
- break;
- }
-
- return NOTIFY_DONE;
-}
-
-static void engines_idle_release(struct i915_gem_engines *engines)
-{
- struct i915_gem_engines_iter it;
- struct intel_context *ce;
- unsigned long flags;
-
- GEM_BUG_ON(!engines);
- i915_sw_fence_init(&engines->fence, engines_notify);
-
- INIT_LIST_HEAD(&engines->link);
- spin_lock_irqsave(&engines->ctx->stale.lock, flags);
- if (!i915_gem_context_is_closed(engines->ctx))
- list_add(&engines->link, &engines->ctx->stale.engines);
- spin_unlock_irqrestore(&engines->ctx->stale.lock, flags);
- if (list_empty(&engines->link)) /* raced, already closed */
- goto kill;
-
- for_each_gem_engine(ce, engines, it) {
- struct dma_fence *fence;
- int err;
-
- if (!ce->timeline)
- continue;
-
- fence = i915_active_fence_get(&ce->timeline->last_request);
- if (!fence)
- continue;
-
- err = i915_sw_fence_await_dma_fence(&engines->fence,
- fence, 0,
- GFP_KERNEL);
-
- dma_fence_put(fence);
- if (err < 0)
- goto kill;
- }
- goto out;
-
-kill:
- kill_engines(engines);
-out:
- i915_sw_fence_commit(&engines->fence);
-}
-
static int
set_engines(struct i915_gem_context *ctx,
const struct drm_i915_gem_context_param *args)
@@ -1739,8 +1747,6 @@ set_engines(struct i915_gem_context *ctx,
if (!set.engines)
return -ENOMEM;
- set.engines->ctx = ctx;
-
for (n = 0; n < num_engines; n++) {
struct i915_engine_class_instance ci;
struct intel_engine_cs *engine;
@@ -1793,6 +1799,11 @@ set_engines(struct i915_gem_context *ctx,
replace:
mutex_lock(&ctx->engines_mutex);
+ if (i915_gem_context_is_closed(ctx)) {
+ mutex_unlock(&ctx->engines_mutex);
+ free_engines(set.engines);
+ return -ENOENT;
+ }
if (args->size)
i915_gem_context_set_user_engines(ctx);
else
@@ -1801,7 +1812,7 @@ set_engines(struct i915_gem_context *ctx,
mutex_unlock(&ctx->engines_mutex);
/* Keep track of old engine sets for kill_context() */
- engines_idle_release(set.engines);
+ engines_idle_release(ctx, set.engines);
return 0;
}
@@ -2077,8 +2088,6 @@ static int clone_engines(struct i915_gem_context *dst,
if (!clone)
goto err_unlock;
- clone->ctx = dst;
-
for (n = 0; n < e->num_engines; n++) {
struct intel_engine_cs *engine;
@@ -2121,8 +2130,7 @@ static int clone_engines(struct i915_gem_context *dst,
i915_gem_context_unlock_engines(src);
/* Serialised by constructor */
- free_engines(__context_engines_static(dst));
- RCU_INIT_POINTER(dst->engines, clone);
+ engines_idle_release(dst, rcu_replace_pointer(dst->engines, clone, 1));
if (user_engines)
i915_gem_context_set_user_engines(dst);
else
@@ -2553,6 +2561,9 @@ i915_gem_engines_iter_next(struct i915_gem_engines_iter *it)
const struct i915_gem_engines *e = it->engines;
struct intel_context *ctx;
+ if (unlikely(!e))
+ return NULL;
+
do {
if (it->idx >= e->num_engines)
return NULL;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index 3ae61a355d87..57b7ae2893e1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -207,7 +207,6 @@ static inline void
i915_gem_engines_iter_init(struct i915_gem_engines_iter *it,
struct i915_gem_engines *engines)
{
- GEM_BUG_ON(!engines);
it->engines = engines;
it->idx = 0;
}
diff --git a/drivers/gpu/drm/i915/gem/selftests/mock_context.c b/drivers/gpu/drm/i915/gem/selftests/mock_context.c
index b12ea1daa29d..e7e3c620f542 100644
--- a/drivers/gpu/drm/i915/gem/selftests/mock_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/mock_context.c
@@ -23,6 +23,9 @@ mock_context(struct drm_i915_private *i915,
INIT_LIST_HEAD(&ctx->link);
ctx->i915 = i915;
+ spin_lock_init(&ctx->stale.lock);
+ INIT_LIST_HEAD(&ctx->stale.engines);
+
i915_gem_context_set_persistence(ctx);
mutex_init(&ctx->engines_mutex);
--
2.25.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH] drm/i915/gem: Consolidate ctx->engines[] release
2020-02-27 11:01 ` Chris Wilson
@ 2020-02-28 12:08 ` Tvrtko Ursulin
2020-02-28 12:19 ` Chris Wilson
0 siblings, 1 reply; 51+ messages in thread
From: Tvrtko Ursulin @ 2020-02-28 12:08 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 27/02/2020 11:01, Chris Wilson wrote:
> Use the same engine_idle_release() routine for cleaning all old
> ctx->engine[] state, closing any potential races with concurrent execbuf
> submission.
>
> v2ish: Use the ce->pin_count to close the execbuf gap.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/issues/1241
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
> Remember to initialise the mock_context as well.
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 193 +++++++++---------
> drivers/gpu/drm/i915/gem/i915_gem_context.h | 1 -
> .../gpu/drm/i915/gem/selftests/mock_context.c | 3 +
> 3 files changed, 105 insertions(+), 92 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index e525ead073f7..cb6b6be48978 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -242,7 +242,6 @@ static void __free_engines(struct i915_gem_engines *e, unsigned int count)
> if (!e->engines[count])
> continue;
>
> - RCU_INIT_POINTER(e->engines[count]->gem_context, NULL);
> intel_context_put(e->engines[count]);
> }
> kfree(e);
> @@ -255,7 +254,11 @@ static void free_engines(struct i915_gem_engines *e)
>
> static void free_engines_rcu(struct rcu_head *rcu)
> {
> - free_engines(container_of(rcu, struct i915_gem_engines, rcu));
> + struct i915_gem_engines *engines =
> + container_of(rcu, struct i915_gem_engines, rcu);
> +
> + i915_sw_fence_fini(&engines->fence);
> + free_engines(engines);
> }
>
> static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx)
> @@ -269,8 +272,6 @@ static struct i915_gem_engines *default_engines(struct i915_gem_context *ctx)
> if (!e)
> return ERR_PTR(-ENOMEM);
>
> - e->ctx = ctx;
> -
> for_each_engine(engine, gt, id) {
> struct intel_context *ce;
>
> @@ -304,7 +305,6 @@ static void i915_gem_context_free(struct i915_gem_context *ctx)
> list_del(&ctx->link);
> spin_unlock(&ctx->i915->gem.contexts.lock);
>
> - free_engines(rcu_access_pointer(ctx->engines));
> mutex_destroy(&ctx->engines_mutex);
>
> if (ctx->timeline)
> @@ -491,30 +491,104 @@ static void kill_engines(struct i915_gem_engines *engines)
> static void kill_stale_engines(struct i915_gem_context *ctx)
> {
> struct i915_gem_engines *pos, *next;
> - unsigned long flags;
>
> - spin_lock_irqsave(&ctx->stale.lock, flags);
> + spin_lock_irq(&ctx->stale.lock);
> + GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
> list_for_each_entry_safe(pos, next, &ctx->stale.engines, link) {
> - if (!i915_sw_fence_await(&pos->fence))
> + if (!i915_sw_fence_await(&pos->fence)) {
> + list_del_init(&pos->link);
> continue;
> + }
>
> - spin_unlock_irqrestore(&ctx->stale.lock, flags);
> + spin_unlock_irq(&ctx->stale.lock);
>
> kill_engines(pos);
>
> - spin_lock_irqsave(&ctx->stale.lock, flags);
> + spin_lock_irq(&ctx->stale.lock);
> + GEM_BUG_ON(i915_sw_fence_signaled(&pos->fence));
> list_safe_reset_next(pos, next, link);
> list_del_init(&pos->link); /* decouple from FENCE_COMPLETE */
>
> i915_sw_fence_complete(&pos->fence);
> }
> - spin_unlock_irqrestore(&ctx->stale.lock, flags);
> + spin_unlock_irq(&ctx->stale.lock);
> }
>
> static void kill_context(struct i915_gem_context *ctx)
> {
> kill_stale_engines(ctx);
> - kill_engines(__context_engines_static(ctx));
> +}
> +
> +static int engines_notify(struct i915_sw_fence *fence,
> + enum i915_sw_fence_notify state)
> +{
> + struct i915_gem_engines *engines =
> + container_of(fence, typeof(*engines), fence);
> +
> + switch (state) {
> + case FENCE_COMPLETE:
> + if (!list_empty(&engines->link)) {
> + struct i915_gem_context *ctx = engines->ctx;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&ctx->stale.lock, flags);
> + list_del(&engines->link);
> + spin_unlock_irqrestore(&ctx->stale.lock, flags);
> + }
> + i915_gem_context_put(engines->ctx);
> + break;
> +
> + case FENCE_FREE:
> + init_rcu_head(&engines->rcu);
> + call_rcu(&engines->rcu, free_engines_rcu);
> + break;
> + }
> +
> + return NOTIFY_DONE;
> +}
> +
> +static void engines_idle_release(struct i915_gem_context *ctx,
> + struct i915_gem_engines *engines)
> +{
> + struct i915_gem_engines_iter it;
> + struct intel_context *ce;
> +
> + i915_sw_fence_init(&engines->fence, engines_notify);
> + INIT_LIST_HEAD(&engines->link);
> +
> + engines->ctx = i915_gem_context_get(ctx);
> +
> + for_each_gem_engine(ce, engines, it) {
> + struct dma_fence *fence;
> + int err = 0;
> +
> + /* serialises with execbuf */
> + RCU_INIT_POINTER(ce->gem_context, NULL);
What is the purpose of this? Looks dodgy - like it can't really
guarantee much.
> + if (!intel_context_pin_if_active(ce))
> + continue;
> +
> + fence = i915_active_fence_get(&ce->timeline->last_request);
> + if (fence) {
> + err = i915_sw_fence_await_dma_fence(&engines->fence,
> + fence, 0,
> + GFP_KERNEL);
> + dma_fence_put(fence);
> + }
> + intel_context_unpin(ce);
> + if (err < 0)
> + goto kill;
> + }
> +
> + spin_lock_irq(&ctx->stale.lock);
> + if (!i915_gem_context_is_closed(ctx))
> + list_add_tail(&engines->link, &ctx->stale.engines);
> + spin_unlock_irq(&ctx->stale.lock);
> +
> +kill:
> + if (list_empty(&engines->link)) /* raced, already closed */
> + kill_engines(engines);
Raced with.. ? context_close? Can't be the fence yet, before it has been
committed.
Regards,
Tvrtko
> +
> + i915_sw_fence_commit(&engines->fence);
> }
>
> static void set_closed_name(struct i915_gem_context *ctx)
> @@ -538,11 +612,16 @@ static void context_close(struct i915_gem_context *ctx)
> {
> struct i915_address_space *vm;
>
> + /* Flush any concurrent set_engines() */
> + mutex_lock(&ctx->engines_mutex);
> + engines_idle_release(ctx, rcu_replace_pointer(ctx->engines, NULL, 1));
> i915_gem_context_set_closed(ctx);
> - set_closed_name(ctx);
> + mutex_unlock(&ctx->engines_mutex);
>
> mutex_lock(&ctx->mutex);
>
> + set_closed_name(ctx);
> +
> vm = i915_gem_context_vm(ctx);
> if (vm)
> i915_vm_close(vm);
> @@ -1626,77 +1705,6 @@ static const i915_user_extension_fn set_engines__extensions[] = {
> [I915_CONTEXT_ENGINES_EXT_BOND] = set_engines__bond,
> };
>
> -static int engines_notify(struct i915_sw_fence *fence,
> - enum i915_sw_fence_notify state)
> -{
> - struct i915_gem_engines *engines =
> - container_of(fence, typeof(*engines), fence);
> -
> - switch (state) {
> - case FENCE_COMPLETE:
> - if (!list_empty(&engines->link)) {
> - struct i915_gem_context *ctx = engines->ctx;
> - unsigned long flags;
> -
> - spin_lock_irqsave(&ctx->stale.lock, flags);
> - list_del(&engines->link);
> - spin_unlock_irqrestore(&ctx->stale.lock, flags);
> - }
> - break;
> -
> - case FENCE_FREE:
> - init_rcu_head(&engines->rcu);
> - call_rcu(&engines->rcu, free_engines_rcu);
> - break;
> - }
> -
> - return NOTIFY_DONE;
> -}
> -
> -static void engines_idle_release(struct i915_gem_engines *engines)
> -{
> - struct i915_gem_engines_iter it;
> - struct intel_context *ce;
> - unsigned long flags;
> -
> - GEM_BUG_ON(!engines);
> - i915_sw_fence_init(&engines->fence, engines_notify);
> -
> - INIT_LIST_HEAD(&engines->link);
> - spin_lock_irqsave(&engines->ctx->stale.lock, flags);
> - if (!i915_gem_context_is_closed(engines->ctx))
> - list_add(&engines->link, &engines->ctx->stale.engines);
> - spin_unlock_irqrestore(&engines->ctx->stale.lock, flags);
> - if (list_empty(&engines->link)) /* raced, already closed */
> - goto kill;
> -
> - for_each_gem_engine(ce, engines, it) {
> - struct dma_fence *fence;
> - int err;
> -
> - if (!ce->timeline)
> - continue;
> -
> - fence = i915_active_fence_get(&ce->timeline->last_request);
> - if (!fence)
> - continue;
> -
> - err = i915_sw_fence_await_dma_fence(&engines->fence,
> - fence, 0,
> - GFP_KERNEL);
> -
> - dma_fence_put(fence);
> - if (err < 0)
> - goto kill;
> - }
> - goto out;
> -
> -kill:
> - kill_engines(engines);
> -out:
> - i915_sw_fence_commit(&engines->fence);
> -}
> -
> static int
> set_engines(struct i915_gem_context *ctx,
> const struct drm_i915_gem_context_param *args)
> @@ -1739,8 +1747,6 @@ set_engines(struct i915_gem_context *ctx,
> if (!set.engines)
> return -ENOMEM;
>
> - set.engines->ctx = ctx;
> -
> for (n = 0; n < num_engines; n++) {
> struct i915_engine_class_instance ci;
> struct intel_engine_cs *engine;
> @@ -1793,6 +1799,11 @@ set_engines(struct i915_gem_context *ctx,
>
> replace:
> mutex_lock(&ctx->engines_mutex);
> + if (i915_gem_context_is_closed(ctx)) {
> + mutex_unlock(&ctx->engines_mutex);
> + free_engines(set.engines);
> + return -ENOENT;
> + }
> if (args->size)
> i915_gem_context_set_user_engines(ctx);
> else
> @@ -1801,7 +1812,7 @@ set_engines(struct i915_gem_context *ctx,
> mutex_unlock(&ctx->engines_mutex);
>
> /* Keep track of old engine sets for kill_context() */
> - engines_idle_release(set.engines);
> + engines_idle_release(ctx, set.engines);
>
> return 0;
> }
> @@ -2077,8 +2088,6 @@ static int clone_engines(struct i915_gem_context *dst,
> if (!clone)
> goto err_unlock;
>
> - clone->ctx = dst;
> -
> for (n = 0; n < e->num_engines; n++) {
> struct intel_engine_cs *engine;
>
> @@ -2121,8 +2130,7 @@ static int clone_engines(struct i915_gem_context *dst,
> i915_gem_context_unlock_engines(src);
>
> /* Serialised by constructor */
> - free_engines(__context_engines_static(dst));
> - RCU_INIT_POINTER(dst->engines, clone);
> + engines_idle_release(dst, rcu_replace_pointer(dst->engines, clone, 1));
> if (user_engines)
> i915_gem_context_set_user_engines(dst);
> else
> @@ -2553,6 +2561,9 @@ i915_gem_engines_iter_next(struct i915_gem_engines_iter *it)
> const struct i915_gem_engines *e = it->engines;
> struct intel_context *ctx;
>
> + if (unlikely(!e))
> + return NULL;
> +
> do {
> if (it->idx >= e->num_engines)
> return NULL;
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h
> index 3ae61a355d87..57b7ae2893e1 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
> @@ -207,7 +207,6 @@ static inline void
> i915_gem_engines_iter_init(struct i915_gem_engines_iter *it,
> struct i915_gem_engines *engines)
> {
> - GEM_BUG_ON(!engines);
> it->engines = engines;
> it->idx = 0;
> }
> diff --git a/drivers/gpu/drm/i915/gem/selftests/mock_context.c b/drivers/gpu/drm/i915/gem/selftests/mock_context.c
> index b12ea1daa29d..e7e3c620f542 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/mock_context.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/mock_context.c
> @@ -23,6 +23,9 @@ mock_context(struct drm_i915_private *i915,
> INIT_LIST_HEAD(&ctx->link);
> ctx->i915 = i915;
>
> + spin_lock_init(&ctx->stale.lock);
> + INIT_LIST_HEAD(&ctx->stale.engines);
> +
> i915_gem_context_set_persistence(ctx);
>
> mutex_init(&ctx->engines_mutex);
>
_______________________________________________
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^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH] drm/i915/gem: Consolidate ctx->engines[] release
2020-02-28 12:08 ` Tvrtko Ursulin
@ 2020-02-28 12:19 ` Chris Wilson
2020-03-02 14:20 ` Tvrtko Ursulin
0 siblings, 1 reply; 51+ messages in thread
From: Chris Wilson @ 2020-02-28 12:19 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx
Quoting Tvrtko Ursulin (2020-02-28 12:08:18)
>
> On 27/02/2020 11:01, Chris Wilson wrote:
> > +static void engines_idle_release(struct i915_gem_context *ctx,
> > + struct i915_gem_engines *engines)
> > +{
> > + struct i915_gem_engines_iter it;
> > + struct intel_context *ce;
> > +
> > + i915_sw_fence_init(&engines->fence, engines_notify);
> > + INIT_LIST_HEAD(&engines->link);
> > +
> > + engines->ctx = i915_gem_context_get(ctx);
> > +
> > + for_each_gem_engine(ce, engines, it) {
> > + struct dma_fence *fence;
> > + int err = 0;
> > +
> > + /* serialises with execbuf */
> > + RCU_INIT_POINTER(ce->gem_context, NULL);
>
> What is the purpose of this? Looks dodgy - like it can't really
> guarantee much.
It should be fine if we do:
execbuf: context_close:
ce->gem_context = NULL;
add_to_timeline(); get(&ce->timeline->last_request);
if (!ce->gem_context)
return -ENOENT;
If add is before the get, we will wait on it.
If add is after the get, we will wait on the earlier request, and skip
this one -- it will not execute.
> > + if (!intel_context_pin_if_active(ce))
> > + continue;
> > +
> > + fence = i915_active_fence_get(&ce->timeline->last_request);
> > + if (fence) {
> > + err = i915_sw_fence_await_dma_fence(&engines->fence,
> > + fence, 0,
> > + GFP_KERNEL);
> > + dma_fence_put(fence);
> > + }
> > + intel_context_unpin(ce);
> > + if (err < 0)
> > + goto kill;
> > + }
> > +
> > + spin_lock_irq(&ctx->stale.lock);
> > + if (!i915_gem_context_is_closed(ctx))
> > + list_add_tail(&engines->link, &ctx->stale.engines);
> > + spin_unlock_irq(&ctx->stale.lock);
> > +
> > +kill:
> > + if (list_empty(&engines->link)) /* raced, already closed */
> > + kill_engines(engines);
>
> Raced with.. ? context_close? Can't be the fence yet, before it has been
> committed.
Yes, there's still the set_engines vs context_close to worry about.
-Chris
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^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH] drm/i915/gem: Consolidate ctx->engines[] release
2020-02-28 12:19 ` Chris Wilson
@ 2020-03-02 14:20 ` Tvrtko Ursulin
0 siblings, 0 replies; 51+ messages in thread
From: Tvrtko Ursulin @ 2020-03-02 14:20 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 28/02/2020 12:19, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2020-02-28 12:08:18)
>>
>> On 27/02/2020 11:01, Chris Wilson wrote:
>>> +static void engines_idle_release(struct i915_gem_context *ctx,
>>> + struct i915_gem_engines *engines)
>>> +{
>>> + struct i915_gem_engines_iter it;
>>> + struct intel_context *ce;
>>> +
>>> + i915_sw_fence_init(&engines->fence, engines_notify);
>>> + INIT_LIST_HEAD(&engines->link);
>>> +
>>> + engines->ctx = i915_gem_context_get(ctx);
>>> +
>>> + for_each_gem_engine(ce, engines, it) {
>>> + struct dma_fence *fence;
>>> + int err = 0;
>>> +
>>> + /* serialises with execbuf */
>>> + RCU_INIT_POINTER(ce->gem_context, NULL);
>>
>> What is the purpose of this? Looks dodgy - like it can't really
>> guarantee much.
>
> It should be fine if we do:
>
> execbuf: context_close:
> ce->gem_context = NULL;
> add_to_timeline(); get(&ce->timeline->last_request);
> if (!ce->gem_context)
> return -ENOENT;
>
> If add is before the get, we will wait on it.
> If add is after the get, we will wait on the earlier request, and skip
> this one -- it will not execute.
What guarantees we see the latest last_request here, or that execbuf
sees the NULL before we try the get? The code elsewhere isn't assuming
unstable ce->gem_context I think.. engines we can change, but I don't
remember we accounted for this.
>>> + if (!intel_context_pin_if_active(ce))
>>> + continue;
>>> +
>>> + fence = i915_active_fence_get(&ce->timeline->last_request);
>>> + if (fence) {
>>> + err = i915_sw_fence_await_dma_fence(&engines->fence,
>>> + fence, 0,
>>> + GFP_KERNEL);
>>> + dma_fence_put(fence);
>>> + }
>>> + intel_context_unpin(ce);
>>> + if (err < 0)
>>> + goto kill;
>>> + }
>>> +
>>> + spin_lock_irq(&ctx->stale.lock);
>>> + if (!i915_gem_context_is_closed(ctx))
>>> + list_add_tail(&engines->link, &ctx->stale.engines);
>>> + spin_unlock_irq(&ctx->stale.lock);
>>> +
>>> +kill:
>>> + if (list_empty(&engines->link)) /* raced, already closed */
>>> + kill_engines(engines);
>>
>> Raced with.. ? context_close? Can't be the fence yet, before it has been
>> committed.
>
> Yes, there's still the set_engines vs context_close to worry about.
I'd just say "raced with context_close" then.
Regards,
Tvrtko
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^ permalink raw reply [flat|nested] 51+ messages in thread
* [Intel-gfx] [PATCH 06/20] drm/i915/gt: Prevent allocation on a banned context
2020-02-27 8:57 [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits Chris Wilson
` (3 preceding siblings ...)
2020-02-27 8:57 ` [Intel-gfx] [PATCH 05/20] drm/i915/gem: Consolidate ctx->engines[] release Chris Wilson
@ 2020-02-27 8:57 ` Chris Wilson
2020-02-27 8:57 ` [Intel-gfx] [PATCH 07/20] drm/i915/gem: Check that the context wasn't closed during setup Chris Wilson
` (20 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Chris Wilson @ 2020-02-27 8:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Matthew Auld
If a context is banned even before we submit our first request to it,
report the failure before we attempt to allocate any resources for the
context.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/gt/intel_context.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c
index 8bb444cda14f..01474d3a558b 100644
--- a/drivers/gpu/drm/i915/gt/intel_context.c
+++ b/drivers/gpu/drm/i915/gt/intel_context.c
@@ -51,6 +51,11 @@ int intel_context_alloc_state(struct intel_context *ce)
return -EINTR;
if (!test_bit(CONTEXT_ALLOC_BIT, &ce->flags)) {
+ if (intel_context_is_banned(ce)) {
+ err = -EIO;
+ goto unlock;
+ }
+
err = ce->ops->alloc(ce);
if (unlikely(err))
goto unlock;
--
2.25.1
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^ permalink raw reply related [flat|nested] 51+ messages in thread* [Intel-gfx] [PATCH 07/20] drm/i915/gem: Check that the context wasn't closed during setup
2020-02-27 8:57 [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits Chris Wilson
` (4 preceding siblings ...)
2020-02-27 8:57 ` [Intel-gfx] [PATCH 06/20] drm/i915/gt: Prevent allocation on a banned context Chris Wilson
@ 2020-02-27 8:57 ` Chris Wilson
2020-02-27 8:57 ` [Intel-gfx] [PATCH 08/20] drm/i915/selftests: Disable heartbeat around manual pulse tests Chris Wilson
` (19 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Chris Wilson @ 2020-02-27 8:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Matthew Auld
As setup takes a long time, the user may close the context during the
construction of the execbuf. In order to make sure we correctly track
all outstanding work with non-persistent contexts, we need to serialise
the submission with the context closure and mop up any leaks.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index ac0e5fc5675e..d9392a8978f8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2735,6 +2735,12 @@ i915_gem_do_execbuffer(struct drm_device *dev,
goto err_batch_unpin;
}
+ /* Check that the context wasn't destroyed before setup */
+ if (!rcu_access_pointer(eb.context->gem_context)) {
+ err = -ENOENT;
+ goto err_request;
+ }
+
if (in_fence) {
err = i915_request_await_dma_fence(eb.request, in_fence);
if (err < 0)
--
2.25.1
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^ permalink raw reply related [flat|nested] 51+ messages in thread* [Intel-gfx] [PATCH 08/20] drm/i915/selftests: Disable heartbeat around manual pulse tests
2020-02-27 8:57 [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits Chris Wilson
` (5 preceding siblings ...)
2020-02-27 8:57 ` [Intel-gfx] [PATCH 07/20] drm/i915/gem: Check that the context wasn't closed during setup Chris Wilson
@ 2020-02-27 8:57 ` Chris Wilson
2020-02-27 22:51 ` Andi Shyti
2020-02-27 8:57 ` [Intel-gfx] [PATCH 09/20] drm/i915/gt: Reset queue_priority_hint after wedging Chris Wilson
` (18 subsequent siblings)
25 siblings, 1 reply; 51+ messages in thread
From: Chris Wilson @ 2020-02-27 8:57 UTC (permalink / raw)
To: intel-gfx
Still chasing the mystery of the stray idle flush, let's ensure that the
heartbeat does not run at the same time as our test and confuse us.
References: https://gitlab.freedesktop.org/drm/intel/issues/541
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
.../drm/i915/gt/selftest_engine_heartbeat.c | 30 ++++++++++++++++---
drivers/gpu/drm/i915/selftests/i915_active.c | 3 +-
2 files changed, 27 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
index 43d4d589749f..697114dd1f47 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.c
@@ -142,6 +142,24 @@ static int __live_idle_pulse(struct intel_engine_cs *engine,
return err;
}
+static void engine_heartbeat_disable(struct intel_engine_cs *engine,
+ unsigned long *saved)
+{
+ *saved = engine->props.heartbeat_interval_ms;
+ engine->props.heartbeat_interval_ms = 0;
+
+ intel_engine_pm_get(engine);
+ intel_engine_park_heartbeat(engine);
+}
+
+static void engine_heartbeat_enable(struct intel_engine_cs *engine,
+ unsigned long saved)
+{
+ intel_engine_pm_put(engine);
+
+ engine->props.heartbeat_interval_ms = saved;
+}
+
static int live_idle_flush(void *arg)
{
struct intel_gt *gt = arg;
@@ -152,9 +170,11 @@ static int live_idle_flush(void *arg)
/* Check that we can flush the idle barriers */
for_each_engine(engine, gt, id) {
- intel_engine_pm_get(engine);
+ unsigned long heartbeat;
+
+ engine_heartbeat_disable(engine, &heartbeat);
err = __live_idle_pulse(engine, intel_engine_flush_barriers);
- intel_engine_pm_put(engine);
+ engine_heartbeat_enable(engine, heartbeat);
if (err)
break;
}
@@ -172,9 +192,11 @@ static int live_idle_pulse(void *arg)
/* Check that heartbeat pulses flush the idle barriers */
for_each_engine(engine, gt, id) {
- intel_engine_pm_get(engine);
+ unsigned long heartbeat;
+
+ engine_heartbeat_disable(engine, &heartbeat);
err = __live_idle_pulse(engine, intel_engine_pulse);
- intel_engine_pm_put(engine);
+ engine_heartbeat_enable(engine, heartbeat);
if (err && err != -ENODEV)
break;
diff --git a/drivers/gpu/drm/i915/selftests/i915_active.c b/drivers/gpu/drm/i915/selftests/i915_active.c
index 067e30b8927f..3a37c67ab6c4 100644
--- a/drivers/gpu/drm/i915/selftests/i915_active.c
+++ b/drivers/gpu/drm/i915/selftests/i915_active.c
@@ -331,8 +331,7 @@ void i915_active_unlock_wait(struct i915_active *ref)
}
/* And wait for the retire callback */
- spin_lock_irq(&ref->tree_lock);
- spin_unlock_irq(&ref->tree_lock);
+ spin_unlock_wait(&ref->tree_lock);
/* ... which may have been on a thread instead */
flush_work(&ref->work);
--
2.25.1
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^ permalink raw reply related [flat|nested] 51+ messages in thread* [Intel-gfx] [PATCH 09/20] drm/i915/gt: Reset queue_priority_hint after wedging
2020-02-27 8:57 [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits Chris Wilson
` (6 preceding siblings ...)
2020-02-27 8:57 ` [Intel-gfx] [PATCH 08/20] drm/i915/selftests: Disable heartbeat around manual pulse tests Chris Wilson
@ 2020-02-27 8:57 ` Chris Wilson
2020-02-28 12:10 ` Tvrtko Ursulin
2020-02-27 8:57 ` [Intel-gfx] [PATCH 10/20] drm/i915/gt: Pull marking vm as closed underneath the vm->mutex Chris Wilson
` (17 subsequent siblings)
25 siblings, 1 reply; 51+ messages in thread
From: Chris Wilson @ 2020-02-27 8:57 UTC (permalink / raw)
To: intel-gfx
An odd and highly unlikely path caught us out. On delayed submission
(due to an asynchronous reset handler), we poked the priority_hint and
kicked the tasklet. However, we had already marked the device as wedged
and swapped out the tasklet for a no-op. The result was that we never
cleared the priority hint and became upset when we later checked.
<0> [574.303565] i915_sel-6278 2.... 481822445us : __i915_subtests: Running intel_execlists_live_selftests/live_error_interrupt
<0> [574.303565] i915_sel-6278 2.... 481822472us : __engine_unpark: 0000:00:02.0 rcs0:
<0> [574.303565] i915_sel-6278 2.... 481822491us : __gt_unpark: 0000:00:02.0
<0> [574.303565] i915_sel-6278 2.... 481823220us : execlists_context_reset: 0000:00:02.0 rcs0: context:f4ee reset
<0> [574.303565] i915_sel-6278 2.... 481824830us : __intel_context_active: 0000:00:02.0 rcs0: context:f51b active
<0> [574.303565] i915_sel-6278 2.... 481825258us : __intel_context_do_pin: 0000:00:02.0 rcs0: context:f51b pin ring:{start:00006000, head:0000, tail:0000}
<0> [574.303565] i915_sel-6278 2.... 481825311us : __i915_request_commit: 0000:00:02.0 rcs0: fence f51b:2, current 0
<0> [574.303565] i915_sel-6278 2d..1 481825347us : __i915_request_submit: 0000:00:02.0 rcs0: fence f51b:2, current 0
<0> [574.303565] i915_sel-6278 2d..1 481825363us : trace_ports: 0000:00:02.0 rcs0: submit { f51b:2, 0:0 }
<0> [574.303565] i915_sel-6278 2.... 481826809us : __intel_context_active: 0000:00:02.0 rcs0: context:f51c active
<0> [574.303565] <idle>-0 7d.h2 481827326us : cs_irq_handler: 0000:00:02.0 rcs0: CS error: 1
<0> [574.303565] <idle>-0 7..s1 481827377us : process_csb: 0000:00:02.0 rcs0: cs-irq head=3, tail=4
<0> [574.303565] <idle>-0 7..s1 481827379us : process_csb: 0000:00:02.0 rcs0: csb[4]: status=0x10000001:0x00000000
<0> [574.305593] <idle>-0 7..s1 481827385us : trace_ports: 0000:00:02.0 rcs0: promote { f51b:2*, 0:0 }
<0> [574.305611] <idle>-0 7..s1 481828179us : execlists_reset: 0000:00:02.0 rcs0: reset for CS error
<0> [574.305611] i915_sel-6278 2.... 481828284us : __intel_context_do_pin: 0000:00:02.0 rcs0: context:f51c pin ring:{start:00007000, head:0000, tail:0000}
<0> [574.305611] i915_sel-6278 2.... 481828345us : __i915_request_commit: 0000:00:02.0 rcs0: fence f51c:2, current 0
<0> [574.305611] <idle>-0 7dNs2 481847823us : __i915_request_unsubmit: 0000:00:02.0 rcs0: fence f51b:2, current 1
<0> [574.305611] <idle>-0 7dNs2 481847857us : execlists_hold: 0000:00:02.0 rcs0: fence f51b:2, current 1 on hold
<0> [574.305611] <idle>-0 7.Ns1 481847863us : intel_engine_reset: 0000:00:02.0 rcs0: flags=4
<0> [574.305611] <idle>-0 7.Ns1 481847945us : execlists_reset_prepare: 0000:00:02.0 rcs0: depth<-1
<0> [574.305611] <idle>-0 7.Ns1 481847946us : intel_engine_stop_cs: 0000:00:02.0 rcs0:
<0> [574.305611] <idle>-0 7.Ns1 538584284us : intel_engine_stop_cs: 0000:00:02.0 rcs0: timed out on STOP_RING -> IDLE
<0> [574.305611] <idle>-0 7.Ns1 538584347us : __intel_gt_reset: 0000:00:02.0 engine_mask=1
<0> [574.305611] <idle>-0 7.Ns1 538584406us : execlists_reset_rewind: 0000:00:02.0 rcs0:
<0> [574.305611] <idle>-0 7dNs2 538585050us : __i915_request_reset: 0000:00:02.0 rcs0: fence f51b:2, current 1 guilty? yes
<0> [574.305611] <idle>-0 7dNs2 538585063us : __execlists_reset: 0000:00:02.0 rcs0: replay {head:0000, tail:0068}
<0> [574.306565] <idle>-0 7.Ns1 538588457us : intel_engine_cancel_stop_cs: 0000:00:02.0 rcs0:
<0> [574.306565] <idle>-0 7dNs2 538588462us : __i915_request_submit: 0000:00:02.0 rcs0: fence f51c:2, current 0
<0> [574.306565] <idle>-0 7dNs2 538588471us : trace_ports: 0000:00:02.0 rcs0: submit { f51c:2, 0:0 }
<0> [574.306565] <idle>-0 7.Ns1 538588474us : execlists_reset_finish: 0000:00:02.0 rcs0: depth->1
<0> [574.306565] kworker/-202 2.... 538588755us : i915_request_retire: 0000:00:02.0 rcs0: fence f51c:2, current 2
<0> [574.306565] ksoftirq-46 7..s. 538588773us : process_csb: 0000:00:02.0 rcs0: cs-irq head=11, tail=1
<0> [574.306565] ksoftirq-46 7..s. 538588774us : process_csb: 0000:00:02.0 rcs0: csb[0]: status=0x10000001:0x00000000
<0> [574.306565] ksoftirq-46 7..s. 538588776us : trace_ports: 0000:00:02.0 rcs0: promote { f51c:2!, 0:0 }
<0> [574.306565] ksoftirq-46 7..s. 538588778us : process_csb: 0000:00:02.0 rcs0: csb[1]: status=0x10000018:0x00000020
<0> [574.306565] ksoftirq-46 7..s. 538588779us : trace_ports: 0000:00:02.0 rcs0: completed { f51c:2!, 0:0 }
<0> [574.306565] kworker/-202 2.... 538588826us : intel_context_unpin: 0000:00:02.0 rcs0: context:f51c unpin
<0> [574.306565] i915_sel-6278 6.... 538589663us : __intel_gt_set_wedged.part.32: 0000:00:02.0 start
<0> [574.306565] i915_sel-6278 6.... 538589667us : execlists_reset_prepare: 0000:00:02.0 rcs0: depth<-0
<0> [574.306565] i915_sel-6278 6.... 538589710us : intel_engine_stop_cs: 0000:00:02.0 rcs0:
<0> [574.306565] i915_sel-6278 6.... 538589732us : execlists_reset_prepare: 0000:00:02.0 bcs0: depth<-0
<0> [574.307591] i915_sel-6278 6.... 538589733us : intel_engine_stop_cs: 0000:00:02.0 bcs0:
<0> [574.307591] i915_sel-6278 6.... 538589757us : execlists_reset_prepare: 0000:00:02.0 vcs0: depth<-0
<0> [574.307591] i915_sel-6278 6.... 538589758us : intel_engine_stop_cs: 0000:00:02.0 vcs0:
<0> [574.307591] i915_sel-6278 6.... 538589771us : execlists_reset_prepare: 0000:00:02.0 vcs1: depth<-0
<0> [574.307591] i915_sel-6278 6.... 538589772us : intel_engine_stop_cs: 0000:00:02.0 vcs1:
<0> [574.307591] i915_sel-6278 6.... 538589778us : execlists_reset_prepare: 0000:00:02.0 vecs0: depth<-0
<0> [574.307591] i915_sel-6278 6.... 538589780us : intel_engine_stop_cs: 0000:00:02.0 vecs0:
<0> [574.307591] i915_sel-6278 6.... 538589786us : __intel_gt_reset: 0000:00:02.0 engine_mask=ff
<0> [574.307591] i915_sel-6278 6.... 538591175us : execlists_reset_cancel: 0000:00:02.0 rcs0:
<0> [574.307591] i915_sel-6278 6.... 538591970us : execlists_reset_cancel: 0000:00:02.0 bcs0:
<0> [574.307591] i915_sel-6278 6.... 538591982us : execlists_reset_cancel: 0000:00:02.0 vcs0:
<0> [574.307591] i915_sel-6278 6.... 538591996us : execlists_reset_cancel: 0000:00:02.0 vcs1:
<0> [574.307591] i915_sel-6278 6.... 538592759us : execlists_reset_cancel: 0000:00:02.0 vecs0:
<0> [574.307591] i915_sel-6278 6.... 538592977us : execlists_reset_finish: 0000:00:02.0 rcs0: depth->0
<0> [574.307591] i915_sel-6278 6.N.. 538592996us : execlists_reset_finish: 0000:00:02.0 bcs0: depth->0
<0> [574.307591] i915_sel-6278 6.N.. 538593023us : execlists_reset_finish: 0000:00:02.0 vcs0: depth->0
<0> [574.307591] i915_sel-6278 6.N.. 538593037us : execlists_reset_finish: 0000:00:02.0 vcs1: depth->0
<0> [574.307591] i915_sel-6278 6.N.. 538593051us : execlists_reset_finish: 0000:00:02.0 vecs0: depth->0
<0> [574.307591] i915_sel-6278 6.... 538593407us : __intel_gt_set_wedged.part.32: 0000:00:02.0 end
<0> [574.307591] kworker/-210 7d..1 551958381us : execlists_unhold: 0000:00:02.0 rcs0: fence f51b:2, current 2 hold release
<0> [574.307591] i915_sel-6278 0.... 559490788us : i915_request_retire: 0000:00:02.0 rcs0: fence f51b:2, current 2
<0> [574.307591] i915_sel-6278 0.... 559490793us : intel_context_unpin: 0000:00:02.0 rcs0: context:f51b unpin
<0> [574.307591] i915_sel-6278 0.... 559490798us : __engine_park: 0000:00:02.0 rcs0: parked
<0> [574.307591] i915_sel-6278 0.... 559490982us : __intel_context_retire: 0000:00:02.0 rcs0: context:f51c retire runtime: { total:30004ns, avg:30004ns }
<0> [574.307591] i915_sel-6278 0.... 559491372us : __engine_park: __engine_park:261 GEM_BUG_ON(engine->execlists.queue_priority_hint != (-((int)(~0U >> 1)) - 1))
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 39b0125b7143..35c5cf786726 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3724,7 +3724,10 @@ static void execlists_reset_rewind(struct intel_engine_cs *engine, bool stalled)
static void nop_submission_tasklet(unsigned long data)
{
+ struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
+
/* The driver is wedged; don't process any more events. */
+ WRITE_ONCE(engine->execlists.queue_priority_hint, INT_MIN);
}
static void execlists_reset_cancel(struct intel_engine_cs *engine)
--
2.25.1
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^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH 09/20] drm/i915/gt: Reset queue_priority_hint after wedging
2020-02-27 8:57 ` [Intel-gfx] [PATCH 09/20] drm/i915/gt: Reset queue_priority_hint after wedging Chris Wilson
@ 2020-02-28 12:10 ` Tvrtko Ursulin
2020-02-28 12:31 ` Chris Wilson
0 siblings, 1 reply; 51+ messages in thread
From: Tvrtko Ursulin @ 2020-02-28 12:10 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 27/02/2020 08:57, Chris Wilson wrote:
> An odd and highly unlikely path caught us out. On delayed submission
> (due to an asynchronous reset handler), we poked the priority_hint and
> kicked the tasklet. However, we had already marked the device as wedged
> and swapped out the tasklet for a no-op. The result was that we never
> cleared the priority hint and became upset when we later checked.
>
> <0> [574.303565] i915_sel-6278 2.... 481822445us : __i915_subtests: Running intel_execlists_live_selftests/live_error_interrupt
> <0> [574.303565] i915_sel-6278 2.... 481822472us : __engine_unpark: 0000:00:02.0 rcs0:
> <0> [574.303565] i915_sel-6278 2.... 481822491us : __gt_unpark: 0000:00:02.0
> <0> [574.303565] i915_sel-6278 2.... 481823220us : execlists_context_reset: 0000:00:02.0 rcs0: context:f4ee reset
> <0> [574.303565] i915_sel-6278 2.... 481824830us : __intel_context_active: 0000:00:02.0 rcs0: context:f51b active
> <0> [574.303565] i915_sel-6278 2.... 481825258us : __intel_context_do_pin: 0000:00:02.0 rcs0: context:f51b pin ring:{start:00006000, head:0000, tail:0000}
> <0> [574.303565] i915_sel-6278 2.... 481825311us : __i915_request_commit: 0000:00:02.0 rcs0: fence f51b:2, current 0
> <0> [574.303565] i915_sel-6278 2d..1 481825347us : __i915_request_submit: 0000:00:02.0 rcs0: fence f51b:2, current 0
> <0> [574.303565] i915_sel-6278 2d..1 481825363us : trace_ports: 0000:00:02.0 rcs0: submit { f51b:2, 0:0 }
> <0> [574.303565] i915_sel-6278 2.... 481826809us : __intel_context_active: 0000:00:02.0 rcs0: context:f51c active
> <0> [574.303565] <idle>-0 7d.h2 481827326us : cs_irq_handler: 0000:00:02.0 rcs0: CS error: 1
> <0> [574.303565] <idle>-0 7..s1 481827377us : process_csb: 0000:00:02.0 rcs0: cs-irq head=3, tail=4
> <0> [574.303565] <idle>-0 7..s1 481827379us : process_csb: 0000:00:02.0 rcs0: csb[4]: status=0x10000001:0x00000000
> <0> [574.305593] <idle>-0 7..s1 481827385us : trace_ports: 0000:00:02.0 rcs0: promote { f51b:2*, 0:0 }
> <0> [574.305611] <idle>-0 7..s1 481828179us : execlists_reset: 0000:00:02.0 rcs0: reset for CS error
> <0> [574.305611] i915_sel-6278 2.... 481828284us : __intel_context_do_pin: 0000:00:02.0 rcs0: context:f51c pin ring:{start:00007000, head:0000, tail:0000}
> <0> [574.305611] i915_sel-6278 2.... 481828345us : __i915_request_commit: 0000:00:02.0 rcs0: fence f51c:2, current 0
> <0> [574.305611] <idle>-0 7dNs2 481847823us : __i915_request_unsubmit: 0000:00:02.0 rcs0: fence f51b:2, current 1
> <0> [574.305611] <idle>-0 7dNs2 481847857us : execlists_hold: 0000:00:02.0 rcs0: fence f51b:2, current 1 on hold
> <0> [574.305611] <idle>-0 7.Ns1 481847863us : intel_engine_reset: 0000:00:02.0 rcs0: flags=4
> <0> [574.305611] <idle>-0 7.Ns1 481847945us : execlists_reset_prepare: 0000:00:02.0 rcs0: depth<-1
> <0> [574.305611] <idle>-0 7.Ns1 481847946us : intel_engine_stop_cs: 0000:00:02.0 rcs0:
> <0> [574.305611] <idle>-0 7.Ns1 538584284us : intel_engine_stop_cs: 0000:00:02.0 rcs0: timed out on STOP_RING -> IDLE
> <0> [574.305611] <idle>-0 7.Ns1 538584347us : __intel_gt_reset: 0000:00:02.0 engine_mask=1
> <0> [574.305611] <idle>-0 7.Ns1 538584406us : execlists_reset_rewind: 0000:00:02.0 rcs0:
> <0> [574.305611] <idle>-0 7dNs2 538585050us : __i915_request_reset: 0000:00:02.0 rcs0: fence f51b:2, current 1 guilty? yes
> <0> [574.305611] <idle>-0 7dNs2 538585063us : __execlists_reset: 0000:00:02.0 rcs0: replay {head:0000, tail:0068}
> <0> [574.306565] <idle>-0 7.Ns1 538588457us : intel_engine_cancel_stop_cs: 0000:00:02.0 rcs0:
> <0> [574.306565] <idle>-0 7dNs2 538588462us : __i915_request_submit: 0000:00:02.0 rcs0: fence f51c:2, current 0
> <0> [574.306565] <idle>-0 7dNs2 538588471us : trace_ports: 0000:00:02.0 rcs0: submit { f51c:2, 0:0 }
> <0> [574.306565] <idle>-0 7.Ns1 538588474us : execlists_reset_finish: 0000:00:02.0 rcs0: depth->1
> <0> [574.306565] kworker/-202 2.... 538588755us : i915_request_retire: 0000:00:02.0 rcs0: fence f51c:2, current 2
> <0> [574.306565] ksoftirq-46 7..s. 538588773us : process_csb: 0000:00:02.0 rcs0: cs-irq head=11, tail=1
> <0> [574.306565] ksoftirq-46 7..s. 538588774us : process_csb: 0000:00:02.0 rcs0: csb[0]: status=0x10000001:0x00000000
> <0> [574.306565] ksoftirq-46 7..s. 538588776us : trace_ports: 0000:00:02.0 rcs0: promote { f51c:2!, 0:0 }
> <0> [574.306565] ksoftirq-46 7..s. 538588778us : process_csb: 0000:00:02.0 rcs0: csb[1]: status=0x10000018:0x00000020
> <0> [574.306565] ksoftirq-46 7..s. 538588779us : trace_ports: 0000:00:02.0 rcs0: completed { f51c:2!, 0:0 }
> <0> [574.306565] kworker/-202 2.... 538588826us : intel_context_unpin: 0000:00:02.0 rcs0: context:f51c unpin
> <0> [574.306565] i915_sel-6278 6.... 538589663us : __intel_gt_set_wedged.part.32: 0000:00:02.0 start
> <0> [574.306565] i915_sel-6278 6.... 538589667us : execlists_reset_prepare: 0000:00:02.0 rcs0: depth<-0
> <0> [574.306565] i915_sel-6278 6.... 538589710us : intel_engine_stop_cs: 0000:00:02.0 rcs0:
> <0> [574.306565] i915_sel-6278 6.... 538589732us : execlists_reset_prepare: 0000:00:02.0 bcs0: depth<-0
> <0> [574.307591] i915_sel-6278 6.... 538589733us : intel_engine_stop_cs: 0000:00:02.0 bcs0:
> <0> [574.307591] i915_sel-6278 6.... 538589757us : execlists_reset_prepare: 0000:00:02.0 vcs0: depth<-0
> <0> [574.307591] i915_sel-6278 6.... 538589758us : intel_engine_stop_cs: 0000:00:02.0 vcs0:
> <0> [574.307591] i915_sel-6278 6.... 538589771us : execlists_reset_prepare: 0000:00:02.0 vcs1: depth<-0
> <0> [574.307591] i915_sel-6278 6.... 538589772us : intel_engine_stop_cs: 0000:00:02.0 vcs1:
> <0> [574.307591] i915_sel-6278 6.... 538589778us : execlists_reset_prepare: 0000:00:02.0 vecs0: depth<-0
> <0> [574.307591] i915_sel-6278 6.... 538589780us : intel_engine_stop_cs: 0000:00:02.0 vecs0:
> <0> [574.307591] i915_sel-6278 6.... 538589786us : __intel_gt_reset: 0000:00:02.0 engine_mask=ff
> <0> [574.307591] i915_sel-6278 6.... 538591175us : execlists_reset_cancel: 0000:00:02.0 rcs0:
> <0> [574.307591] i915_sel-6278 6.... 538591970us : execlists_reset_cancel: 0000:00:02.0 bcs0:
> <0> [574.307591] i915_sel-6278 6.... 538591982us : execlists_reset_cancel: 0000:00:02.0 vcs0:
> <0> [574.307591] i915_sel-6278 6.... 538591996us : execlists_reset_cancel: 0000:00:02.0 vcs1:
> <0> [574.307591] i915_sel-6278 6.... 538592759us : execlists_reset_cancel: 0000:00:02.0 vecs0:
> <0> [574.307591] i915_sel-6278 6.... 538592977us : execlists_reset_finish: 0000:00:02.0 rcs0: depth->0
> <0> [574.307591] i915_sel-6278 6.N.. 538592996us : execlists_reset_finish: 0000:00:02.0 bcs0: depth->0
> <0> [574.307591] i915_sel-6278 6.N.. 538593023us : execlists_reset_finish: 0000:00:02.0 vcs0: depth->0
> <0> [574.307591] i915_sel-6278 6.N.. 538593037us : execlists_reset_finish: 0000:00:02.0 vcs1: depth->0
> <0> [574.307591] i915_sel-6278 6.N.. 538593051us : execlists_reset_finish: 0000:00:02.0 vecs0: depth->0
> <0> [574.307591] i915_sel-6278 6.... 538593407us : __intel_gt_set_wedged.part.32: 0000:00:02.0 end
> <0> [574.307591] kworker/-210 7d..1 551958381us : execlists_unhold: 0000:00:02.0 rcs0: fence f51b:2, current 2 hold release
> <0> [574.307591] i915_sel-6278 0.... 559490788us : i915_request_retire: 0000:00:02.0 rcs0: fence f51b:2, current 2
> <0> [574.307591] i915_sel-6278 0.... 559490793us : intel_context_unpin: 0000:00:02.0 rcs0: context:f51b unpin
> <0> [574.307591] i915_sel-6278 0.... 559490798us : __engine_park: 0000:00:02.0 rcs0: parked
> <0> [574.307591] i915_sel-6278 0.... 559490982us : __intel_context_retire: 0000:00:02.0 rcs0: context:f51c retire runtime: { total:30004ns, avg:30004ns }
> <0> [574.307591] i915_sel-6278 0.... 559491372us : __engine_park: __engine_park:261 GEM_BUG_ON(engine->execlists.queue_priority_hint != (-((int)(~0U >> 1)) - 1))
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 39b0125b7143..35c5cf786726 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -3724,7 +3724,10 @@ static void execlists_reset_rewind(struct intel_engine_cs *engine, bool stalled)
>
> static void nop_submission_tasklet(unsigned long data)
> {
> + struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
> +
> /* The driver is wedged; don't process any more events. */
> + WRITE_ONCE(engine->execlists.queue_priority_hint, INT_MIN);
Why from the tasklet and not the place which clears the queue?
Regards,
Tvrtko
> }
>
> static void execlists_reset_cancel(struct intel_engine_cs *engine)
>
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^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH 09/20] drm/i915/gt: Reset queue_priority_hint after wedging
2020-02-28 12:10 ` Tvrtko Ursulin
@ 2020-02-28 12:31 ` Chris Wilson
2020-02-28 12:59 ` Tvrtko Ursulin
0 siblings, 1 reply; 51+ messages in thread
From: Chris Wilson @ 2020-02-28 12:31 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx
Quoting Tvrtko Ursulin (2020-02-28 12:10:23)
>
> On 27/02/2020 08:57, Chris Wilson wrote:
> > An odd and highly unlikely path caught us out. On delayed submission
> > (due to an asynchronous reset handler), we poked the priority_hint and
> > kicked the tasklet. However, we had already marked the device as wedged
> > and swapped out the tasklet for a no-op. The result was that we never
> > cleared the priority hint and became upset when we later checked.
> >
> > <0> [574.303565] i915_sel-6278 2.... 481822445us : __i915_subtests: Running intel_execlists_live_selftests/live_error_interrupt
> > <0> [574.303565] i915_sel-6278 2.... 481822472us : __engine_unpark: 0000:00:02.0 rcs0:
> > <0> [574.303565] i915_sel-6278 2.... 481822491us : __gt_unpark: 0000:00:02.0
> > <0> [574.303565] i915_sel-6278 2.... 481823220us : execlists_context_reset: 0000:00:02.0 rcs0: context:f4ee reset
> > <0> [574.303565] i915_sel-6278 2.... 481824830us : __intel_context_active: 0000:00:02.0 rcs0: context:f51b active
> > <0> [574.303565] i915_sel-6278 2.... 481825258us : __intel_context_do_pin: 0000:00:02.0 rcs0: context:f51b pin ring:{start:00006000, head:0000, tail:0000}
> > <0> [574.303565] i915_sel-6278 2.... 481825311us : __i915_request_commit: 0000:00:02.0 rcs0: fence f51b:2, current 0
> > <0> [574.303565] i915_sel-6278 2d..1 481825347us : __i915_request_submit: 0000:00:02.0 rcs0: fence f51b:2, current 0
> > <0> [574.303565] i915_sel-6278 2d..1 481825363us : trace_ports: 0000:00:02.0 rcs0: submit { f51b:2, 0:0 }
> > <0> [574.303565] i915_sel-6278 2.... 481826809us : __intel_context_active: 0000:00:02.0 rcs0: context:f51c active
> > <0> [574.303565] <idle>-0 7d.h2 481827326us : cs_irq_handler: 0000:00:02.0 rcs0: CS error: 1
> > <0> [574.303565] <idle>-0 7..s1 481827377us : process_csb: 0000:00:02.0 rcs0: cs-irq head=3, tail=4
> > <0> [574.303565] <idle>-0 7..s1 481827379us : process_csb: 0000:00:02.0 rcs0: csb[4]: status=0x10000001:0x00000000
> > <0> [574.305593] <idle>-0 7..s1 481827385us : trace_ports: 0000:00:02.0 rcs0: promote { f51b:2*, 0:0 }
> > <0> [574.305611] <idle>-0 7..s1 481828179us : execlists_reset: 0000:00:02.0 rcs0: reset for CS error
> > <0> [574.305611] i915_sel-6278 2.... 481828284us : __intel_context_do_pin: 0000:00:02.0 rcs0: context:f51c pin ring:{start:00007000, head:0000, tail:0000}
> > <0> [574.305611] i915_sel-6278 2.... 481828345us : __i915_request_commit: 0000:00:02.0 rcs0: fence f51c:2, current 0
> > <0> [574.305611] <idle>-0 7dNs2 481847823us : __i915_request_unsubmit: 0000:00:02.0 rcs0: fence f51b:2, current 1
> > <0> [574.305611] <idle>-0 7dNs2 481847857us : execlists_hold: 0000:00:02.0 rcs0: fence f51b:2, current 1 on hold
> > <0> [574.305611] <idle>-0 7.Ns1 481847863us : intel_engine_reset: 0000:00:02.0 rcs0: flags=4
> > <0> [574.305611] <idle>-0 7.Ns1 481847945us : execlists_reset_prepare: 0000:00:02.0 rcs0: depth<-1
> > <0> [574.305611] <idle>-0 7.Ns1 481847946us : intel_engine_stop_cs: 0000:00:02.0 rcs0:
> > <0> [574.305611] <idle>-0 7.Ns1 538584284us : intel_engine_stop_cs: 0000:00:02.0 rcs0: timed out on STOP_RING -> IDLE
> > <0> [574.305611] <idle>-0 7.Ns1 538584347us : __intel_gt_reset: 0000:00:02.0 engine_mask=1
> > <0> [574.305611] <idle>-0 7.Ns1 538584406us : execlists_reset_rewind: 0000:00:02.0 rcs0:
> > <0> [574.305611] <idle>-0 7dNs2 538585050us : __i915_request_reset: 0000:00:02.0 rcs0: fence f51b:2, current 1 guilty? yes
> > <0> [574.305611] <idle>-0 7dNs2 538585063us : __execlists_reset: 0000:00:02.0 rcs0: replay {head:0000, tail:0068}
> > <0> [574.306565] <idle>-0 7.Ns1 538588457us : intel_engine_cancel_stop_cs: 0000:00:02.0 rcs0:
> > <0> [574.306565] <idle>-0 7dNs2 538588462us : __i915_request_submit: 0000:00:02.0 rcs0: fence f51c:2, current 0
> > <0> [574.306565] <idle>-0 7dNs2 538588471us : trace_ports: 0000:00:02.0 rcs0: submit { f51c:2, 0:0 }
> > <0> [574.306565] <idle>-0 7.Ns1 538588474us : execlists_reset_finish: 0000:00:02.0 rcs0: depth->1
> > <0> [574.306565] kworker/-202 2.... 538588755us : i915_request_retire: 0000:00:02.0 rcs0: fence f51c:2, current 2
> > <0> [574.306565] ksoftirq-46 7..s. 538588773us : process_csb: 0000:00:02.0 rcs0: cs-irq head=11, tail=1
> > <0> [574.306565] ksoftirq-46 7..s. 538588774us : process_csb: 0000:00:02.0 rcs0: csb[0]: status=0x10000001:0x00000000
> > <0> [574.306565] ksoftirq-46 7..s. 538588776us : trace_ports: 0000:00:02.0 rcs0: promote { f51c:2!, 0:0 }
> > <0> [574.306565] ksoftirq-46 7..s. 538588778us : process_csb: 0000:00:02.0 rcs0: csb[1]: status=0x10000018:0x00000020
> > <0> [574.306565] ksoftirq-46 7..s. 538588779us : trace_ports: 0000:00:02.0 rcs0: completed { f51c:2!, 0:0 }
> > <0> [574.306565] kworker/-202 2.... 538588826us : intel_context_unpin: 0000:00:02.0 rcs0: context:f51c unpin
> > <0> [574.306565] i915_sel-6278 6.... 538589663us : __intel_gt_set_wedged.part.32: 0000:00:02.0 start
> > <0> [574.306565] i915_sel-6278 6.... 538589667us : execlists_reset_prepare: 0000:00:02.0 rcs0: depth<-0
> > <0> [574.306565] i915_sel-6278 6.... 538589710us : intel_engine_stop_cs: 0000:00:02.0 rcs0:
> > <0> [574.306565] i915_sel-6278 6.... 538589732us : execlists_reset_prepare: 0000:00:02.0 bcs0: depth<-0
> > <0> [574.307591] i915_sel-6278 6.... 538589733us : intel_engine_stop_cs: 0000:00:02.0 bcs0:
> > <0> [574.307591] i915_sel-6278 6.... 538589757us : execlists_reset_prepare: 0000:00:02.0 vcs0: depth<-0
> > <0> [574.307591] i915_sel-6278 6.... 538589758us : intel_engine_stop_cs: 0000:00:02.0 vcs0:
> > <0> [574.307591] i915_sel-6278 6.... 538589771us : execlists_reset_prepare: 0000:00:02.0 vcs1: depth<-0
> > <0> [574.307591] i915_sel-6278 6.... 538589772us : intel_engine_stop_cs: 0000:00:02.0 vcs1:
> > <0> [574.307591] i915_sel-6278 6.... 538589778us : execlists_reset_prepare: 0000:00:02.0 vecs0: depth<-0
> > <0> [574.307591] i915_sel-6278 6.... 538589780us : intel_engine_stop_cs: 0000:00:02.0 vecs0:
> > <0> [574.307591] i915_sel-6278 6.... 538589786us : __intel_gt_reset: 0000:00:02.0 engine_mask=ff
> > <0> [574.307591] i915_sel-6278 6.... 538591175us : execlists_reset_cancel: 0000:00:02.0 rcs0:
> > <0> [574.307591] i915_sel-6278 6.... 538591970us : execlists_reset_cancel: 0000:00:02.0 bcs0:
> > <0> [574.307591] i915_sel-6278 6.... 538591982us : execlists_reset_cancel: 0000:00:02.0 vcs0:
> > <0> [574.307591] i915_sel-6278 6.... 538591996us : execlists_reset_cancel: 0000:00:02.0 vcs1:
> > <0> [574.307591] i915_sel-6278 6.... 538592759us : execlists_reset_cancel: 0000:00:02.0 vecs0:
> > <0> [574.307591] i915_sel-6278 6.... 538592977us : execlists_reset_finish: 0000:00:02.0 rcs0: depth->0
> > <0> [574.307591] i915_sel-6278 6.N.. 538592996us : execlists_reset_finish: 0000:00:02.0 bcs0: depth->0
> > <0> [574.307591] i915_sel-6278 6.N.. 538593023us : execlists_reset_finish: 0000:00:02.0 vcs0: depth->0
> > <0> [574.307591] i915_sel-6278 6.N.. 538593037us : execlists_reset_finish: 0000:00:02.0 vcs1: depth->0
> > <0> [574.307591] i915_sel-6278 6.N.. 538593051us : execlists_reset_finish: 0000:00:02.0 vecs0: depth->0
> > <0> [574.307591] i915_sel-6278 6.... 538593407us : __intel_gt_set_wedged.part.32: 0000:00:02.0 end
> > <0> [574.307591] kworker/-210 7d..1 551958381us : execlists_unhold: 0000:00:02.0 rcs0: fence f51b:2, current 2 hold release
> > <0> [574.307591] i915_sel-6278 0.... 559490788us : i915_request_retire: 0000:00:02.0 rcs0: fence f51b:2, current 2
> > <0> [574.307591] i915_sel-6278 0.... 559490793us : intel_context_unpin: 0000:00:02.0 rcs0: context:f51b unpin
> > <0> [574.307591] i915_sel-6278 0.... 559490798us : __engine_park: 0000:00:02.0 rcs0: parked
> > <0> [574.307591] i915_sel-6278 0.... 559490982us : __intel_context_retire: 0000:00:02.0 rcs0: context:f51c retire runtime: { total:30004ns, avg:30004ns }
> > <0> [574.307591] i915_sel-6278 0.... 559491372us : __engine_park: __engine_park:261 GEM_BUG_ON(engine->execlists.queue_priority_hint != (-((int)(~0U >> 1)) - 1))
> >
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > ---
> > drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > index 39b0125b7143..35c5cf786726 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > @@ -3724,7 +3724,10 @@ static void execlists_reset_rewind(struct intel_engine_cs *engine, bool stalled)
> >
> > static void nop_submission_tasklet(unsigned long data)
> > {
> > + struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
> > +
> > /* The driver is wedged; don't process any more events. */
> > + WRITE_ONCE(engine->execlists.queue_priority_hint, INT_MIN);
>
> Why from the tasklet and not the place which clears the queue?
That would be the list_move within nop_submit_request()
[i915_request_submit]
I chose this tasklet as we do the reset in execlists_submission_tasklet()
on clearing the queue there, and so thought this was analogous.
-Chris
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^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH 09/20] drm/i915/gt: Reset queue_priority_hint after wedging
2020-02-28 12:31 ` Chris Wilson
@ 2020-02-28 12:59 ` Tvrtko Ursulin
2020-02-28 13:10 ` Chris Wilson
0 siblings, 1 reply; 51+ messages in thread
From: Tvrtko Ursulin @ 2020-02-28 12:59 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 28/02/2020 12:31, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2020-02-28 12:10:23)
>>
>> On 27/02/2020 08:57, Chris Wilson wrote:
>>> An odd and highly unlikely path caught us out. On delayed submission
>>> (due to an asynchronous reset handler), we poked the priority_hint and
>>> kicked the tasklet. However, we had already marked the device as wedged
>>> and swapped out the tasklet for a no-op. The result was that we never
>>> cleared the priority hint and became upset when we later checked.
>>>
>>> <0> [574.303565] i915_sel-6278 2.... 481822445us : __i915_subtests: Running intel_execlists_live_selftests/live_error_interrupt
>>> <0> [574.303565] i915_sel-6278 2.... 481822472us : __engine_unpark: 0000:00:02.0 rcs0:
>>> <0> [574.303565] i915_sel-6278 2.... 481822491us : __gt_unpark: 0000:00:02.0
>>> <0> [574.303565] i915_sel-6278 2.... 481823220us : execlists_context_reset: 0000:00:02.0 rcs0: context:f4ee reset
>>> <0> [574.303565] i915_sel-6278 2.... 481824830us : __intel_context_active: 0000:00:02.0 rcs0: context:f51b active
>>> <0> [574.303565] i915_sel-6278 2.... 481825258us : __intel_context_do_pin: 0000:00:02.0 rcs0: context:f51b pin ring:{start:00006000, head:0000, tail:0000}
>>> <0> [574.303565] i915_sel-6278 2.... 481825311us : __i915_request_commit: 0000:00:02.0 rcs0: fence f51b:2, current 0
>>> <0> [574.303565] i915_sel-6278 2d..1 481825347us : __i915_request_submit: 0000:00:02.0 rcs0: fence f51b:2, current 0
>>> <0> [574.303565] i915_sel-6278 2d..1 481825363us : trace_ports: 0000:00:02.0 rcs0: submit { f51b:2, 0:0 }
>>> <0> [574.303565] i915_sel-6278 2.... 481826809us : __intel_context_active: 0000:00:02.0 rcs0: context:f51c active
>>> <0> [574.303565] <idle>-0 7d.h2 481827326us : cs_irq_handler: 0000:00:02.0 rcs0: CS error: 1
>>> <0> [574.303565] <idle>-0 7..s1 481827377us : process_csb: 0000:00:02.0 rcs0: cs-irq head=3, tail=4
>>> <0> [574.303565] <idle>-0 7..s1 481827379us : process_csb: 0000:00:02.0 rcs0: csb[4]: status=0x10000001:0x00000000
>>> <0> [574.305593] <idle>-0 7..s1 481827385us : trace_ports: 0000:00:02.0 rcs0: promote { f51b:2*, 0:0 }
>>> <0> [574.305611] <idle>-0 7..s1 481828179us : execlists_reset: 0000:00:02.0 rcs0: reset for CS error
>>> <0> [574.305611] i915_sel-6278 2.... 481828284us : __intel_context_do_pin: 0000:00:02.0 rcs0: context:f51c pin ring:{start:00007000, head:0000, tail:0000}
>>> <0> [574.305611] i915_sel-6278 2.... 481828345us : __i915_request_commit: 0000:00:02.0 rcs0: fence f51c:2, current 0
>>> <0> [574.305611] <idle>-0 7dNs2 481847823us : __i915_request_unsubmit: 0000:00:02.0 rcs0: fence f51b:2, current 1
>>> <0> [574.305611] <idle>-0 7dNs2 481847857us : execlists_hold: 0000:00:02.0 rcs0: fence f51b:2, current 1 on hold
>>> <0> [574.305611] <idle>-0 7.Ns1 481847863us : intel_engine_reset: 0000:00:02.0 rcs0: flags=4
>>> <0> [574.305611] <idle>-0 7.Ns1 481847945us : execlists_reset_prepare: 0000:00:02.0 rcs0: depth<-1
>>> <0> [574.305611] <idle>-0 7.Ns1 481847946us : intel_engine_stop_cs: 0000:00:02.0 rcs0:
>>> <0> [574.305611] <idle>-0 7.Ns1 538584284us : intel_engine_stop_cs: 0000:00:02.0 rcs0: timed out on STOP_RING -> IDLE
>>> <0> [574.305611] <idle>-0 7.Ns1 538584347us : __intel_gt_reset: 0000:00:02.0 engine_mask=1
>>> <0> [574.305611] <idle>-0 7.Ns1 538584406us : execlists_reset_rewind: 0000:00:02.0 rcs0:
>>> <0> [574.305611] <idle>-0 7dNs2 538585050us : __i915_request_reset: 0000:00:02.0 rcs0: fence f51b:2, current 1 guilty? yes
>>> <0> [574.305611] <idle>-0 7dNs2 538585063us : __execlists_reset: 0000:00:02.0 rcs0: replay {head:0000, tail:0068}
>>> <0> [574.306565] <idle>-0 7.Ns1 538588457us : intel_engine_cancel_stop_cs: 0000:00:02.0 rcs0:
>>> <0> [574.306565] <idle>-0 7dNs2 538588462us : __i915_request_submit: 0000:00:02.0 rcs0: fence f51c:2, current 0
>>> <0> [574.306565] <idle>-0 7dNs2 538588471us : trace_ports: 0000:00:02.0 rcs0: submit { f51c:2, 0:0 }
>>> <0> [574.306565] <idle>-0 7.Ns1 538588474us : execlists_reset_finish: 0000:00:02.0 rcs0: depth->1
>>> <0> [574.306565] kworker/-202 2.... 538588755us : i915_request_retire: 0000:00:02.0 rcs0: fence f51c:2, current 2
>>> <0> [574.306565] ksoftirq-46 7..s. 538588773us : process_csb: 0000:00:02.0 rcs0: cs-irq head=11, tail=1
>>> <0> [574.306565] ksoftirq-46 7..s. 538588774us : process_csb: 0000:00:02.0 rcs0: csb[0]: status=0x10000001:0x00000000
>>> <0> [574.306565] ksoftirq-46 7..s. 538588776us : trace_ports: 0000:00:02.0 rcs0: promote { f51c:2!, 0:0 }
>>> <0> [574.306565] ksoftirq-46 7..s. 538588778us : process_csb: 0000:00:02.0 rcs0: csb[1]: status=0x10000018:0x00000020
>>> <0> [574.306565] ksoftirq-46 7..s. 538588779us : trace_ports: 0000:00:02.0 rcs0: completed { f51c:2!, 0:0 }
>>> <0> [574.306565] kworker/-202 2.... 538588826us : intel_context_unpin: 0000:00:02.0 rcs0: context:f51c unpin
>>> <0> [574.306565] i915_sel-6278 6.... 538589663us : __intel_gt_set_wedged.part.32: 0000:00:02.0 start
>>> <0> [574.306565] i915_sel-6278 6.... 538589667us : execlists_reset_prepare: 0000:00:02.0 rcs0: depth<-0
>>> <0> [574.306565] i915_sel-6278 6.... 538589710us : intel_engine_stop_cs: 0000:00:02.0 rcs0:
>>> <0> [574.306565] i915_sel-6278 6.... 538589732us : execlists_reset_prepare: 0000:00:02.0 bcs0: depth<-0
>>> <0> [574.307591] i915_sel-6278 6.... 538589733us : intel_engine_stop_cs: 0000:00:02.0 bcs0:
>>> <0> [574.307591] i915_sel-6278 6.... 538589757us : execlists_reset_prepare: 0000:00:02.0 vcs0: depth<-0
>>> <0> [574.307591] i915_sel-6278 6.... 538589758us : intel_engine_stop_cs: 0000:00:02.0 vcs0:
>>> <0> [574.307591] i915_sel-6278 6.... 538589771us : execlists_reset_prepare: 0000:00:02.0 vcs1: depth<-0
>>> <0> [574.307591] i915_sel-6278 6.... 538589772us : intel_engine_stop_cs: 0000:00:02.0 vcs1:
>>> <0> [574.307591] i915_sel-6278 6.... 538589778us : execlists_reset_prepare: 0000:00:02.0 vecs0: depth<-0
>>> <0> [574.307591] i915_sel-6278 6.... 538589780us : intel_engine_stop_cs: 0000:00:02.0 vecs0:
>>> <0> [574.307591] i915_sel-6278 6.... 538589786us : __intel_gt_reset: 0000:00:02.0 engine_mask=ff
>>> <0> [574.307591] i915_sel-6278 6.... 538591175us : execlists_reset_cancel: 0000:00:02.0 rcs0:
>>> <0> [574.307591] i915_sel-6278 6.... 538591970us : execlists_reset_cancel: 0000:00:02.0 bcs0:
>>> <0> [574.307591] i915_sel-6278 6.... 538591982us : execlists_reset_cancel: 0000:00:02.0 vcs0:
>>> <0> [574.307591] i915_sel-6278 6.... 538591996us : execlists_reset_cancel: 0000:00:02.0 vcs1:
>>> <0> [574.307591] i915_sel-6278 6.... 538592759us : execlists_reset_cancel: 0000:00:02.0 vecs0:
>>> <0> [574.307591] i915_sel-6278 6.... 538592977us : execlists_reset_finish: 0000:00:02.0 rcs0: depth->0
>>> <0> [574.307591] i915_sel-6278 6.N.. 538592996us : execlists_reset_finish: 0000:00:02.0 bcs0: depth->0
>>> <0> [574.307591] i915_sel-6278 6.N.. 538593023us : execlists_reset_finish: 0000:00:02.0 vcs0: depth->0
>>> <0> [574.307591] i915_sel-6278 6.N.. 538593037us : execlists_reset_finish: 0000:00:02.0 vcs1: depth->0
>>> <0> [574.307591] i915_sel-6278 6.N.. 538593051us : execlists_reset_finish: 0000:00:02.0 vecs0: depth->0
>>> <0> [574.307591] i915_sel-6278 6.... 538593407us : __intel_gt_set_wedged.part.32: 0000:00:02.0 end
>>> <0> [574.307591] kworker/-210 7d..1 551958381us : execlists_unhold: 0000:00:02.0 rcs0: fence f51b:2, current 2 hold release
>>> <0> [574.307591] i915_sel-6278 0.... 559490788us : i915_request_retire: 0000:00:02.0 rcs0: fence f51b:2, current 2
>>> <0> [574.307591] i915_sel-6278 0.... 559490793us : intel_context_unpin: 0000:00:02.0 rcs0: context:f51b unpin
>>> <0> [574.307591] i915_sel-6278 0.... 559490798us : __engine_park: 0000:00:02.0 rcs0: parked
>>> <0> [574.307591] i915_sel-6278 0.... 559490982us : __intel_context_retire: 0000:00:02.0 rcs0: context:f51c retire runtime: { total:30004ns, avg:30004ns }
>>> <0> [574.307591] i915_sel-6278 0.... 559491372us : __engine_park: __engine_park:261 GEM_BUG_ON(engine->execlists.queue_priority_hint != (-((int)(~0U >> 1)) - 1))
>>>
>>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>>> ---
>>> drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
>>> 1 file changed, 3 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
>>> index 39b0125b7143..35c5cf786726 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
>>> @@ -3724,7 +3724,10 @@ static void execlists_reset_rewind(struct intel_engine_cs *engine, bool stalled)
>>>
>>> static void nop_submission_tasklet(unsigned long data)
>>> {
>>> + struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
>>> +
>>> /* The driver is wedged; don't process any more events. */
>>> + WRITE_ONCE(engine->execlists.queue_priority_hint, INT_MIN);
>>
>> Why from the tasklet and not the place which clears the queue?
>
> That would be the list_move within nop_submit_request()
> [i915_request_submit]
>
> I chose this tasklet as we do the reset in execlists_submission_tasklet()
> on clearing the queue there, and so thought this was analogous.
It actually looks to me it is unhold which is causing this, so it is not
true we never reset the hint, it was probably overwritten:
execlists_reset_cancel, at the end of it:
/* Remaining _unready_ requests will be nop'ed when submitted */
execlists->queue_priority_hint = INT_MIN;
Just who overwrote it.. someone called unhold after
execlists_reset_cancel finished.
Should unhold not restore the priority hint if the requests on the hold
list are -EIO?
Regards,
Tvrtko
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^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH 09/20] drm/i915/gt: Reset queue_priority_hint after wedging
2020-02-28 12:59 ` Tvrtko Ursulin
@ 2020-02-28 13:10 ` Chris Wilson
2020-02-28 13:20 ` Tvrtko Ursulin
0 siblings, 1 reply; 51+ messages in thread
From: Chris Wilson @ 2020-02-28 13:10 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx
Quoting Tvrtko Ursulin (2020-02-28 12:59:37)
>
> On 28/02/2020 12:31, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2020-02-28 12:10:23)
> >>
> >> On 27/02/2020 08:57, Chris Wilson wrote:
> >>> An odd and highly unlikely path caught us out. On delayed submission
> >>> (due to an asynchronous reset handler), we poked the priority_hint and
> >>> kicked the tasklet. However, we had already marked the device as wedged
> >>> and swapped out the tasklet for a no-op. The result was that we never
> >>> cleared the priority hint and became upset when we later checked.
> >>>
> >>> <0> [574.303565] i915_sel-6278 2.... 481822445us : __i915_subtests: Running intel_execlists_live_selftests/live_error_interrupt
> >>> <0> [574.303565] i915_sel-6278 2.... 481822472us : __engine_unpark: 0000:00:02.0 rcs0:
> >>> <0> [574.303565] i915_sel-6278 2.... 481822491us : __gt_unpark: 0000:00:02.0
> >>> <0> [574.303565] i915_sel-6278 2.... 481823220us : execlists_context_reset: 0000:00:02.0 rcs0: context:f4ee reset
> >>> <0> [574.303565] i915_sel-6278 2.... 481824830us : __intel_context_active: 0000:00:02.0 rcs0: context:f51b active
> >>> <0> [574.303565] i915_sel-6278 2.... 481825258us : __intel_context_do_pin: 0000:00:02.0 rcs0: context:f51b pin ring:{start:00006000, head:0000, tail:0000}
> >>> <0> [574.303565] i915_sel-6278 2.... 481825311us : __i915_request_commit: 0000:00:02.0 rcs0: fence f51b:2, current 0
> >>> <0> [574.303565] i915_sel-6278 2d..1 481825347us : __i915_request_submit: 0000:00:02.0 rcs0: fence f51b:2, current 0
> >>> <0> [574.303565] i915_sel-6278 2d..1 481825363us : trace_ports: 0000:00:02.0 rcs0: submit { f51b:2, 0:0 }
> >>> <0> [574.303565] i915_sel-6278 2.... 481826809us : __intel_context_active: 0000:00:02.0 rcs0: context:f51c active
> >>> <0> [574.303565] <idle>-0 7d.h2 481827326us : cs_irq_handler: 0000:00:02.0 rcs0: CS error: 1
> >>> <0> [574.303565] <idle>-0 7..s1 481827377us : process_csb: 0000:00:02.0 rcs0: cs-irq head=3, tail=4
> >>> <0> [574.303565] <idle>-0 7..s1 481827379us : process_csb: 0000:00:02.0 rcs0: csb[4]: status=0x10000001:0x00000000
> >>> <0> [574.305593] <idle>-0 7..s1 481827385us : trace_ports: 0000:00:02.0 rcs0: promote { f51b:2*, 0:0 }
> >>> <0> [574.305611] <idle>-0 7..s1 481828179us : execlists_reset: 0000:00:02.0 rcs0: reset for CS error
> >>> <0> [574.305611] i915_sel-6278 2.... 481828284us : __intel_context_do_pin: 0000:00:02.0 rcs0: context:f51c pin ring:{start:00007000, head:0000, tail:0000}
> >>> <0> [574.305611] i915_sel-6278 2.... 481828345us : __i915_request_commit: 0000:00:02.0 rcs0: fence f51c:2, current 0
> >>> <0> [574.305611] <idle>-0 7dNs2 481847823us : __i915_request_unsubmit: 0000:00:02.0 rcs0: fence f51b:2, current 1
> >>> <0> [574.305611] <idle>-0 7dNs2 481847857us : execlists_hold: 0000:00:02.0 rcs0: fence f51b:2, current 1 on hold
> >>> <0> [574.305611] <idle>-0 7.Ns1 481847863us : intel_engine_reset: 0000:00:02.0 rcs0: flags=4
> >>> <0> [574.305611] <idle>-0 7.Ns1 481847945us : execlists_reset_prepare: 0000:00:02.0 rcs0: depth<-1
> >>> <0> [574.305611] <idle>-0 7.Ns1 481847946us : intel_engine_stop_cs: 0000:00:02.0 rcs0:
> >>> <0> [574.305611] <idle>-0 7.Ns1 538584284us : intel_engine_stop_cs: 0000:00:02.0 rcs0: timed out on STOP_RING -> IDLE
> >>> <0> [574.305611] <idle>-0 7.Ns1 538584347us : __intel_gt_reset: 0000:00:02.0 engine_mask=1
> >>> <0> [574.305611] <idle>-0 7.Ns1 538584406us : execlists_reset_rewind: 0000:00:02.0 rcs0:
> >>> <0> [574.305611] <idle>-0 7dNs2 538585050us : __i915_request_reset: 0000:00:02.0 rcs0: fence f51b:2, current 1 guilty? yes
> >>> <0> [574.305611] <idle>-0 7dNs2 538585063us : __execlists_reset: 0000:00:02.0 rcs0: replay {head:0000, tail:0068}
> >>> <0> [574.306565] <idle>-0 7.Ns1 538588457us : intel_engine_cancel_stop_cs: 0000:00:02.0 rcs0:
> >>> <0> [574.306565] <idle>-0 7dNs2 538588462us : __i915_request_submit: 0000:00:02.0 rcs0: fence f51c:2, current 0
> >>> <0> [574.306565] <idle>-0 7dNs2 538588471us : trace_ports: 0000:00:02.0 rcs0: submit { f51c:2, 0:0 }
> >>> <0> [574.306565] <idle>-0 7.Ns1 538588474us : execlists_reset_finish: 0000:00:02.0 rcs0: depth->1
> >>> <0> [574.306565] kworker/-202 2.... 538588755us : i915_request_retire: 0000:00:02.0 rcs0: fence f51c:2, current 2
> >>> <0> [574.306565] ksoftirq-46 7..s. 538588773us : process_csb: 0000:00:02.0 rcs0: cs-irq head=11, tail=1
> >>> <0> [574.306565] ksoftirq-46 7..s. 538588774us : process_csb: 0000:00:02.0 rcs0: csb[0]: status=0x10000001:0x00000000
> >>> <0> [574.306565] ksoftirq-46 7..s. 538588776us : trace_ports: 0000:00:02.0 rcs0: promote { f51c:2!, 0:0 }
> >>> <0> [574.306565] ksoftirq-46 7..s. 538588778us : process_csb: 0000:00:02.0 rcs0: csb[1]: status=0x10000018:0x00000020
> >>> <0> [574.306565] ksoftirq-46 7..s. 538588779us : trace_ports: 0000:00:02.0 rcs0: completed { f51c:2!, 0:0 }
> >>> <0> [574.306565] kworker/-202 2.... 538588826us : intel_context_unpin: 0000:00:02.0 rcs0: context:f51c unpin
> >>> <0> [574.306565] i915_sel-6278 6.... 538589663us : __intel_gt_set_wedged.part.32: 0000:00:02.0 start
> >>> <0> [574.306565] i915_sel-6278 6.... 538589667us : execlists_reset_prepare: 0000:00:02.0 rcs0: depth<-0
> >>> <0> [574.306565] i915_sel-6278 6.... 538589710us : intel_engine_stop_cs: 0000:00:02.0 rcs0:
> >>> <0> [574.306565] i915_sel-6278 6.... 538589732us : execlists_reset_prepare: 0000:00:02.0 bcs0: depth<-0
> >>> <0> [574.307591] i915_sel-6278 6.... 538589733us : intel_engine_stop_cs: 0000:00:02.0 bcs0:
> >>> <0> [574.307591] i915_sel-6278 6.... 538589757us : execlists_reset_prepare: 0000:00:02.0 vcs0: depth<-0
> >>> <0> [574.307591] i915_sel-6278 6.... 538589758us : intel_engine_stop_cs: 0000:00:02.0 vcs0:
> >>> <0> [574.307591] i915_sel-6278 6.... 538589771us : execlists_reset_prepare: 0000:00:02.0 vcs1: depth<-0
> >>> <0> [574.307591] i915_sel-6278 6.... 538589772us : intel_engine_stop_cs: 0000:00:02.0 vcs1:
> >>> <0> [574.307591] i915_sel-6278 6.... 538589778us : execlists_reset_prepare: 0000:00:02.0 vecs0: depth<-0
> >>> <0> [574.307591] i915_sel-6278 6.... 538589780us : intel_engine_stop_cs: 0000:00:02.0 vecs0:
> >>> <0> [574.307591] i915_sel-6278 6.... 538589786us : __intel_gt_reset: 0000:00:02.0 engine_mask=ff
> >>> <0> [574.307591] i915_sel-6278 6.... 538591175us : execlists_reset_cancel: 0000:00:02.0 rcs0:
> >>> <0> [574.307591] i915_sel-6278 6.... 538591970us : execlists_reset_cancel: 0000:00:02.0 bcs0:
> >>> <0> [574.307591] i915_sel-6278 6.... 538591982us : execlists_reset_cancel: 0000:00:02.0 vcs0:
> >>> <0> [574.307591] i915_sel-6278 6.... 538591996us : execlists_reset_cancel: 0000:00:02.0 vcs1:
> >>> <0> [574.307591] i915_sel-6278 6.... 538592759us : execlists_reset_cancel: 0000:00:02.0 vecs0:
> >>> <0> [574.307591] i915_sel-6278 6.... 538592977us : execlists_reset_finish: 0000:00:02.0 rcs0: depth->0
> >>> <0> [574.307591] i915_sel-6278 6.N.. 538592996us : execlists_reset_finish: 0000:00:02.0 bcs0: depth->0
> >>> <0> [574.307591] i915_sel-6278 6.N.. 538593023us : execlists_reset_finish: 0000:00:02.0 vcs0: depth->0
> >>> <0> [574.307591] i915_sel-6278 6.N.. 538593037us : execlists_reset_finish: 0000:00:02.0 vcs1: depth->0
> >>> <0> [574.307591] i915_sel-6278 6.N.. 538593051us : execlists_reset_finish: 0000:00:02.0 vecs0: depth->0
> >>> <0> [574.307591] i915_sel-6278 6.... 538593407us : __intel_gt_set_wedged.part.32: 0000:00:02.0 end
> >>> <0> [574.307591] kworker/-210 7d..1 551958381us : execlists_unhold: 0000:00:02.0 rcs0: fence f51b:2, current 2 hold release
> >>> <0> [574.307591] i915_sel-6278 0.... 559490788us : i915_request_retire: 0000:00:02.0 rcs0: fence f51b:2, current 2
> >>> <0> [574.307591] i915_sel-6278 0.... 559490793us : intel_context_unpin: 0000:00:02.0 rcs0: context:f51b unpin
> >>> <0> [574.307591] i915_sel-6278 0.... 559490798us : __engine_park: 0000:00:02.0 rcs0: parked
> >>> <0> [574.307591] i915_sel-6278 0.... 559490982us : __intel_context_retire: 0000:00:02.0 rcs0: context:f51c retire runtime: { total:30004ns, avg:30004ns }
> >>> <0> [574.307591] i915_sel-6278 0.... 559491372us : __engine_park: __engine_park:261 GEM_BUG_ON(engine->execlists.queue_priority_hint != (-((int)(~0U >> 1)) - 1))
> >>>
> >>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> >>> ---
> >>> drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
> >>> 1 file changed, 3 insertions(+)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> >>> index 39b0125b7143..35c5cf786726 100644
> >>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> >>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> >>> @@ -3724,7 +3724,10 @@ static void execlists_reset_rewind(struct intel_engine_cs *engine, bool stalled)
> >>>
> >>> static void nop_submission_tasklet(unsigned long data)
> >>> {
> >>> + struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
> >>> +
> >>> /* The driver is wedged; don't process any more events. */
> >>> + WRITE_ONCE(engine->execlists.queue_priority_hint, INT_MIN);
> >>
> >> Why from the tasklet and not the place which clears the queue?
> >
> > That would be the list_move within nop_submit_request()
> > [i915_request_submit]
> >
> > I chose this tasklet as we do the reset in execlists_submission_tasklet()
> > on clearing the queue there, and so thought this was analogous.
>
> It actually looks to me it is unhold which is causing this, so it is not
> true we never reset the hint, it was probably overwritten:
>
> execlists_reset_cancel, at the end of it:
>
> /* Remaining _unready_ requests will be nop'ed when submitted */
>
> execlists->queue_priority_hint = INT_MIN;
>
> Just who overwrote it.. someone called unhold after
> execlists_reset_cancel finished.
>
> Should unhold not restore the priority hint if the requests on the hold
> list are -EIO?
It is the unhold callback, it does
if (rq_prio(rq) > engine->execlists.queue_priority_hint) {
engine->execlists.queue_priority_hint = rq_prio(rq);
tasklet_hi_schedule(&engine->execlists.tasklet);
}
and queues the [now] nop_submission_tasklet. Which would be fine if it
behaved similarly.
-Chris
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^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH 09/20] drm/i915/gt: Reset queue_priority_hint after wedging
2020-02-28 13:10 ` Chris Wilson
@ 2020-02-28 13:20 ` Tvrtko Ursulin
2020-02-28 13:34 ` Chris Wilson
0 siblings, 1 reply; 51+ messages in thread
From: Tvrtko Ursulin @ 2020-02-28 13:20 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 28/02/2020 13:10, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2020-02-28 12:59:37)
>>
>> On 28/02/2020 12:31, Chris Wilson wrote:
>>> Quoting Tvrtko Ursulin (2020-02-28 12:10:23)
>>>>
>>>> On 27/02/2020 08:57, Chris Wilson wrote:
>>>>> An odd and highly unlikely path caught us out. On delayed submission
>>>>> (due to an asynchronous reset handler), we poked the priority_hint and
>>>>> kicked the tasklet. However, we had already marked the device as wedged
>>>>> and swapped out the tasklet for a no-op. The result was that we never
>>>>> cleared the priority hint and became upset when we later checked.
>>>>>
>>>>> <0> [574.303565] i915_sel-6278 2.... 481822445us : __i915_subtests: Running intel_execlists_live_selftests/live_error_interrupt
>>>>> <0> [574.303565] i915_sel-6278 2.... 481822472us : __engine_unpark: 0000:00:02.0 rcs0:
>>>>> <0> [574.303565] i915_sel-6278 2.... 481822491us : __gt_unpark: 0000:00:02.0
>>>>> <0> [574.303565] i915_sel-6278 2.... 481823220us : execlists_context_reset: 0000:00:02.0 rcs0: context:f4ee reset
>>>>> <0> [574.303565] i915_sel-6278 2.... 481824830us : __intel_context_active: 0000:00:02.0 rcs0: context:f51b active
>>>>> <0> [574.303565] i915_sel-6278 2.... 481825258us : __intel_context_do_pin: 0000:00:02.0 rcs0: context:f51b pin ring:{start:00006000, head:0000, tail:0000}
>>>>> <0> [574.303565] i915_sel-6278 2.... 481825311us : __i915_request_commit: 0000:00:02.0 rcs0: fence f51b:2, current 0
>>>>> <0> [574.303565] i915_sel-6278 2d..1 481825347us : __i915_request_submit: 0000:00:02.0 rcs0: fence f51b:2, current 0
>>>>> <0> [574.303565] i915_sel-6278 2d..1 481825363us : trace_ports: 0000:00:02.0 rcs0: submit { f51b:2, 0:0 }
>>>>> <0> [574.303565] i915_sel-6278 2.... 481826809us : __intel_context_active: 0000:00:02.0 rcs0: context:f51c active
>>>>> <0> [574.303565] <idle>-0 7d.h2 481827326us : cs_irq_handler: 0000:00:02.0 rcs0: CS error: 1
>>>>> <0> [574.303565] <idle>-0 7..s1 481827377us : process_csb: 0000:00:02.0 rcs0: cs-irq head=3, tail=4
>>>>> <0> [574.303565] <idle>-0 7..s1 481827379us : process_csb: 0000:00:02.0 rcs0: csb[4]: status=0x10000001:0x00000000
>>>>> <0> [574.305593] <idle>-0 7..s1 481827385us : trace_ports: 0000:00:02.0 rcs0: promote { f51b:2*, 0:0 }
>>>>> <0> [574.305611] <idle>-0 7..s1 481828179us : execlists_reset: 0000:00:02.0 rcs0: reset for CS error
>>>>> <0> [574.305611] i915_sel-6278 2.... 481828284us : __intel_context_do_pin: 0000:00:02.0 rcs0: context:f51c pin ring:{start:00007000, head:0000, tail:0000}
>>>>> <0> [574.305611] i915_sel-6278 2.... 481828345us : __i915_request_commit: 0000:00:02.0 rcs0: fence f51c:2, current 0
>>>>> <0> [574.305611] <idle>-0 7dNs2 481847823us : __i915_request_unsubmit: 0000:00:02.0 rcs0: fence f51b:2, current 1
>>>>> <0> [574.305611] <idle>-0 7dNs2 481847857us : execlists_hold: 0000:00:02.0 rcs0: fence f51b:2, current 1 on hold
>>>>> <0> [574.305611] <idle>-0 7.Ns1 481847863us : intel_engine_reset: 0000:00:02.0 rcs0: flags=4
>>>>> <0> [574.305611] <idle>-0 7.Ns1 481847945us : execlists_reset_prepare: 0000:00:02.0 rcs0: depth<-1
>>>>> <0> [574.305611] <idle>-0 7.Ns1 481847946us : intel_engine_stop_cs: 0000:00:02.0 rcs0:
>>>>> <0> [574.305611] <idle>-0 7.Ns1 538584284us : intel_engine_stop_cs: 0000:00:02.0 rcs0: timed out on STOP_RING -> IDLE
>>>>> <0> [574.305611] <idle>-0 7.Ns1 538584347us : __intel_gt_reset: 0000:00:02.0 engine_mask=1
>>>>> <0> [574.305611] <idle>-0 7.Ns1 538584406us : execlists_reset_rewind: 0000:00:02.0 rcs0:
>>>>> <0> [574.305611] <idle>-0 7dNs2 538585050us : __i915_request_reset: 0000:00:02.0 rcs0: fence f51b:2, current 1 guilty? yes
>>>>> <0> [574.305611] <idle>-0 7dNs2 538585063us : __execlists_reset: 0000:00:02.0 rcs0: replay {head:0000, tail:0068}
>>>>> <0> [574.306565] <idle>-0 7.Ns1 538588457us : intel_engine_cancel_stop_cs: 0000:00:02.0 rcs0:
>>>>> <0> [574.306565] <idle>-0 7dNs2 538588462us : __i915_request_submit: 0000:00:02.0 rcs0: fence f51c:2, current 0
>>>>> <0> [574.306565] <idle>-0 7dNs2 538588471us : trace_ports: 0000:00:02.0 rcs0: submit { f51c:2, 0:0 }
>>>>> <0> [574.306565] <idle>-0 7.Ns1 538588474us : execlists_reset_finish: 0000:00:02.0 rcs0: depth->1
>>>>> <0> [574.306565] kworker/-202 2.... 538588755us : i915_request_retire: 0000:00:02.0 rcs0: fence f51c:2, current 2
>>>>> <0> [574.306565] ksoftirq-46 7..s. 538588773us : process_csb: 0000:00:02.0 rcs0: cs-irq head=11, tail=1
>>>>> <0> [574.306565] ksoftirq-46 7..s. 538588774us : process_csb: 0000:00:02.0 rcs0: csb[0]: status=0x10000001:0x00000000
>>>>> <0> [574.306565] ksoftirq-46 7..s. 538588776us : trace_ports: 0000:00:02.0 rcs0: promote { f51c:2!, 0:0 }
>>>>> <0> [574.306565] ksoftirq-46 7..s. 538588778us : process_csb: 0000:00:02.0 rcs0: csb[1]: status=0x10000018:0x00000020
>>>>> <0> [574.306565] ksoftirq-46 7..s. 538588779us : trace_ports: 0000:00:02.0 rcs0: completed { f51c:2!, 0:0 }
>>>>> <0> [574.306565] kworker/-202 2.... 538588826us : intel_context_unpin: 0000:00:02.0 rcs0: context:f51c unpin
>>>>> <0> [574.306565] i915_sel-6278 6.... 538589663us : __intel_gt_set_wedged.part.32: 0000:00:02.0 start
>>>>> <0> [574.306565] i915_sel-6278 6.... 538589667us : execlists_reset_prepare: 0000:00:02.0 rcs0: depth<-0
>>>>> <0> [574.306565] i915_sel-6278 6.... 538589710us : intel_engine_stop_cs: 0000:00:02.0 rcs0:
>>>>> <0> [574.306565] i915_sel-6278 6.... 538589732us : execlists_reset_prepare: 0000:00:02.0 bcs0: depth<-0
>>>>> <0> [574.307591] i915_sel-6278 6.... 538589733us : intel_engine_stop_cs: 0000:00:02.0 bcs0:
>>>>> <0> [574.307591] i915_sel-6278 6.... 538589757us : execlists_reset_prepare: 0000:00:02.0 vcs0: depth<-0
>>>>> <0> [574.307591] i915_sel-6278 6.... 538589758us : intel_engine_stop_cs: 0000:00:02.0 vcs0:
>>>>> <0> [574.307591] i915_sel-6278 6.... 538589771us : execlists_reset_prepare: 0000:00:02.0 vcs1: depth<-0
>>>>> <0> [574.307591] i915_sel-6278 6.... 538589772us : intel_engine_stop_cs: 0000:00:02.0 vcs1:
>>>>> <0> [574.307591] i915_sel-6278 6.... 538589778us : execlists_reset_prepare: 0000:00:02.0 vecs0: depth<-0
>>>>> <0> [574.307591] i915_sel-6278 6.... 538589780us : intel_engine_stop_cs: 0000:00:02.0 vecs0:
>>>>> <0> [574.307591] i915_sel-6278 6.... 538589786us : __intel_gt_reset: 0000:00:02.0 engine_mask=ff
>>>>> <0> [574.307591] i915_sel-6278 6.... 538591175us : execlists_reset_cancel: 0000:00:02.0 rcs0:
>>>>> <0> [574.307591] i915_sel-6278 6.... 538591970us : execlists_reset_cancel: 0000:00:02.0 bcs0:
>>>>> <0> [574.307591] i915_sel-6278 6.... 538591982us : execlists_reset_cancel: 0000:00:02.0 vcs0:
>>>>> <0> [574.307591] i915_sel-6278 6.... 538591996us : execlists_reset_cancel: 0000:00:02.0 vcs1:
>>>>> <0> [574.307591] i915_sel-6278 6.... 538592759us : execlists_reset_cancel: 0000:00:02.0 vecs0:
>>>>> <0> [574.307591] i915_sel-6278 6.... 538592977us : execlists_reset_finish: 0000:00:02.0 rcs0: depth->0
>>>>> <0> [574.307591] i915_sel-6278 6.N.. 538592996us : execlists_reset_finish: 0000:00:02.0 bcs0: depth->0
>>>>> <0> [574.307591] i915_sel-6278 6.N.. 538593023us : execlists_reset_finish: 0000:00:02.0 vcs0: depth->0
>>>>> <0> [574.307591] i915_sel-6278 6.N.. 538593037us : execlists_reset_finish: 0000:00:02.0 vcs1: depth->0
>>>>> <0> [574.307591] i915_sel-6278 6.N.. 538593051us : execlists_reset_finish: 0000:00:02.0 vecs0: depth->0
>>>>> <0> [574.307591] i915_sel-6278 6.... 538593407us : __intel_gt_set_wedged.part.32: 0000:00:02.0 end
>>>>> <0> [574.307591] kworker/-210 7d..1 551958381us : execlists_unhold: 0000:00:02.0 rcs0: fence f51b:2, current 2 hold release
>>>>> <0> [574.307591] i915_sel-6278 0.... 559490788us : i915_request_retire: 0000:00:02.0 rcs0: fence f51b:2, current 2
>>>>> <0> [574.307591] i915_sel-6278 0.... 559490793us : intel_context_unpin: 0000:00:02.0 rcs0: context:f51b unpin
>>>>> <0> [574.307591] i915_sel-6278 0.... 559490798us : __engine_park: 0000:00:02.0 rcs0: parked
>>>>> <0> [574.307591] i915_sel-6278 0.... 559490982us : __intel_context_retire: 0000:00:02.0 rcs0: context:f51c retire runtime: { total:30004ns, avg:30004ns }
>>>>> <0> [574.307591] i915_sel-6278 0.... 559491372us : __engine_park: __engine_park:261 GEM_BUG_ON(engine->execlists.queue_priority_hint != (-((int)(~0U >> 1)) - 1))
>>>>>
>>>>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>>>>> ---
>>>>> drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
>>>>> 1 file changed, 3 insertions(+)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
>>>>> index 39b0125b7143..35c5cf786726 100644
>>>>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
>>>>> @@ -3724,7 +3724,10 @@ static void execlists_reset_rewind(struct intel_engine_cs *engine, bool stalled)
>>>>>
>>>>> static void nop_submission_tasklet(unsigned long data)
>>>>> {
>>>>> + struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
>>>>> +
>>>>> /* The driver is wedged; don't process any more events. */
>>>>> + WRITE_ONCE(engine->execlists.queue_priority_hint, INT_MIN);
>>>>
>>>> Why from the tasklet and not the place which clears the queue?
>>>
>>> That would be the list_move within nop_submit_request()
>>> [i915_request_submit]
>>>
>>> I chose this tasklet as we do the reset in execlists_submission_tasklet()
>>> on clearing the queue there, and so thought this was analogous.
>>
>> It actually looks to me it is unhold which is causing this, so it is not
>> true we never reset the hint, it was probably overwritten:
>>
>> execlists_reset_cancel, at the end of it:
>>
>> /* Remaining _unready_ requests will be nop'ed when submitted */
>>
>> execlists->queue_priority_hint = INT_MIN;
>>
>> Just who overwrote it.. someone called unhold after
>> execlists_reset_cancel finished.
>>
>> Should unhold not restore the priority hint if the requests on the hold
>> list are -EIO?
>
> It is the unhold callback, it does
>
> if (rq_prio(rq) > engine->execlists.queue_priority_hint) {
> engine->execlists.queue_priority_hint = rq_prio(rq);
> tasklet_hi_schedule(&engine->execlists.tasklet);
> }
>
> and queues the [now] nop_submission_tasklet. Which would be fine if it
> behaved similarly.
That I found, but who calls it?
I was thinking that since execlists_reset_cancel bothers to mark held
requests with -EIO then unhold could be smarter and not consider them
when setting the priority hint.
That way the hint is immediately true, not only after tasklet is
flushed. But okay, no big deal either way.
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
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^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH 09/20] drm/i915/gt: Reset queue_priority_hint after wedging
2020-02-28 13:20 ` Tvrtko Ursulin
@ 2020-02-28 13:34 ` Chris Wilson
0 siblings, 0 replies; 51+ messages in thread
From: Chris Wilson @ 2020-02-28 13:34 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx
Quoting Tvrtko Ursulin (2020-02-28 13:20:24)
>
> On 28/02/2020 13:10, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2020-02-28 12:59:37)
> >>
> >> On 28/02/2020 12:31, Chris Wilson wrote:
> >>> Quoting Tvrtko Ursulin (2020-02-28 12:10:23)
> >>>>
> >>>> On 27/02/2020 08:57, Chris Wilson wrote:
> >>>>> An odd and highly unlikely path caught us out. On delayed submission
> >>>>> (due to an asynchronous reset handler), we poked the priority_hint and
> >>>>> kicked the tasklet. However, we had already marked the device as wedged
> >>>>> and swapped out the tasklet for a no-op. The result was that we never
> >>>>> cleared the priority hint and became upset when we later checked.
> >>>>>
> >>>>> <0> [574.303565] i915_sel-6278 2.... 481822445us : __i915_subtests: Running intel_execlists_live_selftests/live_error_interrupt
> >>>>> <0> [574.303565] i915_sel-6278 2.... 481822472us : __engine_unpark: 0000:00:02.0 rcs0:
> >>>>> <0> [574.303565] i915_sel-6278 2.... 481822491us : __gt_unpark: 0000:00:02.0
> >>>>> <0> [574.303565] i915_sel-6278 2.... 481823220us : execlists_context_reset: 0000:00:02.0 rcs0: context:f4ee reset
> >>>>> <0> [574.303565] i915_sel-6278 2.... 481824830us : __intel_context_active: 0000:00:02.0 rcs0: context:f51b active
> >>>>> <0> [574.303565] i915_sel-6278 2.... 481825258us : __intel_context_do_pin: 0000:00:02.0 rcs0: context:f51b pin ring:{start:00006000, head:0000, tail:0000}
> >>>>> <0> [574.303565] i915_sel-6278 2.... 481825311us : __i915_request_commit: 0000:00:02.0 rcs0: fence f51b:2, current 0
> >>>>> <0> [574.303565] i915_sel-6278 2d..1 481825347us : __i915_request_submit: 0000:00:02.0 rcs0: fence f51b:2, current 0
> >>>>> <0> [574.303565] i915_sel-6278 2d..1 481825363us : trace_ports: 0000:00:02.0 rcs0: submit { f51b:2, 0:0 }
> >>>>> <0> [574.303565] i915_sel-6278 2.... 481826809us : __intel_context_active: 0000:00:02.0 rcs0: context:f51c active
> >>>>> <0> [574.303565] <idle>-0 7d.h2 481827326us : cs_irq_handler: 0000:00:02.0 rcs0: CS error: 1
> >>>>> <0> [574.303565] <idle>-0 7..s1 481827377us : process_csb: 0000:00:02.0 rcs0: cs-irq head=3, tail=4
> >>>>> <0> [574.303565] <idle>-0 7..s1 481827379us : process_csb: 0000:00:02.0 rcs0: csb[4]: status=0x10000001:0x00000000
> >>>>> <0> [574.305593] <idle>-0 7..s1 481827385us : trace_ports: 0000:00:02.0 rcs0: promote { f51b:2*, 0:0 }
> >>>>> <0> [574.305611] <idle>-0 7..s1 481828179us : execlists_reset: 0000:00:02.0 rcs0: reset for CS error
> >>>>> <0> [574.305611] i915_sel-6278 2.... 481828284us : __intel_context_do_pin: 0000:00:02.0 rcs0: context:f51c pin ring:{start:00007000, head:0000, tail:0000}
> >>>>> <0> [574.305611] i915_sel-6278 2.... 481828345us : __i915_request_commit: 0000:00:02.0 rcs0: fence f51c:2, current 0
> >>>>> <0> [574.305611] <idle>-0 7dNs2 481847823us : __i915_request_unsubmit: 0000:00:02.0 rcs0: fence f51b:2, current 1
> >>>>> <0> [574.305611] <idle>-0 7dNs2 481847857us : execlists_hold: 0000:00:02.0 rcs0: fence f51b:2, current 1 on hold
> >>>>> <0> [574.305611] <idle>-0 7.Ns1 481847863us : intel_engine_reset: 0000:00:02.0 rcs0: flags=4
> >>>>> <0> [574.305611] <idle>-0 7.Ns1 481847945us : execlists_reset_prepare: 0000:00:02.0 rcs0: depth<-1
> >>>>> <0> [574.305611] <idle>-0 7.Ns1 481847946us : intel_engine_stop_cs: 0000:00:02.0 rcs0:
> >>>>> <0> [574.305611] <idle>-0 7.Ns1 538584284us : intel_engine_stop_cs: 0000:00:02.0 rcs0: timed out on STOP_RING -> IDLE
> >>>>> <0> [574.305611] <idle>-0 7.Ns1 538584347us : __intel_gt_reset: 0000:00:02.0 engine_mask=1
> >>>>> <0> [574.305611] <idle>-0 7.Ns1 538584406us : execlists_reset_rewind: 0000:00:02.0 rcs0:
> >>>>> <0> [574.305611] <idle>-0 7dNs2 538585050us : __i915_request_reset: 0000:00:02.0 rcs0: fence f51b:2, current 1 guilty? yes
> >>>>> <0> [574.305611] <idle>-0 7dNs2 538585063us : __execlists_reset: 0000:00:02.0 rcs0: replay {head:0000, tail:0068}
> >>>>> <0> [574.306565] <idle>-0 7.Ns1 538588457us : intel_engine_cancel_stop_cs: 0000:00:02.0 rcs0:
> >>>>> <0> [574.306565] <idle>-0 7dNs2 538588462us : __i915_request_submit: 0000:00:02.0 rcs0: fence f51c:2, current 0
> >>>>> <0> [574.306565] <idle>-0 7dNs2 538588471us : trace_ports: 0000:00:02.0 rcs0: submit { f51c:2, 0:0 }
> >>>>> <0> [574.306565] <idle>-0 7.Ns1 538588474us : execlists_reset_finish: 0000:00:02.0 rcs0: depth->1
> >>>>> <0> [574.306565] kworker/-202 2.... 538588755us : i915_request_retire: 0000:00:02.0 rcs0: fence f51c:2, current 2
> >>>>> <0> [574.306565] ksoftirq-46 7..s. 538588773us : process_csb: 0000:00:02.0 rcs0: cs-irq head=11, tail=1
> >>>>> <0> [574.306565] ksoftirq-46 7..s. 538588774us : process_csb: 0000:00:02.0 rcs0: csb[0]: status=0x10000001:0x00000000
> >>>>> <0> [574.306565] ksoftirq-46 7..s. 538588776us : trace_ports: 0000:00:02.0 rcs0: promote { f51c:2!, 0:0 }
> >>>>> <0> [574.306565] ksoftirq-46 7..s. 538588778us : process_csb: 0000:00:02.0 rcs0: csb[1]: status=0x10000018:0x00000020
> >>>>> <0> [574.306565] ksoftirq-46 7..s. 538588779us : trace_ports: 0000:00:02.0 rcs0: completed { f51c:2!, 0:0 }
> >>>>> <0> [574.306565] kworker/-202 2.... 538588826us : intel_context_unpin: 0000:00:02.0 rcs0: context:f51c unpin
> >>>>> <0> [574.306565] i915_sel-6278 6.... 538589663us : __intel_gt_set_wedged.part.32: 0000:00:02.0 start
> >>>>> <0> [574.306565] i915_sel-6278 6.... 538589667us : execlists_reset_prepare: 0000:00:02.0 rcs0: depth<-0
> >>>>> <0> [574.306565] i915_sel-6278 6.... 538589710us : intel_engine_stop_cs: 0000:00:02.0 rcs0:
> >>>>> <0> [574.306565] i915_sel-6278 6.... 538589732us : execlists_reset_prepare: 0000:00:02.0 bcs0: depth<-0
> >>>>> <0> [574.307591] i915_sel-6278 6.... 538589733us : intel_engine_stop_cs: 0000:00:02.0 bcs0:
> >>>>> <0> [574.307591] i915_sel-6278 6.... 538589757us : execlists_reset_prepare: 0000:00:02.0 vcs0: depth<-0
> >>>>> <0> [574.307591] i915_sel-6278 6.... 538589758us : intel_engine_stop_cs: 0000:00:02.0 vcs0:
> >>>>> <0> [574.307591] i915_sel-6278 6.... 538589771us : execlists_reset_prepare: 0000:00:02.0 vcs1: depth<-0
> >>>>> <0> [574.307591] i915_sel-6278 6.... 538589772us : intel_engine_stop_cs: 0000:00:02.0 vcs1:
> >>>>> <0> [574.307591] i915_sel-6278 6.... 538589778us : execlists_reset_prepare: 0000:00:02.0 vecs0: depth<-0
> >>>>> <0> [574.307591] i915_sel-6278 6.... 538589780us : intel_engine_stop_cs: 0000:00:02.0 vecs0:
> >>>>> <0> [574.307591] i915_sel-6278 6.... 538589786us : __intel_gt_reset: 0000:00:02.0 engine_mask=ff
> >>>>> <0> [574.307591] i915_sel-6278 6.... 538591175us : execlists_reset_cancel: 0000:00:02.0 rcs0:
> >>>>> <0> [574.307591] i915_sel-6278 6.... 538591970us : execlists_reset_cancel: 0000:00:02.0 bcs0:
> >>>>> <0> [574.307591] i915_sel-6278 6.... 538591982us : execlists_reset_cancel: 0000:00:02.0 vcs0:
> >>>>> <0> [574.307591] i915_sel-6278 6.... 538591996us : execlists_reset_cancel: 0000:00:02.0 vcs1:
> >>>>> <0> [574.307591] i915_sel-6278 6.... 538592759us : execlists_reset_cancel: 0000:00:02.0 vecs0:
> >>>>> <0> [574.307591] i915_sel-6278 6.... 538592977us : execlists_reset_finish: 0000:00:02.0 rcs0: depth->0
> >>>>> <0> [574.307591] i915_sel-6278 6.N.. 538592996us : execlists_reset_finish: 0000:00:02.0 bcs0: depth->0
> >>>>> <0> [574.307591] i915_sel-6278 6.N.. 538593023us : execlists_reset_finish: 0000:00:02.0 vcs0: depth->0
> >>>>> <0> [574.307591] i915_sel-6278 6.N.. 538593037us : execlists_reset_finish: 0000:00:02.0 vcs1: depth->0
> >>>>> <0> [574.307591] i915_sel-6278 6.N.. 538593051us : execlists_reset_finish: 0000:00:02.0 vecs0: depth->0
> >>>>> <0> [574.307591] i915_sel-6278 6.... 538593407us : __intel_gt_set_wedged.part.32: 0000:00:02.0 end
> >>>>> <0> [574.307591] kworker/-210 7d..1 551958381us : execlists_unhold: 0000:00:02.0 rcs0: fence f51b:2, current 2 hold release
> >>>>> <0> [574.307591] i915_sel-6278 0.... 559490788us : i915_request_retire: 0000:00:02.0 rcs0: fence f51b:2, current 2
> >>>>> <0> [574.307591] i915_sel-6278 0.... 559490793us : intel_context_unpin: 0000:00:02.0 rcs0: context:f51b unpin
> >>>>> <0> [574.307591] i915_sel-6278 0.... 559490798us : __engine_park: 0000:00:02.0 rcs0: parked
> >>>>> <0> [574.307591] i915_sel-6278 0.... 559490982us : __intel_context_retire: 0000:00:02.0 rcs0: context:f51c retire runtime: { total:30004ns, avg:30004ns }
> >>>>> <0> [574.307591] i915_sel-6278 0.... 559491372us : __engine_park: __engine_park:261 GEM_BUG_ON(engine->execlists.queue_priority_hint != (-((int)(~0U >> 1)) - 1))
> >>>>>
> >>>>> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> >>>>> ---
> >>>>> drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +++
> >>>>> 1 file changed, 3 insertions(+)
> >>>>>
> >>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> >>>>> index 39b0125b7143..35c5cf786726 100644
> >>>>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> >>>>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> >>>>> @@ -3724,7 +3724,10 @@ static void execlists_reset_rewind(struct intel_engine_cs *engine, bool stalled)
> >>>>>
> >>>>> static void nop_submission_tasklet(unsigned long data)
> >>>>> {
> >>>>> + struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
> >>>>> +
> >>>>> /* The driver is wedged; don't process any more events. */
> >>>>> + WRITE_ONCE(engine->execlists.queue_priority_hint, INT_MIN);
> >>>>
> >>>> Why from the tasklet and not the place which clears the queue?
> >>>
> >>> That would be the list_move within nop_submit_request()
> >>> [i915_request_submit]
> >>>
> >>> I chose this tasklet as we do the reset in execlists_submission_tasklet()
> >>> on clearing the queue there, and so thought this was analogous.
> >>
> >> It actually looks to me it is unhold which is causing this, so it is not
> >> true we never reset the hint, it was probably overwritten:
> >>
> >> execlists_reset_cancel, at the end of it:
> >>
> >> /* Remaining _unready_ requests will be nop'ed when submitted */
> >>
> >> execlists->queue_priority_hint = INT_MIN;
> >>
> >> Just who overwrote it.. someone called unhold after
> >> execlists_reset_cancel finished.
> >>
> >> Should unhold not restore the priority hint if the requests on the hold
> >> list are -EIO?
> >
> > It is the unhold callback, it does
> >
> > if (rq_prio(rq) > engine->execlists.queue_priority_hint) {
> > engine->execlists.queue_priority_hint = rq_prio(rq);
> > tasklet_hi_schedule(&engine->execlists.tasklet);
> > }
> >
> > and queues the [now] nop_submission_tasklet. Which would be fine if it
> > behaved similarly.
>
> That I found, but who calls it?
Currently, a reset worker. Intention is that any path that first called
execlists_hold(). (E.g. holding requests across suspend is one
possible idea I have. No concrete second use case yet, just more of a
feeling this might be useful again.)
> I was thinking that since execlists_reset_cancel bothers to mark held
> requests with -EIO then unhold could be smarter and not consider them
> when setting the priority hint.
Could do, trying to keep it simple :) My preference is to push the
complexity to the edge case of wedge handling; and I'm not keen on
having to worry about -EIO here. The intent is remove from queue, place
in holding area, put back onto queue. Trying to do that correctly is
hard enough [apparently] :)
> That way the hint is immediately true, not only after tasklet is
> flushed. But okay, no big deal either way.
On the other hand, if the assertion is more troublesome than it's worth,
we just set the hint = INT_MIN on resume.
-Chris
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^ permalink raw reply [flat|nested] 51+ messages in thread
* [Intel-gfx] [PATCH 10/20] drm/i915/gt: Pull marking vm as closed underneath the vm->mutex
2020-02-27 8:57 [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits Chris Wilson
` (7 preceding siblings ...)
2020-02-27 8:57 ` [Intel-gfx] [PATCH 09/20] drm/i915/gt: Reset queue_priority_hint after wedging Chris Wilson
@ 2020-02-27 8:57 ` Chris Wilson
2020-02-28 12:12 ` Tvrtko Ursulin
2020-02-27 8:57 ` [Intel-gfx] [PATCH 11/20] drm/i915: Protect i915_request_await_start from early waits Chris Wilson
` (16 subsequent siblings)
25 siblings, 1 reply; 51+ messages in thread
From: Chris Wilson @ 2020-02-27 8:57 UTC (permalink / raw)
To: intel-gfx
Pull the final atomic_dec of vm->open (marking the vm as closed)
underneath the same vm->mutex as used to close it. This is required to
correctly serialise with attempting to reuse the vma as the vm is closed
by a second thread.
References: 00de702c6c6f ("drm/i915: Check that the vma hasn't been closed before we insert it")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_gtt.c | 5 ++++-
drivers/gpu/drm/i915/gt/intel_gtt.h | 3 +--
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index bb9a6e638175..dfb1be050cca 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -171,7 +171,9 @@ void __i915_vm_close(struct i915_address_space *vm)
{
struct i915_vma *vma, *vn;
- mutex_lock(&vm->mutex);
+ if (!atomic_dec_and_mutex_lock(&vm->open, &vm->mutex))
+ return;
+
list_for_each_entry_safe(vma, vn, &vm->bound_list, vm_link) {
struct drm_i915_gem_object *obj = vma->obj;
@@ -186,6 +188,7 @@ void __i915_vm_close(struct i915_address_space *vm)
i915_gem_object_put(obj);
}
GEM_BUG_ON(!list_empty(&vm->bound_list));
+
mutex_unlock(&vm->mutex);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 23004445806a..eac38c682ef4 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -429,8 +429,7 @@ static inline void
i915_vm_close(struct i915_address_space *vm)
{
GEM_BUG_ON(!atomic_read(&vm->open));
- if (atomic_dec_and_test(&vm->open))
- __i915_vm_close(vm);
+ __i915_vm_close(vm);
i915_vm_put(vm);
}
--
2.25.1
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^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH 10/20] drm/i915/gt: Pull marking vm as closed underneath the vm->mutex
2020-02-27 8:57 ` [Intel-gfx] [PATCH 10/20] drm/i915/gt: Pull marking vm as closed underneath the vm->mutex Chris Wilson
@ 2020-02-28 12:12 ` Tvrtko Ursulin
0 siblings, 0 replies; 51+ messages in thread
From: Tvrtko Ursulin @ 2020-02-28 12:12 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 27/02/2020 08:57, Chris Wilson wrote:
> Pull the final atomic_dec of vm->open (marking the vm as closed)
> underneath the same vm->mutex as used to close it. This is required to
> correctly serialise with attempting to reuse the vma as the vm is closed
> by a second thread.
>
> References: 00de702c6c6f ("drm/i915: Check that the vma hasn't been closed before we insert it")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/gt/intel_gtt.c | 5 ++++-
> drivers/gpu/drm/i915/gt/intel_gtt.h | 3 +--
> 2 files changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
> index bb9a6e638175..dfb1be050cca 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> @@ -171,7 +171,9 @@ void __i915_vm_close(struct i915_address_space *vm)
> {
> struct i915_vma *vma, *vn;
>
> - mutex_lock(&vm->mutex);
> + if (!atomic_dec_and_mutex_lock(&vm->open, &vm->mutex))
> + return;
> +
> list_for_each_entry_safe(vma, vn, &vm->bound_list, vm_link) {
> struct drm_i915_gem_object *obj = vma->obj;
>
> @@ -186,6 +188,7 @@ void __i915_vm_close(struct i915_address_space *vm)
> i915_gem_object_put(obj);
> }
> GEM_BUG_ON(!list_empty(&vm->bound_list));
> +
> mutex_unlock(&vm->mutex);
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
> index 23004445806a..eac38c682ef4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
> @@ -429,8 +429,7 @@ static inline void
> i915_vm_close(struct i915_address_space *vm)
> {
> GEM_BUG_ON(!atomic_read(&vm->open));
> - if (atomic_dec_and_test(&vm->open))
> - __i915_vm_close(vm);
> + __i915_vm_close(vm);
>
> i915_vm_put(vm);
> }
>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
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^ permalink raw reply [flat|nested] 51+ messages in thread
* [Intel-gfx] [PATCH 11/20] drm/i915: Protect i915_request_await_start from early waits
2020-02-27 8:57 [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits Chris Wilson
` (8 preceding siblings ...)
2020-02-27 8:57 ` [Intel-gfx] [PATCH 10/20] drm/i915/gt: Pull marking vm as closed underneath the vm->mutex Chris Wilson
@ 2020-02-27 8:57 ` Chris Wilson
2020-02-28 12:41 ` Tvrtko Ursulin
2020-02-27 8:57 ` [Intel-gfx] [PATCH 12/20] drm/i915/selftests: Verify LRC isolation Chris Wilson
` (15 subsequent siblings)
25 siblings, 1 reply; 51+ messages in thread
From: Chris Wilson @ 2020-02-27 8:57 UTC (permalink / raw)
To: intel-gfx
We need to be extremely careful inside i915_request_await_start() as it
needs to walk the list of requests in the foreign timeline with very
little protection. As we hold our own timeline mutex, we can not nest
inside the signaler's timeline mutex, so all that remains is our RCU
protection. However, to be safe we need to tell the compiler that we may
be traversing the list only under RCU protection, and furthermore we
need to start declaring requests as elements of the timeline from their
construction.
Fixes: 9ddc8ec027a3 ("drm/i915: Eliminate the trylock for awaiting an earlier request")
Fixes: 6a79d848403d ("drm/i915: Lock signaler timeline while navigating")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_request.c | 41 ++++++++++++++++++++---------
1 file changed, 28 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index d53af93b919b..e5a55801f753 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -290,7 +290,7 @@ bool i915_request_retire(struct i915_request *rq)
spin_unlock_irq(&rq->lock);
remove_from_client(rq);
- list_del(&rq->link);
+ list_del_rcu(&rq->link);
intel_context_exit(rq->context);
intel_context_unpin(rq->context);
@@ -736,6 +736,8 @@ __i915_request_create(struct intel_context *ce, gfp_t gfp)
rq->infix = rq->ring->emit; /* end of header; start of user payload */
intel_context_mark_active(ce);
+ list_add_tail_rcu(&rq->link, &tl->requests);
+
return rq;
err_unwind:
@@ -792,13 +794,23 @@ i915_request_await_start(struct i915_request *rq, struct i915_request *signal)
GEM_BUG_ON(i915_request_timeline(rq) ==
rcu_access_pointer(signal->timeline));
+ if (i915_request_started(signal))
+ return 0;
+
fence = NULL;
rcu_read_lock();
spin_lock_irq(&signal->lock);
- if (!i915_request_started(signal) &&
- !list_is_first(&signal->link,
- &rcu_dereference(signal->timeline)->requests)) {
- struct i915_request *prev = list_prev_entry(signal, link);
+ do {
+ struct list_head *pos = READ_ONCE(signal->link.prev);
+ struct i915_request *prev;
+
+ /* Confirm signal has not been retired, the link is valid */
+ if (unlikely(i915_request_started(signal)))
+ break;
+
+ /* Is signal the earliest request on its timeline? */
+ if (pos == &rcu_dereference(signal->timeline)->requests)
+ break;
/*
* Peek at the request before us in the timeline. That
@@ -806,13 +818,18 @@ i915_request_await_start(struct i915_request *rq, struct i915_request *signal)
* after acquiring a reference to it, confirm that it is
* still part of the signaler's timeline.
*/
- if (i915_request_get_rcu(prev)) {
- if (list_next_entry(prev, link) == signal)
- fence = &prev->fence;
- else
- i915_request_put(prev);
+ prev = list_entry(pos, typeof(*prev), link);
+ if (!i915_request_get_rcu(prev))
+ break;
+
+ /* After the strong barrier, confirm prev is still attached */
+ if (unlikely(READ_ONCE(prev->link.next) != &signal->link)) {
+ i915_request_put(prev);
+ break;
}
- }
+
+ fence = &prev->fence;
+ } while (0);
spin_unlock_irq(&signal->lock);
rcu_read_unlock();
if (!fence)
@@ -1253,8 +1270,6 @@ __i915_request_add_to_timeline(struct i915_request *rq)
0);
}
- list_add_tail(&rq->link, &timeline->requests);
-
/*
* Make sure that no request gazumped us - if it was allocated after
* our i915_request_alloc() and called __i915_request_add() before
--
2.25.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH 11/20] drm/i915: Protect i915_request_await_start from early waits
2020-02-27 8:57 ` [Intel-gfx] [PATCH 11/20] drm/i915: Protect i915_request_await_start from early waits Chris Wilson
@ 2020-02-28 12:41 ` Tvrtko Ursulin
0 siblings, 0 replies; 51+ messages in thread
From: Tvrtko Ursulin @ 2020-02-28 12:41 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 27/02/2020 08:57, Chris Wilson wrote:
> We need to be extremely careful inside i915_request_await_start() as it
> needs to walk the list of requests in the foreign timeline with very
> little protection. As we hold our own timeline mutex, we can not nest
> inside the signaler's timeline mutex, so all that remains is our RCU
> protection. However, to be safe we need to tell the compiler that we may
> be traversing the list only under RCU protection, and furthermore we
> need to start declaring requests as elements of the timeline from their
> construction.
>
> Fixes: 9ddc8ec027a3 ("drm/i915: Eliminate the trylock for awaiting an earlier request")
> Fixes: 6a79d848403d ("drm/i915: Lock signaler timeline while navigating")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_request.c | 41 ++++++++++++++++++++---------
> 1 file changed, 28 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
> index d53af93b919b..e5a55801f753 100644
> --- a/drivers/gpu/drm/i915/i915_request.c
> +++ b/drivers/gpu/drm/i915/i915_request.c
> @@ -290,7 +290,7 @@ bool i915_request_retire(struct i915_request *rq)
> spin_unlock_irq(&rq->lock);
>
> remove_from_client(rq);
> - list_del(&rq->link);
> + list_del_rcu(&rq->link);
>
> intel_context_exit(rq->context);
> intel_context_unpin(rq->context);
> @@ -736,6 +736,8 @@ __i915_request_create(struct intel_context *ce, gfp_t gfp)
> rq->infix = rq->ring->emit; /* end of header; start of user payload */
>
> intel_context_mark_active(ce);
> + list_add_tail_rcu(&rq->link, &tl->requests);
> +
> return rq;
>
> err_unwind:
> @@ -792,13 +794,23 @@ i915_request_await_start(struct i915_request *rq, struct i915_request *signal)
> GEM_BUG_ON(i915_request_timeline(rq) ==
> rcu_access_pointer(signal->timeline));
>
> + if (i915_request_started(signal))
> + return 0;
> +
> fence = NULL;
> rcu_read_lock();
> spin_lock_irq(&signal->lock);
> - if (!i915_request_started(signal) &&
> - !list_is_first(&signal->link,
> - &rcu_dereference(signal->timeline)->requests)) {
> - struct i915_request *prev = list_prev_entry(signal, link);
> + do {
> + struct list_head *pos = READ_ONCE(signal->link.prev);
> + struct i915_request *prev;
> +
> + /* Confirm signal has not been retired, the link is valid */
> + if (unlikely(i915_request_started(signal)))
> + break;
> +
> + /* Is signal the earliest request on its timeline? */
> + if (pos == &rcu_dereference(signal->timeline)->requests)
> + break;
>
> /*
> * Peek at the request before us in the timeline. That
> @@ -806,13 +818,18 @@ i915_request_await_start(struct i915_request *rq, struct i915_request *signal)
> * after acquiring a reference to it, confirm that it is
> * still part of the signaler's timeline.
> */
> - if (i915_request_get_rcu(prev)) {
> - if (list_next_entry(prev, link) == signal)
> - fence = &prev->fence;
> - else
> - i915_request_put(prev);
> + prev = list_entry(pos, typeof(*prev), link);
> + if (!i915_request_get_rcu(prev))
> + break;
> +
> + /* After the strong barrier, confirm prev is still attached */
> + if (unlikely(READ_ONCE(prev->link.next) != &signal->link)) {
> + i915_request_put(prev);
> + break;
> }
> - }
> +
> + fence = &prev->fence;
> + } while (0);
> spin_unlock_irq(&signal->lock);
> rcu_read_unlock();
> if (!fence)
> @@ -1253,8 +1270,6 @@ __i915_request_add_to_timeline(struct i915_request *rq)
> 0);
> }
>
> - list_add_tail(&rq->link, &timeline->requests);
> -
> /*
> * Make sure that no request gazumped us - if it was allocated after
> * our i915_request_alloc() and called __i915_request_add() before
>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 51+ messages in thread
* [Intel-gfx] [PATCH 12/20] drm/i915/selftests: Verify LRC isolation
2020-02-27 8:57 [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits Chris Wilson
` (9 preceding siblings ...)
2020-02-27 8:57 ` [Intel-gfx] [PATCH 11/20] drm/i915: Protect i915_request_await_start from early waits Chris Wilson
@ 2020-02-27 8:57 ` Chris Wilson
2020-02-28 11:30 ` Mika Kuoppala
2020-02-27 8:57 ` [Intel-gfx] [PATCH 13/20] drm/i915/selftests: Check recovery from corrupted LRC Chris Wilson
` (14 subsequent siblings)
25 siblings, 1 reply; 51+ messages in thread
From: Chris Wilson @ 2020-02-27 8:57 UTC (permalink / raw)
To: intel-gfx
Record the LRC registers before/after a preemption event to ensure that
the first context sees nothing from the second client; at least in the
normal per-context register state.
References: https://gitlab.freedesktop.org/drm/intel/issues/1233
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 545 +++++++++++++++++++++++++
1 file changed, 545 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index febd608c23a7..810f7857ad26 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -4748,6 +4748,550 @@ static int live_lrc_timestamp(void *arg)
return 0;
}
+static struct i915_vma *
+create_user_vma(struct i915_address_space *vm, unsigned long size)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ int err;
+
+ obj = i915_gem_object_create_internal(vm->i915, size);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ vma = i915_vma_instance(obj, vm, NULL);
+ if (IS_ERR(vma)) {
+ i915_gem_object_put(obj);
+ return vma;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err) {
+ i915_gem_object_put(obj);
+ return ERR_PTR(err);
+ }
+
+ return vma;
+}
+
+static struct i915_vma *
+store_context(struct intel_context *ce, struct i915_vma *scratch)
+{
+ struct i915_vma *batch;
+ u32 dw, x, *cs, *hw;
+
+ batch = create_user_vma(ce->vm, SZ_64K);
+ if (IS_ERR(batch))
+ return ERR_CAST(batch);
+
+ cs = i915_gem_object_pin_map(batch->obj, I915_MAP_WC);
+ if (IS_ERR(cs)) {
+ i915_vma_put(batch);
+ return ERR_CAST(cs);
+ }
+
+ x = 0;
+ dw = 0;
+ hw = ce->engine->pinned_default_state;
+ hw += LRC_STATE_PN * PAGE_SIZE / sizeof(*hw);
+ do {
+ u32 lri = hw[dw];
+
+ if (lri == 0) {
+ dw++;
+ continue;
+ }
+
+ if ((lri & GENMASK(31, 23)) != MI_INSTR(0x22, 0)) {
+ lri &= 0x7f;
+ dw += lri + 2;
+ continue;
+ }
+
+ lri &= 0x7f;
+ lri++;
+ dw++;
+
+ while (lri) {
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8;
+ *cs++ = hw[dw];
+ *cs++ = lower_32_bits(scratch->node.start + x);
+ *cs++ = upper_32_bits(scratch->node.start + x);
+
+ dw += 2;
+ lri -= 2;
+ x += 4;
+ }
+ } while (dw < PAGE_SIZE / sizeof(u32) &&
+ (hw[dw] & ~BIT(0)) != MI_BATCH_BUFFER_END);
+
+ *cs++ = MI_BATCH_BUFFER_END;
+
+ i915_gem_object_flush_map(batch->obj);
+ i915_gem_object_unpin_map(batch->obj);
+
+ return batch;
+}
+
+static int move_to_active(struct i915_request *rq,
+ struct i915_vma *vma,
+ unsigned int flags)
+{
+ int err;
+
+ i915_vma_lock(vma);
+ err = i915_request_await_object(rq, vma->obj, flags);
+ if (!err)
+ err = i915_vma_move_to_active(vma, rq, flags);
+ i915_vma_unlock(vma);
+
+ return err;
+}
+
+static struct i915_request *
+record_registers(struct intel_context *ce,
+ struct i915_vma *before,
+ struct i915_vma *after,
+ u32 *sema)
+{
+ struct i915_vma *b_before, *b_after;
+ struct i915_request *rq;
+ u32 *cs;
+ int err;
+
+ b_before = store_context(ce, before);
+ if (IS_ERR(b_before))
+ return ERR_CAST(b_before);
+
+ b_after = store_context(ce, after);
+ if (IS_ERR(b_after)) {
+ rq = ERR_CAST(b_after);
+ goto err_before;
+ }
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq))
+ goto err_after;
+
+ err = move_to_active(rq, before, EXEC_OBJECT_WRITE);
+ if (err)
+ goto err_rq;
+
+ err = move_to_active(rq, b_before, 0);
+ if (err)
+ goto err_rq;
+
+ err = move_to_active(rq, after, EXEC_OBJECT_WRITE);
+ if (err)
+ goto err_rq;
+
+ err = move_to_active(rq, b_after, 0);
+ if (err)
+ goto err_rq;
+
+ cs = intel_ring_begin(rq, 14);
+ if (IS_ERR(cs)) {
+ err = PTR_ERR(cs);
+ goto err_rq;
+ }
+
+ *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
+ *cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
+ *cs++ = lower_32_bits(b_before->node.start);
+ *cs++ = upper_32_bits(b_before->node.start);
+
+ *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
+ *cs++ = MI_SEMAPHORE_WAIT |
+ MI_SEMAPHORE_GLOBAL_GTT |
+ MI_SEMAPHORE_POLL |
+ MI_SEMAPHORE_SAD_NEQ_SDD;
+ *cs++ = 0;
+ *cs++ = i915_ggtt_offset(ce->engine->status_page.vma) +
+ offset_in_page(sema);
+ *cs++ = 0;
+ *cs++ = MI_NOOP;
+
+ *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
+ *cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
+ *cs++ = lower_32_bits(b_after->node.start);
+ *cs++ = upper_32_bits(b_after->node.start);
+
+ intel_ring_advance(rq, cs);
+
+ WRITE_ONCE(*sema, 0);
+ i915_request_get(rq);
+ i915_request_add(rq);
+err_after:
+ i915_vma_put(b_after);
+err_before:
+ i915_vma_put(b_before);
+ return rq;
+
+err_rq:
+ i915_request_add(rq);
+ rq = ERR_PTR(err);
+ goto err_after;
+}
+
+static struct i915_vma *load_context(struct intel_context *ce, u32 poison)
+{
+ struct i915_vma *batch;
+ u32 dw, *cs, *hw;
+
+ batch = create_user_vma(ce->vm, SZ_64K);
+ if (IS_ERR(batch))
+ return ERR_CAST(batch);
+
+ cs = i915_gem_object_pin_map(batch->obj, I915_MAP_WC);
+ if (IS_ERR(cs)) {
+ i915_vma_put(batch);
+ return ERR_CAST(cs);
+ }
+
+ dw = 0;
+ hw = ce->engine->pinned_default_state;
+ hw += LRC_STATE_PN * PAGE_SIZE / sizeof(*hw);
+ do {
+ u32 lri = hw[dw];
+
+ if (lri == 0) {
+ dw++;
+ continue;
+ }
+
+ if ((lri & GENMASK(31, 23)) != MI_INSTR(0x22, 0)) {
+ lri &= 0x7f;
+ dw += lri + 2;
+ continue;
+ }
+
+ lri &= 0x7f;
+ lri++;
+ dw++;
+
+ lri /= 2;
+ *cs++ = MI_LOAD_REGISTER_IMM(lri);
+ while (lri--) {
+ *cs++ = hw[dw];
+ *cs++ = poison;
+ dw += 2;
+ }
+ } while (dw < PAGE_SIZE / sizeof(u32) &&
+ (hw[dw] & ~BIT(0)) != MI_BATCH_BUFFER_END);
+
+ *cs++ = MI_BATCH_BUFFER_END;
+
+ i915_gem_object_flush_map(batch->obj);
+ i915_gem_object_unpin_map(batch->obj);
+
+ return batch;
+}
+
+static int poison_registers(struct intel_context *ce, u32 poison, u32 *sema)
+{
+ struct i915_request *rq;
+ struct i915_vma *batch;
+ u32 *cs;
+ int err;
+
+ batch = load_context(ce, poison);
+ if (IS_ERR(batch))
+ return PTR_ERR(batch);
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_batch;
+ }
+
+ err = move_to_active(rq, batch, 0);
+ if (err)
+ goto err_rq;
+
+ cs = intel_ring_begin(rq, 8);
+ if (IS_ERR(cs)) {
+ err = PTR_ERR(cs);
+ goto err_rq;
+ }
+
+ *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
+ *cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
+ *cs++ = lower_32_bits(batch->node.start);
+ *cs++ = upper_32_bits(batch->node.start);
+
+ *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
+ *cs++ = i915_ggtt_offset(ce->engine->status_page.vma) +
+ offset_in_page(sema);
+ *cs++ = 0;
+ *cs++ = 1;
+
+ intel_ring_advance(rq, cs);
+
+ rq->sched.attr.priority = I915_PRIORITY_BARRIER;
+err_rq:
+ i915_request_add(rq);
+err_batch:
+ i915_vma_put(batch);
+ return err;
+}
+
+static bool is_moving(u32 a, u32 b)
+{
+ return a != b;
+}
+
+static int compare_isolation(struct intel_engine_cs *engine,
+ struct i915_vma *ref[2],
+ struct i915_vma *result[2],
+ struct intel_context *ce,
+ u32 poison)
+{
+ u32 x, dw, *hw, *lrc;
+ u32 *A[2], *B[2];
+ int err = 0;
+
+ A[0] = i915_gem_object_pin_map(ref[0]->obj, I915_MAP_WC);
+ if (IS_ERR(A[0]))
+ return PTR_ERR(A[0]);
+
+ A[1] = i915_gem_object_pin_map(ref[1]->obj, I915_MAP_WC);
+ if (IS_ERR(A[1])) {
+ err = PTR_ERR(A[1]);
+ goto err_A0;
+ }
+
+ B[0] = i915_gem_object_pin_map(result[0]->obj, I915_MAP_WC);
+ if (IS_ERR(B[0])) {
+ err = PTR_ERR(B[0]);
+ goto err_A1;
+ }
+
+ B[1] = i915_gem_object_pin_map(result[1]->obj, I915_MAP_WC);
+ if (IS_ERR(B[1])) {
+ err = PTR_ERR(B[1]);
+ goto err_B0;
+ }
+
+ lrc = i915_gem_object_pin_map(ce->state->obj,
+ i915_coherent_map_type(engine->i915));
+ if (IS_ERR(lrc)) {
+ err = PTR_ERR(lrc);
+ goto err_B1;
+ }
+ lrc += LRC_STATE_PN * PAGE_SIZE / sizeof(*hw);
+
+ x = 0;
+ dw = 0;
+ hw = engine->pinned_default_state;
+ hw += LRC_STATE_PN * PAGE_SIZE / sizeof(*hw);
+ do {
+ u32 lri = hw[dw];
+
+ if (lri == 0) {
+ dw++;
+ continue;
+ }
+
+ if ((lri & GENMASK(31, 23)) != MI_INSTR(0x22, 0)) {
+ lri &= 0x7f;
+ dw += lri + 2;
+ continue;
+ }
+
+ lri &= 0x7f;
+ lri++;
+ dw++;
+
+ while (lri) {
+ if (!is_moving(A[0][x], A[1][x]) &&
+ (A[0][x] != B[0][x] || A[1][x] != B[1][x])) {
+ switch (hw[dw] & 4095) {
+ case 0x30: /* RING_HEAD */
+ case 0x34: /* RING_TAIL */
+ break;
+
+ default:
+ pr_err("%s[%d]: Mismatch for register %4x, default %08x, reference %08x, result (%08x, %08x), poison %08x, context %08x\n",
+ engine->name, x,
+ hw[dw], hw[dw + 1],
+ A[0][x], B[0][x], B[1][x],
+ poison, lrc[dw + 1]);
+ err = -EINVAL;
+ break;
+ }
+ }
+ dw += 2;
+ lri -= 2;
+ x++;
+ }
+ } while (dw < PAGE_SIZE / sizeof(u32) &&
+ (hw[dw] & ~BIT(0)) != MI_BATCH_BUFFER_END);
+
+ i915_gem_object_unpin_map(ce->state->obj);
+err_B1:
+ i915_gem_object_unpin_map(result[1]->obj);
+err_B0:
+ i915_gem_object_unpin_map(result[0]->obj);
+err_A1:
+ i915_gem_object_unpin_map(ref[1]->obj);
+err_A0:
+ i915_gem_object_unpin_map(ref[0]->obj);
+ return err;
+}
+
+static int __lrc_isolation(struct intel_engine_cs *engine, u32 poison)
+{
+ u32 *sema = memset32(engine->status_page.addr + 1000, 0, 1);
+ struct i915_vma *ref[2], *result[2];
+ struct intel_context *A, *B;
+ struct i915_request *rq;
+ int err;
+
+ A = intel_context_create(engine);
+ if (IS_ERR(A))
+ return PTR_ERR(A);
+
+ B = intel_context_create(engine);
+ if (IS_ERR(B)) {
+ err = PTR_ERR(B);
+ goto err_A;
+ }
+
+ ref[0] = create_user_vma(A->vm, SZ_64K);
+ if (IS_ERR(ref[0])) {
+ err = PTR_ERR(ref[0]);
+ goto err_B;
+ }
+
+ ref[1] = create_user_vma(A->vm, SZ_64K);
+ if (IS_ERR(ref[1])) {
+ err = PTR_ERR(ref[1]);
+ goto err_ref0;
+ }
+
+ rq = record_registers(A, ref[0], ref[1], sema);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_ref1;
+ }
+
+ WRITE_ONCE(*sema, 1);
+ wmb();
+
+ if (i915_request_wait(rq, 0, HZ / 2) < 0) {
+ i915_request_put(rq);
+ err = -ETIME;
+ goto err_ref1;
+ }
+ i915_request_put(rq);
+
+ result[0] = create_user_vma(A->vm, SZ_64K);
+ if (IS_ERR(result[0])) {
+ err = PTR_ERR(result[0]);
+ goto err_ref1;
+ }
+
+ result[1] = create_user_vma(A->vm, SZ_64K);
+ if (IS_ERR(result[1])) {
+ err = PTR_ERR(result[1]);
+ goto err_result0;
+ }
+
+ rq = record_registers(A, result[0], result[1], sema);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_result1;
+ }
+
+ err = poison_registers(B, poison, sema);
+ if (err) {
+ WRITE_ONCE(*sema, -1);
+ i915_request_put(rq);
+ goto err_result1;
+ }
+
+ if (i915_request_wait(rq, 0, HZ / 2) < 0) {
+ i915_request_put(rq);
+ err = -ETIME;
+ goto err_result1;
+ }
+ i915_request_put(rq);
+
+ err = compare_isolation(engine, ref, result, A, poison);
+
+err_result1:
+ i915_vma_put(result[1]);
+err_result0:
+ i915_vma_put(result[0]);
+err_ref1:
+ i915_vma_put(ref[1]);
+err_ref0:
+ i915_vma_put(ref[0]);
+err_B:
+ intel_context_put(B);
+err_A:
+ intel_context_put(A);
+ return err;
+}
+
+static bool skip_isolation(const struct intel_engine_cs *engine)
+{
+ if (engine->class == COPY_ENGINE_CLASS && INTEL_GEN(engine->i915) == 9)
+ return true;
+
+ if (engine->class == RENDER_CLASS && INTEL_GEN(engine->i915) == 11)
+ return true;
+
+ return false;
+}
+
+static int live_lrc_isolation(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ const u32 poison[] = {
+ STACK_MAGIC,
+ 0x3a3a3a3a,
+ 0xc5c5c5c5,
+ 0xffffffff,
+ };
+
+ /*
+ * Our goal is try and verify that per-context state cannot be
+ * tampered with by another non-privileged client.
+ *
+ * We take the list of context registers from the LRI in the default
+ * context image and attempt to modify that list from a remote context.
+ */
+
+ for_each_engine(engine, gt, id) {
+ int err = 0;
+ int i;
+
+ /* Just don't even ask */
+ if (!IS_ENABLED(CONFIG_DRM_I915_SELFTEST_BROKEN) &&
+ skip_isolation(engine))
+ continue;
+
+ intel_engine_pm_get(engine);
+ if (engine->pinned_default_state) {
+ for (i = 0; i < ARRAY_SIZE(poison); i++) {
+ err = __lrc_isolation(engine, poison[i]);
+ if (err)
+ break;
+ }
+ }
+ if (igt_flush_test(gt->i915))
+ err = -EIO;
+ intel_engine_pm_put(engine);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
static int __live_pphwsp_runtime(struct intel_engine_cs *engine)
{
struct intel_context *ce;
@@ -4845,6 +5389,7 @@ int intel_lrc_live_selftests(struct drm_i915_private *i915)
SUBTEST(live_lrc_fixed),
SUBTEST(live_lrc_state),
SUBTEST(live_lrc_gpr),
+ SUBTEST(live_lrc_isolation),
SUBTEST(live_lrc_timestamp),
SUBTEST(live_pphwsp_runtime),
};
--
2.25.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH 12/20] drm/i915/selftests: Verify LRC isolation
2020-02-27 8:57 ` [Intel-gfx] [PATCH 12/20] drm/i915/selftests: Verify LRC isolation Chris Wilson
@ 2020-02-28 11:30 ` Mika Kuoppala
2020-02-28 11:52 ` Chris Wilson
0 siblings, 1 reply; 51+ messages in thread
From: Mika Kuoppala @ 2020-02-28 11:30 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Record the LRC registers before/after a preemption event to ensure that
> the first context sees nothing from the second client; at least in the
> normal per-context register state.
>
> References: https://gitlab.freedesktop.org/drm/intel/issues/1233
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/gt/selftest_lrc.c | 545 +++++++++++++++++++++++++
> 1 file changed, 545 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> index febd608c23a7..810f7857ad26 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
> @@ -4748,6 +4748,550 @@ static int live_lrc_timestamp(void *arg)
> return 0;
> }
>
> +static struct i915_vma *
> +create_user_vma(struct i915_address_space *vm, unsigned long size)
> +{
> + struct drm_i915_gem_object *obj;
> + struct i915_vma *vma;
> + int err;
> +
> + obj = i915_gem_object_create_internal(vm->i915, size);
> + if (IS_ERR(obj))
> + return ERR_CAST(obj);
> +
> + vma = i915_vma_instance(obj, vm, NULL);
> + if (IS_ERR(vma)) {
> + i915_gem_object_put(obj);
> + return vma;
> + }
> +
> + err = i915_vma_pin(vma, 0, 0, PIN_USER);
> + if (err) {
> + i915_gem_object_put(obj);
> + return ERR_PTR(err);
> + }
> +
> + return vma;
> +}
> +
> +static struct i915_vma *
> +store_context(struct intel_context *ce, struct i915_vma *scratch)
> +{
> + struct i915_vma *batch;
> + u32 dw, x, *cs, *hw;
> +
> + batch = create_user_vma(ce->vm, SZ_64K);
> + if (IS_ERR(batch))
> + return ERR_CAST(batch);
Superfluous cast but not harmful.
> +
> + cs = i915_gem_object_pin_map(batch->obj, I915_MAP_WC);
> + if (IS_ERR(cs)) {
> + i915_vma_put(batch);
> + return ERR_CAST(cs);
> + }
> +
> + x = 0;
> + dw = 0;
> + hw = ce->engine->pinned_default_state;
> + hw += LRC_STATE_PN * PAGE_SIZE / sizeof(*hw);
> + do {
> + u32 lri = hw[dw];
As you filter the everything other than lri out
early and then basically just operate on len,
it might be useful to do u32 len = hw[dw] & 0x7f;
and use hw[dw] on genmask check.
> +
> + if (lri == 0) {
> + dw++;
> + continue;
> + }
> +
> + if ((lri & GENMASK(31, 23)) != MI_INSTR(0x22, 0)) {
> + lri &= 0x7f;
> + dw += lri + 2;
> + continue;
> + }
> +
> + lri &= 0x7f;
> + lri++;
> + dw++;
> +
> + while (lri) {
> + *cs++ = MI_STORE_REGISTER_MEM_GEN8;
> + *cs++ = hw[dw];
> + *cs++ = lower_32_bits(scratch->node.start + x);
> + *cs++ = upper_32_bits(scratch->node.start + x);
> +
> + dw += 2;
> + lri -= 2;
> + x += 4;
> + }
> + } while (dw < PAGE_SIZE / sizeof(u32) &&
> + (hw[dw] & ~BIT(0)) != MI_BATCH_BUFFER_END);
> +
> + *cs++ = MI_BATCH_BUFFER_END;
> +
> + i915_gem_object_flush_map(batch->obj);
> + i915_gem_object_unpin_map(batch->obj);
> +
> + return batch;
> +}
> +
> +static int move_to_active(struct i915_request *rq,
> + struct i915_vma *vma,
> + unsigned int flags)
> +{
> + int err;
> +
> + i915_vma_lock(vma);
> + err = i915_request_await_object(rq, vma->obj, flags);
> + if (!err)
> + err = i915_vma_move_to_active(vma, rq, flags);
> + i915_vma_unlock(vma);
> +
> + return err;
> +}
> +
> +static struct i915_request *
> +record_registers(struct intel_context *ce,
> + struct i915_vma *before,
> + struct i915_vma *after,
> + u32 *sema)
> +{
> + struct i915_vma *b_before, *b_after;
> + struct i915_request *rq;
> + u32 *cs;
> + int err;
> +
> + b_before = store_context(ce, before);
> + if (IS_ERR(b_before))
> + return ERR_CAST(b_before);
> +
> + b_after = store_context(ce, after);
> + if (IS_ERR(b_after)) {
> + rq = ERR_CAST(b_after);
> + goto err_before;
> + }
> +
> + rq = intel_context_create_request(ce);
> + if (IS_ERR(rq))
> + goto err_after;
> +
> + err = move_to_active(rq, before, EXEC_OBJECT_WRITE);
> + if (err)
> + goto err_rq;
> +
> + err = move_to_active(rq, b_before, 0);
> + if (err)
> + goto err_rq;
> +
> + err = move_to_active(rq, after, EXEC_OBJECT_WRITE);
> + if (err)
> + goto err_rq;
> +
> + err = move_to_active(rq, b_after, 0);
> + if (err)
> + goto err_rq;
> +
> + cs = intel_ring_begin(rq, 14);
> + if (IS_ERR(cs)) {
> + err = PTR_ERR(cs);
> + goto err_rq;
> + }
> +
> + *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
> + *cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
> + *cs++ = lower_32_bits(b_before->node.start);
> + *cs++ = upper_32_bits(b_before->node.start);
> +
> + *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
> + *cs++ = MI_SEMAPHORE_WAIT |
> + MI_SEMAPHORE_GLOBAL_GTT |
> + MI_SEMAPHORE_POLL |
> + MI_SEMAPHORE_SAD_NEQ_SDD;
> + *cs++ = 0;
> + *cs++ = i915_ggtt_offset(ce->engine->status_page.vma) +
> + offset_in_page(sema);
> + *cs++ = 0;
> + *cs++ = MI_NOOP;
> +
> + *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
> + *cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
> + *cs++ = lower_32_bits(b_after->node.start);
> + *cs++ = upper_32_bits(b_after->node.start);
> +
> + intel_ring_advance(rq, cs);
> +
> + WRITE_ONCE(*sema, 0);
> + i915_request_get(rq);
> + i915_request_add(rq);
> +err_after:
> + i915_vma_put(b_after);
> +err_before:
> + i915_vma_put(b_before);
> + return rq;
> +
> +err_rq:
> + i915_request_add(rq);
> + rq = ERR_PTR(err);
> + goto err_after;
> +}
> +
> +static struct i915_vma *load_context(struct intel_context *ce, u32 poison)
> +{
> + struct i915_vma *batch;
> + u32 dw, *cs, *hw;
> +
> + batch = create_user_vma(ce->vm, SZ_64K);
> + if (IS_ERR(batch))
> + return ERR_CAST(batch);
Superfluous cast.
> +
> + cs = i915_gem_object_pin_map(batch->obj, I915_MAP_WC);
> + if (IS_ERR(cs)) {
> + i915_vma_put(batch);
> + return ERR_CAST(cs);
> + }
> +
> + dw = 0;
> + hw = ce->engine->pinned_default_state;
> + hw += LRC_STATE_PN * PAGE_SIZE / sizeof(*hw);
> + do {
> + u32 lri = hw[dw];
Altho I suggested len, one starts to accustom to the lri.
Shrug.
> +
> + if (lri == 0) {
> + dw++;
> + continue;
> + }
> +
> + if ((lri & GENMASK(31, 23)) != MI_INSTR(0x22, 0)) {
> + lri &= 0x7f;
> + dw += lri + 2;
> + continue;
> + }
> +
> + lri &= 0x7f;
> + lri++;
> + dw++;
> +
> + lri /= 2;
> + *cs++ = MI_LOAD_REGISTER_IMM(lri);
> + while (lri--) {
> + *cs++ = hw[dw];
> + *cs++ = poison;
> + dw += 2;
> + }
> + } while (dw < PAGE_SIZE / sizeof(u32) &&
> + (hw[dw] & ~BIT(0)) != MI_BATCH_BUFFER_END);
> +
> + *cs++ = MI_BATCH_BUFFER_END;
> +
> + i915_gem_object_flush_map(batch->obj);
> + i915_gem_object_unpin_map(batch->obj);
> +
> + return batch;
> +}
> +
> +static int poison_registers(struct intel_context *ce, u32 poison, u32 *sema)
> +{
> + struct i915_request *rq;
> + struct i915_vma *batch;
> + u32 *cs;
> + int err;
> +
> + batch = load_context(ce, poison);
> + if (IS_ERR(batch))
> + return PTR_ERR(batch);
> +
> + rq = intel_context_create_request(ce);
> + if (IS_ERR(rq)) {
> + err = PTR_ERR(rq);
> + goto err_batch;
> + }
> +
> + err = move_to_active(rq, batch, 0);
> + if (err)
> + goto err_rq;
> +
> + cs = intel_ring_begin(rq, 8);
> + if (IS_ERR(cs)) {
> + err = PTR_ERR(cs);
> + goto err_rq;
> + }
> +
> + *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
> + *cs++ = MI_BATCH_BUFFER_START_GEN8 | BIT(8);
> + *cs++ = lower_32_bits(batch->node.start);
> + *cs++ = upper_32_bits(batch->node.start);
> +
> + *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> + *cs++ = i915_ggtt_offset(ce->engine->status_page.vma) +
> + offset_in_page(sema);
> + *cs++ = 0;
> + *cs++ = 1;
For a future glimpse reader defines like SEMA_WAIT, SEMA_GO might
ease some pain. But not insisting.
> +
> + intel_ring_advance(rq, cs);
> +
> + rq->sched.attr.priority = I915_PRIORITY_BARRIER;
> +err_rq:
> + i915_request_add(rq);
> +err_batch:
> + i915_vma_put(batch);
> + return err;
> +}
> +
> +static bool is_moving(u32 a, u32 b)
> +{
> + return a != b;
> +}
> +
> +static int compare_isolation(struct intel_engine_cs *engine,
> + struct i915_vma *ref[2],
> + struct i915_vma *result[2],
> + struct intel_context *ce,
> + u32 poison)
> +{
> + u32 x, dw, *hw, *lrc;
> + u32 *A[2], *B[2];
Using these names got me a bit off the balance
as I associated them with after and before.
> + int err = 0;
> +
> + A[0] = i915_gem_object_pin_map(ref[0]->obj, I915_MAP_WC);
> + if (IS_ERR(A[0]))
> + return PTR_ERR(A[0]);
> +
> + A[1] = i915_gem_object_pin_map(ref[1]->obj, I915_MAP_WC);
> + if (IS_ERR(A[1])) {
> + err = PTR_ERR(A[1]);
> + goto err_A0;
> + }
> +
> + B[0] = i915_gem_object_pin_map(result[0]->obj, I915_MAP_WC);
> + if (IS_ERR(B[0])) {
> + err = PTR_ERR(B[0]);
> + goto err_A1;
> + }
> +
> + B[1] = i915_gem_object_pin_map(result[1]->obj, I915_MAP_WC);
> + if (IS_ERR(B[1])) {
> + err = PTR_ERR(B[1]);
> + goto err_B0;
> + }
> +
> + lrc = i915_gem_object_pin_map(ce->state->obj,
> + i915_coherent_map_type(engine->i915));
> + if (IS_ERR(lrc)) {
> + err = PTR_ERR(lrc);
> + goto err_B1;
> + }
> + lrc += LRC_STATE_PN * PAGE_SIZE / sizeof(*hw);
> +
> + x = 0;
> + dw = 0;
> + hw = engine->pinned_default_state;
> + hw += LRC_STATE_PN * PAGE_SIZE / sizeof(*hw);
> + do {
> + u32 lri = hw[dw];
> +
> + if (lri == 0) {
> + dw++;
> + continue;
> + }
> +
> + if ((lri & GENMASK(31, 23)) != MI_INSTR(0x22, 0)) {
> + lri &= 0x7f;
> + dw += lri + 2;
> + continue;
> + }
> +
> + lri &= 0x7f;
> + lri++;
> + dw++;
The pattern for weeding out everything except lris starts
to stand out as a boilerplate.
> +
> + while (lri) {
> + if (!is_moving(A[0][x], A[1][x]) &&
> + (A[0][x] != B[0][x] || A[1][x] != B[1][x])) {
> + switch (hw[dw] & 4095) {
> + case 0x30: /* RING_HEAD */
> + case 0x34: /* RING_TAIL */
> + break;
> +
> + default:
> + pr_err("%s[%d]: Mismatch for register %4x, default %08x, reference %08x, result (%08x, %08x), poison %08x, context %08x\n",
0x left out on all for compactness or by accident?
> + engine->name, x,
> + hw[dw], hw[dw + 1],
> + A[0][x], B[0][x], B[1][x],
> + poison, lrc[dw + 1]);
> + err = -EINVAL;
> + break;
> + }
> + }
> + dw += 2;
> + lri -= 2;
> + x++;
> + }
> + } while (dw < PAGE_SIZE / sizeof(u32) &&
> + (hw[dw] & ~BIT(0)) != MI_BATCH_BUFFER_END);
> +
> + i915_gem_object_unpin_map(ce->state->obj);
> +err_B1:
> + i915_gem_object_unpin_map(result[1]->obj);
> +err_B0:
> + i915_gem_object_unpin_map(result[0]->obj);
> +err_A1:
> + i915_gem_object_unpin_map(ref[1]->obj);
> +err_A0:
> + i915_gem_object_unpin_map(ref[0]->obj);
> + return err;
> +}
> +
> +static int __lrc_isolation(struct intel_engine_cs *engine, u32 poison)
> +{
> + u32 *sema = memset32(engine->status_page.addr + 1000, 0, 1);
> + struct i915_vma *ref[2], *result[2];
> + struct intel_context *A, *B;
> + struct i915_request *rq;
> + int err;
> +
> + A = intel_context_create(engine);
> + if (IS_ERR(A))
> + return PTR_ERR(A);
> +
> + B = intel_context_create(engine);
> + if (IS_ERR(B)) {
> + err = PTR_ERR(B);
> + goto err_A;
> + }
> +
> + ref[0] = create_user_vma(A->vm, SZ_64K);
> + if (IS_ERR(ref[0])) {
> + err = PTR_ERR(ref[0]);
> + goto err_B;
> + }
> +
> + ref[1] = create_user_vma(A->vm, SZ_64K);
> + if (IS_ERR(ref[1])) {
> + err = PTR_ERR(ref[1]);
> + goto err_ref0;
> + }
> +
> + rq = record_registers(A, ref[0], ref[1], sema);
> + if (IS_ERR(rq)) {
> + err = PTR_ERR(rq);
> + goto err_ref1;
> + }
> +
> + WRITE_ONCE(*sema, 1);
> + wmb();
So with this you get reference base for before and after...
> +
> + if (i915_request_wait(rq, 0, HZ / 2) < 0) {
> + i915_request_put(rq);
> + err = -ETIME;
> + goto err_ref1;
> + }
> + i915_request_put(rq);
> +
> + result[0] = create_user_vma(A->vm, SZ_64K);
> + if (IS_ERR(result[0])) {
> + err = PTR_ERR(result[0]);
> + goto err_ref1;
> + }
> +
> + result[1] = create_user_vma(A->vm, SZ_64K);
> + if (IS_ERR(result[1])) {
> + err = PTR_ERR(result[1]);
> + goto err_result0;
> + }
> +
> + rq = record_registers(A, result[0], result[1], sema);
> + if (IS_ERR(rq)) {
> + err = PTR_ERR(rq);
> + goto err_result1;
> + }
> +
> + err = poison_registers(B, poison, sema);
..and apparently the poisoning releases the semaphore
triggering the preemption?
How can you make preempt happen deterministically with this?
Released semaphore generates interrupt and you have it ready
with maximum prio?
I am also puzzled why there is a need for two set of reference
values?
-Mika
> + if (err) {
> + WRITE_ONCE(*sema, -1);
> + i915_request_put(rq);
> + goto err_result1;
> + }
> +
> + if (i915_request_wait(rq, 0, HZ / 2) < 0) {
> + i915_request_put(rq);
> + err = -ETIME;
> + goto err_result1;
> + }
> + i915_request_put(rq);
> +
> + err = compare_isolation(engine, ref, result, A, poison);
> +
> +err_result1:
> + i915_vma_put(result[1]);
> +err_result0:
> + i915_vma_put(result[0]);
> +err_ref1:
> + i915_vma_put(ref[1]);
> +err_ref0:
> + i915_vma_put(ref[0]);
> +err_B:
> + intel_context_put(B);
> +err_A:
> + intel_context_put(A);
> + return err;
> +}
> +
> +static bool skip_isolation(const struct intel_engine_cs *engine)
> +{
> + if (engine->class == COPY_ENGINE_CLASS && INTEL_GEN(engine->i915) == 9)
> + return true;
> +
> + if (engine->class == RENDER_CLASS && INTEL_GEN(engine->i915) == 11)
> + return true;
> +
> + return false;
> +}
> +
> +static int live_lrc_isolation(void *arg)
> +{
> + struct intel_gt *gt = arg;
> + struct intel_engine_cs *engine;
> + enum intel_engine_id id;
> + const u32 poison[] = {
> + STACK_MAGIC,
> + 0x3a3a3a3a,
> + 0xc5c5c5c5,
> + 0xffffffff,
> + };
> +
> + /*
> + * Our goal is try and verify that per-context state cannot be
> + * tampered with by another non-privileged client.
> + *
> + * We take the list of context registers from the LRI in the default
> + * context image and attempt to modify that list from a remote context.
> + */
> +
> + for_each_engine(engine, gt, id) {
> + int err = 0;
> + int i;
> +
> + /* Just don't even ask */
> + if (!IS_ENABLED(CONFIG_DRM_I915_SELFTEST_BROKEN) &&
> + skip_isolation(engine))
> + continue;
> +
> + intel_engine_pm_get(engine);
> + if (engine->pinned_default_state) {
> + for (i = 0; i < ARRAY_SIZE(poison); i++) {
> + err = __lrc_isolation(engine, poison[i]);
> + if (err)
> + break;
> + }
> + }
> + if (igt_flush_test(gt->i915))
> + err = -EIO;
> + intel_engine_pm_put(engine);
> + if (err)
> + return err;
> + }
> +
> + return 0;
> +}
> +
> static int __live_pphwsp_runtime(struct intel_engine_cs *engine)
> {
> struct intel_context *ce;
> @@ -4845,6 +5389,7 @@ int intel_lrc_live_selftests(struct drm_i915_private *i915)
> SUBTEST(live_lrc_fixed),
> SUBTEST(live_lrc_state),
> SUBTEST(live_lrc_gpr),
> + SUBTEST(live_lrc_isolation),
> SUBTEST(live_lrc_timestamp),
> SUBTEST(live_pphwsp_runtime),
> };
> --
> 2.25.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH 12/20] drm/i915/selftests: Verify LRC isolation
2020-02-28 11:30 ` Mika Kuoppala
@ 2020-02-28 11:52 ` Chris Wilson
2020-02-28 12:13 ` Mika Kuoppala
0 siblings, 1 reply; 51+ messages in thread
From: Chris Wilson @ 2020-02-28 11:52 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2020-02-28 11:30:21)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
> > + x = 0;
> > + dw = 0;
> > + hw = engine->pinned_default_state;
> > + hw += LRC_STATE_PN * PAGE_SIZE / sizeof(*hw);
> > + do {
> > + u32 lri = hw[dw];
> > +
> > + if (lri == 0) {
> > + dw++;
> > + continue;
> > + }
> > +
> > + if ((lri & GENMASK(31, 23)) != MI_INSTR(0x22, 0)) {
> > + lri &= 0x7f;
> > + dw += lri + 2;
> > + continue;
> > + }
> > +
> > + lri &= 0x7f;
> > + lri++;
> > + dw++;
>
> The pattern for weeding out everything except lris starts
> to stand out as a boilerplate.
Ssh. Just do a visual replacement with for_each_register()
>
> > +
> > + while (lri) {
> > + if (!is_moving(A[0][x], A[1][x]) &&
> > + (A[0][x] != B[0][x] || A[1][x] != B[1][x])) {
> > + switch (hw[dw] & 4095) {
> > + case 0x30: /* RING_HEAD */
> > + case 0x34: /* RING_TAIL */
> > + break;
> > +
> > + default:
> > + pr_err("%s[%d]: Mismatch for register %4x, default %08x, reference %08x, result (%08x, %08x), poison %08x, context %08x\n",
>
> 0x left out on all for compactness or by accident?
I tend not to use 0x, unless it looks odd or we need machine parsing :)
Here the compactness helps with a very long line.
> > + engine->name, x,
> > + hw[dw], hw[dw + 1],
> > + A[0][x], B[0][x], B[1][x],
> > + poison, lrc[dw + 1]);
> > + err = -EINVAL;
> > + break;
> > + }
> > + }
> > + dw += 2;
> > + lri -= 2;
> > + x++;
> > + }
> > + } while (dw < PAGE_SIZE / sizeof(u32) &&
> > + (hw[dw] & ~BIT(0)) != MI_BATCH_BUFFER_END);
> > +
> > + i915_gem_object_unpin_map(ce->state->obj);
> > +err_B1:
> > + i915_gem_object_unpin_map(result[1]->obj);
> > +err_B0:
> > + i915_gem_object_unpin_map(result[0]->obj);
> > +err_A1:
> > + i915_gem_object_unpin_map(ref[1]->obj);
> > +err_A0:
> > + i915_gem_object_unpin_map(ref[0]->obj);
> > + return err;
> > +}
> > +
> > +static int __lrc_isolation(struct intel_engine_cs *engine, u32 poison)
> > +{
> > + u32 *sema = memset32(engine->status_page.addr + 1000, 0, 1);
> > + struct i915_vma *ref[2], *result[2];
> > + struct intel_context *A, *B;
> > + struct i915_request *rq;
> > + int err;
> > +
> > + A = intel_context_create(engine);
> > + if (IS_ERR(A))
> > + return PTR_ERR(A);
> > +
> > + B = intel_context_create(engine);
> > + if (IS_ERR(B)) {
> > + err = PTR_ERR(B);
> > + goto err_A;
> > + }
> > +
> > + ref[0] = create_user_vma(A->vm, SZ_64K);
> > + if (IS_ERR(ref[0])) {
> > + err = PTR_ERR(ref[0]);
> > + goto err_B;
> > + }
> > +
> > + ref[1] = create_user_vma(A->vm, SZ_64K);
> > + if (IS_ERR(ref[1])) {
> > + err = PTR_ERR(ref[1]);
> > + goto err_ref0;
> > + }
> > +
> > + rq = record_registers(A, ref[0], ref[1], sema);
> > + if (IS_ERR(rq)) {
> > + err = PTR_ERR(rq);
> > + goto err_ref1;
> > + }
> > +
> > + WRITE_ONCE(*sema, 1);
> > + wmb();
>
> So with this you get reference base for before and after...
>
> > +
> > + if (i915_request_wait(rq, 0, HZ / 2) < 0) {
> > + i915_request_put(rq);
> > + err = -ETIME;
> > + goto err_ref1;
> > + }
> > + i915_request_put(rq);
> > +
> > + result[0] = create_user_vma(A->vm, SZ_64K);
> > + if (IS_ERR(result[0])) {
> > + err = PTR_ERR(result[0]);
> > + goto err_ref1;
> > + }
> > +
> > + result[1] = create_user_vma(A->vm, SZ_64K);
> > + if (IS_ERR(result[1])) {
> > + err = PTR_ERR(result[1]);
> > + goto err_result0;
> > + }
> > +
> > + rq = record_registers(A, result[0], result[1], sema);
> > + if (IS_ERR(rq)) {
> > + err = PTR_ERR(rq);
> > + goto err_result1;
> > + }
> > +
> > + err = poison_registers(B, poison, sema);
>
> ..and apparently the poisoning releases the semaphore
> triggering the preemption?
Correct.
> How can you make preempt happen deterministically with this?
We use MI_ARB_ONOFF to ensure that we can only be preempted within the
semaphore.
> Released semaphore generates interrupt and you have it ready
> with maximum prio?
On submission of the I915_PRIORITY_BARRIER request, we will immediately
submit it to ELSP, and so queue the preemption request to HW. Since we
disable preemption in record_registers() until it hits the semaphore, we
know that the second batch must run only when the first is waiting on
that semaphore.
> I am also puzzled why there is a need for two set of reference
> values?
One is without preemption from a second context (so just one context
running on the HW). This reference should match the context image
before/after. The other is after having been preempted between the
two reads. This /should/ also match its context image...
The first checks our mechanism for reading back the registers and
comparing them to the context, the second is the actual test.
-Chris
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH 12/20] drm/i915/selftests: Verify LRC isolation
2020-02-28 11:52 ` Chris Wilson
@ 2020-02-28 12:13 ` Mika Kuoppala
0 siblings, 0 replies; 51+ messages in thread
From: Mika Kuoppala @ 2020-02-28 12:13 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Quoting Mika Kuoppala (2020-02-28 11:30:21)
>> Chris Wilson <chris@chris-wilson.co.uk> writes:
>> > + x = 0;
>> > + dw = 0;
>> > + hw = engine->pinned_default_state;
>> > + hw += LRC_STATE_PN * PAGE_SIZE / sizeof(*hw);
>> > + do {
>> > + u32 lri = hw[dw];
>> > +
>> > + if (lri == 0) {
>> > + dw++;
>> > + continue;
>> > + }
>> > +
>> > + if ((lri & GENMASK(31, 23)) != MI_INSTR(0x22, 0)) {
>> > + lri &= 0x7f;
>> > + dw += lri + 2;
>> > + continue;
>> > + }
>> > +
>> > + lri &= 0x7f;
>> > + lri++;
>> > + dw++;
>>
>> The pattern for weeding out everything except lris starts
>> to stand out as a boilerplate.
>
> Ssh. Just do a visual replacement with for_each_register()
>
>>
>> > +
>> > + while (lri) {
>> > + if (!is_moving(A[0][x], A[1][x]) &&
>> > + (A[0][x] != B[0][x] || A[1][x] != B[1][x])) {
>> > + switch (hw[dw] & 4095) {
>> > + case 0x30: /* RING_HEAD */
>> > + case 0x34: /* RING_TAIL */
>> > + break;
>> > +
>> > + default:
>> > + pr_err("%s[%d]: Mismatch for register %4x, default %08x, reference %08x, result (%08x, %08x), poison %08x, context %08x\n",
>>
>> 0x left out on all for compactness or by accident?
>
> I tend not to use 0x, unless it looks odd or we need machine parsing :)
> Here the compactness helps with a very long line.
>
>> > + engine->name, x,
>> > + hw[dw], hw[dw + 1],
>> > + A[0][x], B[0][x], B[1][x],
>> > + poison, lrc[dw + 1]);
>> > + err = -EINVAL;
>> > + break;
>> > + }
>> > + }
>> > + dw += 2;
>> > + lri -= 2;
>> > + x++;
>> > + }
>> > + } while (dw < PAGE_SIZE / sizeof(u32) &&
>> > + (hw[dw] & ~BIT(0)) != MI_BATCH_BUFFER_END);
>> > +
>> > + i915_gem_object_unpin_map(ce->state->obj);
>> > +err_B1:
>> > + i915_gem_object_unpin_map(result[1]->obj);
>> > +err_B0:
>> > + i915_gem_object_unpin_map(result[0]->obj);
>> > +err_A1:
>> > + i915_gem_object_unpin_map(ref[1]->obj);
>> > +err_A0:
>> > + i915_gem_object_unpin_map(ref[0]->obj);
>> > + return err;
>> > +}
>> > +
>> > +static int __lrc_isolation(struct intel_engine_cs *engine, u32 poison)
>> > +{
>> > + u32 *sema = memset32(engine->status_page.addr + 1000, 0, 1);
>> > + struct i915_vma *ref[2], *result[2];
>> > + struct intel_context *A, *B;
>> > + struct i915_request *rq;
>> > + int err;
>> > +
>> > + A = intel_context_create(engine);
>> > + if (IS_ERR(A))
>> > + return PTR_ERR(A);
>> > +
>> > + B = intel_context_create(engine);
>> > + if (IS_ERR(B)) {
>> > + err = PTR_ERR(B);
>> > + goto err_A;
>> > + }
>> > +
>> > + ref[0] = create_user_vma(A->vm, SZ_64K);
>> > + if (IS_ERR(ref[0])) {
>> > + err = PTR_ERR(ref[0]);
>> > + goto err_B;
>> > + }
>> > +
>> > + ref[1] = create_user_vma(A->vm, SZ_64K);
>> > + if (IS_ERR(ref[1])) {
>> > + err = PTR_ERR(ref[1]);
>> > + goto err_ref0;
>> > + }
>> > +
>> > + rq = record_registers(A, ref[0], ref[1], sema);
>> > + if (IS_ERR(rq)) {
>> > + err = PTR_ERR(rq);
>> > + goto err_ref1;
>> > + }
>> > +
>> > + WRITE_ONCE(*sema, 1);
>> > + wmb();
>>
>> So with this you get reference base for before and after...
>>
>> > +
>> > + if (i915_request_wait(rq, 0, HZ / 2) < 0) {
>> > + i915_request_put(rq);
>> > + err = -ETIME;
>> > + goto err_ref1;
>> > + }
>> > + i915_request_put(rq);
>> > +
>> > + result[0] = create_user_vma(A->vm, SZ_64K);
>> > + if (IS_ERR(result[0])) {
>> > + err = PTR_ERR(result[0]);
>> > + goto err_ref1;
>> > + }
>> > +
>> > + result[1] = create_user_vma(A->vm, SZ_64K);
>> > + if (IS_ERR(result[1])) {
>> > + err = PTR_ERR(result[1]);
>> > + goto err_result0;
>> > + }
>> > +
>> > + rq = record_registers(A, result[0], result[1], sema);
>> > + if (IS_ERR(rq)) {
>> > + err = PTR_ERR(rq);
>> > + goto err_result1;
>> > + }
>> > +
>> > + err = poison_registers(B, poison, sema);
>>
>> ..and apparently the poisoning releases the semaphore
>> triggering the preemption?
>
> Correct.
>
>> How can you make preempt happen deterministically with this?
>
> We use MI_ARB_ONOFF to ensure that we can only be preempted within the
> semaphore.
Ah yes this give you the resolution you want.
>
>> Released semaphore generates interrupt and you have it ready
>> with maximum prio?
>
> On submission of the I915_PRIORITY_BARRIER request, we will immediately
> submit it to ELSP, and so queue the preemption request to HW. Since we
> disable preemption in record_registers() until it hits the semaphore, we
> know that the second batch must run only when the first is waiting on
> that semaphore.
Thanks for the explanation.
>
>> I am also puzzled why there is a need for two set of reference
>> values?
>
> One is without preemption from a second context (so just one context
> running on the HW). This reference should match the context image
> before/after. The other is after having been preempted between the
> two reads. This /should/ also match its context image...
>
> The first checks our mechanism for reading back the registers and
> comparing them to the context, the second is the actual test.
I remember yesterday pondering in irc that it would be nice to have
an machanism to test the machinery. You must have been confused
that what do I really mean as this was the mechanism I was looking
for but didn't undestand =)
I like that it adapts to context image content and the
relative mmio trick should work for gens to come.
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> -Chris
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^ permalink raw reply [flat|nested] 51+ messages in thread
* [Intel-gfx] [PATCH 13/20] drm/i915/selftests: Check recovery from corrupted LRC
2020-02-27 8:57 [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits Chris Wilson
` (10 preceding siblings ...)
2020-02-27 8:57 ` [Intel-gfx] [PATCH 12/20] drm/i915/selftests: Verify LRC isolation Chris Wilson
@ 2020-02-27 8:57 ` Chris Wilson
2020-02-27 8:57 ` [Intel-gfx] [PATCH 14/20] drm/i915/selftests: Wait for the kernel context switch Chris Wilson
` (13 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Chris Wilson @ 2020-02-27 8:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Matthew Auld
Check that we can recover if the LRC is totally corrupted. Based on a
very simple theory that anything that can be adjusted via the context
(i.e. on behalf of the user), should be under the purview of the
per-engine-reset.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 135 +++++++++++++++++++++++++
1 file changed, 135 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 810f7857ad26..d7f98aada626 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -5292,6 +5292,140 @@ static int live_lrc_isolation(void *arg)
return 0;
}
+static void garbage_reset(struct intel_engine_cs *engine,
+ struct i915_request *rq)
+{
+ const unsigned int bit = I915_RESET_ENGINE + engine->id;
+ unsigned long *lock = &engine->gt->reset.flags;
+
+ if (test_and_set_bit(bit, lock))
+ return;
+
+ tasklet_disable(&engine->execlists.tasklet);
+
+ if (!rq->fence.error)
+ intel_engine_reset(engine, NULL);
+
+ tasklet_enable(&engine->execlists.tasklet);
+ clear_and_wake_up_bit(bit, lock);
+}
+
+static struct i915_request *garbage(struct intel_context *ce,
+ struct rnd_state *prng)
+{
+ struct i915_request *rq;
+ int err;
+
+ err = intel_context_pin(ce);
+ if (err)
+ return ERR_PTR(err);
+
+ prandom_bytes_state(prng,
+ ce->lrc_reg_state,
+ ce->engine->context_size -
+ LRC_STATE_PN * PAGE_SIZE);
+
+ rq = intel_context_create_request(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_unpin;
+ }
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+ return rq;
+
+err_unpin:
+ intel_context_unpin(ce);
+ return ERR_PTR(err);
+}
+
+static int __lrc_garbage(struct intel_engine_cs *engine, struct rnd_state *prng)
+{
+ struct intel_context *ce;
+ struct i915_request *hang;
+ int err = 0;
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ hang = garbage(ce, prng);
+ if (IS_ERR(hang)) {
+ err = PTR_ERR(hang);
+ goto err_ce;
+ }
+
+ if (wait_for_submit(engine, hang, HZ / 2)) {
+ i915_request_put(hang);
+ err = -ETIME;
+ goto err_ce;
+ }
+
+ intel_context_set_banned(ce);
+ garbage_reset(engine, hang);
+
+ intel_engine_flush_submission(engine);
+ if (!hang->fence.error) {
+ i915_request_put(hang);
+ pr_err("%s: corrupted context was not reset\n",
+ engine->name);
+ err = -EINVAL;
+ goto err_ce;
+ }
+
+ if (i915_request_wait(hang, 0, HZ / 2) < 0) {
+ pr_err("%s: corrupted context did not recover\n",
+ engine->name);
+ i915_request_put(hang);
+ err = -EIO;
+ goto err_ce;
+ }
+ i915_request_put(hang);
+
+err_ce:
+ intel_context_put(ce);
+ return err;
+}
+
+static int live_lrc_garbage(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+
+ /*
+ * Verify that we can recover if one context state is completely
+ * corrupted.
+ */
+
+ if (!IS_ENABLED(CONFIG_DRM_I915_SELFTEST_BROKEN))
+ return 0;
+
+ for_each_engine(engine, gt, id) {
+ I915_RND_STATE(prng);
+ int err = 0, i;
+
+ if (!intel_has_reset_engine(engine->gt))
+ continue;
+
+ intel_engine_pm_get(engine);
+ for (i = 0; i < 3; i++) {
+ err = __lrc_garbage(engine, &prng);
+ if (err)
+ break;
+ }
+ intel_engine_pm_put(engine);
+
+ if (igt_flush_test(gt->i915))
+ err = -EIO;
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
static int __live_pphwsp_runtime(struct intel_engine_cs *engine)
{
struct intel_context *ce;
@@ -5391,6 +5525,7 @@ int intel_lrc_live_selftests(struct drm_i915_private *i915)
SUBTEST(live_lrc_gpr),
SUBTEST(live_lrc_isolation),
SUBTEST(live_lrc_timestamp),
+ SUBTEST(live_lrc_garbage),
SUBTEST(live_pphwsp_runtime),
};
--
2.25.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 51+ messages in thread* [Intel-gfx] [PATCH 14/20] drm/i915/selftests: Wait for the kernel context switch
2020-02-27 8:57 [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits Chris Wilson
` (11 preceding siblings ...)
2020-02-27 8:57 ` [Intel-gfx] [PATCH 13/20] drm/i915/selftests: Check recovery from corrupted LRC Chris Wilson
@ 2020-02-27 8:57 ` Chris Wilson
2020-02-27 8:57 ` [Intel-gfx] [PATCH 15/20] drm/i915/selftests: Be a little more lenient for reset workers Chris Wilson
` (12 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Chris Wilson @ 2020-02-27 8:57 UTC (permalink / raw)
To: intel-gfx
As we require a context switch to ensure that the current context is
switched out and saved to memory, perform an explicit switch to the
kernel context and wait for it.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 37 +++++++++++++++++++-------
1 file changed, 28 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index d7f98aada626..95da6b880e3f 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -4015,6 +4015,31 @@ static int emit_semaphore_signal(struct intel_context *ce, void *slot)
return 0;
}
+static int context_sync(struct intel_context *ce)
+{
+ struct i915_request *rq;
+ struct dma_fence *fence;
+ int err = 0;
+
+ rq = intel_engine_create_kernel_request(ce->engine);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ fence = i915_active_fence_get(&ce->timeline->last_request);
+ if (fence) {
+ i915_request_await_dma_fence(rq, fence);
+ dma_fence_put(fence);
+ }
+
+ rq = i915_request_get(rq);
+ i915_request_add(rq);
+ if (i915_request_wait(rq, 0, HZ / 2) < 0)
+ err = -ETIME;
+ i915_request_put(rq);
+
+ return err;
+}
+
static int live_lrc_layout(void *arg)
{
struct intel_gt *gt = arg;
@@ -4638,16 +4663,10 @@ static int __lrc_timestamp(const struct lrc_timestamp *arg, bool preempt)
wmb();
}
- if (i915_request_wait(rq, 0, HZ / 2) < 0) {
- err = -ETIME;
- goto err;
- }
-
- /* and wait for switch to kernel */
- if (igt_flush_test(arg->engine->i915)) {
- err = -EIO;
+ /* and wait for switch to kernel (to save our context to memory) */
+ err = context_sync(arg->ce[0]);
+ if (err)
goto err;
- }
rmb();
--
2.25.1
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^ permalink raw reply related [flat|nested] 51+ messages in thread* [Intel-gfx] [PATCH 15/20] drm/i915/selftests: Be a little more lenient for reset workers
2020-02-27 8:57 [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits Chris Wilson
` (12 preceding siblings ...)
2020-02-27 8:57 ` [Intel-gfx] [PATCH 14/20] drm/i915/selftests: Wait for the kernel context switch Chris Wilson
@ 2020-02-27 8:57 ` Chris Wilson
2020-02-27 8:57 ` [Intel-gfx] [PATCH 16/20] drm/i915/selftests: Add request throughput measurement to perf Chris Wilson
` (11 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Chris Wilson @ 2020-02-27 8:57 UTC (permalink / raw)
To: intel-gfx
Give the reset worker a kick before losing help when waiting for hang
recovery, as the CPU scheduler is a little unreliable.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 74 ++++++++++++++++++--------
1 file changed, 52 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_lrc.c b/drivers/gpu/drm/i915/gt/selftest_lrc.c
index 95da6b880e3f..af5b3da6d894 100644
--- a/drivers/gpu/drm/i915/gt/selftest_lrc.c
+++ b/drivers/gpu/drm/i915/gt/selftest_lrc.c
@@ -90,6 +90,48 @@ static int wait_for_submit(struct intel_engine_cs *engine,
return -ETIME;
}
+static int wait_for_reset(struct intel_engine_cs *engine,
+ struct i915_request *rq,
+ unsigned long timeout)
+{
+ timeout += jiffies;
+ do {
+ cond_resched();
+ intel_engine_flush_submission(engine);
+
+ if (READ_ONCE(engine->execlists.pending[0]))
+ continue;
+
+ if (i915_request_completed(rq))
+ break;
+
+ if (READ_ONCE(rq->fence.error))
+ break;
+ } while (time_before(jiffies, timeout));
+
+ flush_scheduled_work();
+
+ if (rq->fence.error != -EIO) {
+ pr_err("%s: hanging request %llx:%lld not reset\n",
+ engine->name,
+ rq->fence.context,
+ rq->fence.seqno);
+ return -EINVAL;
+ }
+
+ /* Give the request a jiffie to complete after flushing the worker */
+ if (i915_request_wait(rq, 0,
+ max(0l, (long)(timeout - jiffies)) + 1) < 0) {
+ pr_err("%s: hanging request %llx:%lld did not complete\n",
+ engine->name,
+ rq->fence.context,
+ rq->fence.seqno);
+ return -ETIME;
+ }
+
+ return 0;
+}
+
static int live_sanitycheck(void *arg)
{
struct intel_gt *gt = arg;
@@ -1805,14 +1847,9 @@ static int __cancel_active0(struct live_preempt_cancel *arg)
if (err)
goto out;
- if (i915_request_wait(rq, 0, HZ / 5) < 0) {
- err = -EIO;
- goto out;
- }
-
- if (rq->fence.error != -EIO) {
- pr_err("Cancelled inflight0 request did not report -EIO\n");
- err = -EINVAL;
+ err = wait_for_reset(arg->engine, rq, HZ / 2);
+ if (err) {
+ pr_err("Cancelled inflight0 request did not reset\n");
goto out;
}
@@ -1870,10 +1907,9 @@ static int __cancel_active1(struct live_preempt_cancel *arg)
goto out;
igt_spinner_end(&arg->a.spin);
- if (i915_request_wait(rq[1], 0, HZ / 5) < 0) {
- err = -EIO;
+ err = wait_for_reset(arg->engine, rq[1], HZ / 2);
+ if (err)
goto out;
- }
if (rq[0]->fence.error != 0) {
pr_err("Normal inflight0 request did not complete\n");
@@ -1953,10 +1989,9 @@ static int __cancel_queued(struct live_preempt_cancel *arg)
if (err)
goto out;
- if (i915_request_wait(rq[2], 0, HZ / 5) < 0) {
- err = -EIO;
+ err = wait_for_reset(arg->engine, rq[2], HZ / 2);
+ if (err)
goto out;
- }
if (rq[0]->fence.error != -EIO) {
pr_err("Cancelled inflight0 request did not report -EIO\n");
@@ -2014,14 +2049,9 @@ static int __cancel_hostile(struct live_preempt_cancel *arg)
if (err)
goto out;
- if (i915_request_wait(rq, 0, HZ / 5) < 0) {
- err = -EIO;
- goto out;
- }
-
- if (rq->fence.error != -EIO) {
- pr_err("Cancelled inflight0 request did not report -EIO\n");
- err = -EINVAL;
+ err = wait_for_reset(arg->engine, rq, HZ / 2);
+ if (err) {
+ pr_err("Cancelled inflight0 request did not reset\n");
goto out;
}
--
2.25.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 51+ messages in thread* [Intel-gfx] [PATCH 16/20] drm/i915/selftests: Add request throughput measurement to perf
2020-02-27 8:57 [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits Chris Wilson
` (13 preceding siblings ...)
2020-02-27 8:57 ` [Intel-gfx] [PATCH 15/20] drm/i915/selftests: Be a little more lenient for reset workers Chris Wilson
@ 2020-02-27 8:57 ` Chris Wilson
2020-02-27 8:57 ` [Intel-gfx] [PATCH 17/20] drm/i915/gt: Declare when we enabled timeslicing Chris Wilson
` (10 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Chris Wilson @ 2020-02-27 8:57 UTC (permalink / raw)
To: intel-gfx
Under ideal circumstances, the driver should be able to keep the GPU
fully saturated with work. Measure how close to ideal we get under the
harshest of conditions with no user payload.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
.../drm/i915/selftests/i915_perf_selftests.h | 1 +
drivers/gpu/drm/i915/selftests/i915_request.c | 280 +++++++++++++++++-
2 files changed, 280 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
index 3bf7f53e9924..d8da142985eb 100644
--- a/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
+++ b/drivers/gpu/drm/i915/selftests/i915_perf_selftests.h
@@ -16,5 +16,6 @@
* Tests are executed in order by igt/i915_selftest
*/
selftest(engine_cs, intel_engine_cs_perf_selftests)
+selftest(request, i915_request_perf_selftests)
selftest(blt, i915_gem_object_blt_perf_selftests)
selftest(region, intel_memory_region_perf_selftests)
diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c
index f89d9c42f1fa..91f67995f0ac 100644
--- a/drivers/gpu/drm/i915/selftests/i915_request.c
+++ b/drivers/gpu/drm/i915/selftests/i915_request.c
@@ -23,6 +23,7 @@
*/
#include <linux/prime_numbers.h>
+#include <linux/pm_qos.h>
#include "gem/i915_gem_pm.h"
#include "gem/selftests/mock_context.h"
@@ -1233,7 +1234,7 @@ static int live_parallel_engines(void *arg)
struct igt_live_test t;
unsigned int idx;
- snprintf(name, sizeof(name), "%pS", fn);
+ snprintf(name, sizeof(name), "%ps", *fn);
err = igt_live_test_begin(&t, i915, __func__, name);
if (err)
break;
@@ -1470,3 +1471,280 @@ int i915_request_live_selftests(struct drm_i915_private *i915)
return i915_subtests(tests, i915);
}
+
+struct perf_parallel {
+ struct intel_engine_cs *engine;
+ unsigned long count;
+ ktime_t time;
+ ktime_t busy;
+ u64 runtime;
+};
+
+static int switch_to_kernel_sync(struct intel_context *ce, int err)
+{
+ struct i915_request *rq;
+ struct dma_fence *fence;
+
+ rq = intel_engine_create_kernel_request(ce->engine);
+ if (IS_ERR(rq))
+ return PTR_ERR(rq);
+
+ fence = i915_active_fence_get(&ce->timeline->last_request);
+ if (fence) {
+ i915_request_await_dma_fence(rq, fence);
+ dma_fence_put(fence);
+ }
+
+ rq = i915_request_get(rq);
+ i915_request_add(rq);
+ if (i915_request_wait(rq, 0, HZ / 2) < 0 && !err)
+ err = -ETIME;
+ i915_request_put(rq);
+
+ while (!err && !intel_engine_is_idle(ce->engine))
+ intel_engine_flush_submission(ce->engine);
+
+ return err;
+}
+
+static int perf_sync(void *arg)
+{
+ struct perf_parallel *p = arg;
+ struct intel_engine_cs *engine = p->engine;
+ struct intel_context *ce;
+ IGT_TIMEOUT(end_time);
+ unsigned long count;
+ bool busy;
+ int err = 0;
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ err = intel_context_pin(ce);
+ if (err) {
+ intel_context_put(ce);
+ return err;
+ }
+
+ busy = false;
+ if (intel_engine_supports_stats(engine) &&
+ !intel_enable_engine_stats(engine)) {
+ p->busy = intel_engine_get_busy_time(engine);
+ busy = true;
+ }
+
+ p->time = ktime_get();
+ count = 0;
+ do {
+ struct i915_request *rq;
+
+ rq = i915_request_create(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ break;
+ }
+
+ i915_request_get(rq);
+ i915_request_add(rq);
+
+ err = 0;
+ if (i915_request_wait(rq, 0, HZ / 5) < 0)
+ err = -ETIME;
+ i915_request_put(rq);
+ if (err)
+ break;
+
+ count++;
+ } while (!__igt_timeout(end_time, NULL));
+ p->time = ktime_sub(ktime_get(), p->time);
+
+ if (busy) {
+ p->busy = ktime_sub(intel_engine_get_busy_time(engine),
+ p->busy);
+ intel_disable_engine_stats(engine);
+ }
+
+ err = switch_to_kernel_sync(ce, err);
+ p->runtime = intel_context_get_total_runtime_ns(ce);
+ p->count = count;
+
+ intel_context_unpin(ce);
+ intel_context_put(ce);
+ return err;
+}
+
+static int perf_many(void *arg)
+{
+ struct perf_parallel *p = arg;
+ struct intel_engine_cs *engine = p->engine;
+ struct intel_context *ce;
+ IGT_TIMEOUT(end_time);
+ unsigned long count;
+ int err = 0;
+ bool busy;
+
+ ce = intel_context_create(engine);
+ if (IS_ERR(ce))
+ return PTR_ERR(ce);
+
+ err = intel_context_pin(ce);
+ if (err) {
+ intel_context_put(ce);
+ return err;
+ }
+
+ busy = false;
+ if (intel_engine_supports_stats(engine) &&
+ !intel_enable_engine_stats(engine)) {
+ p->busy = intel_engine_get_busy_time(engine);
+ busy = true;
+ }
+
+ count = 0;
+ p->time = ktime_get();
+ do {
+ struct i915_request *rq;
+
+ rq = i915_request_create(ce);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ break;
+ }
+
+ i915_request_add(rq);
+ count++;
+ } while (!__igt_timeout(end_time, NULL));
+ p->time = ktime_sub(ktime_get(), p->time);
+
+ if (busy) {
+ p->busy = ktime_sub(intel_engine_get_busy_time(engine),
+ p->busy);
+ intel_disable_engine_stats(engine);
+ }
+
+ err = switch_to_kernel_sync(ce, err);
+ p->runtime = intel_context_get_total_runtime_ns(ce);
+ p->count = count;
+
+ intel_context_unpin(ce);
+ intel_context_put(ce);
+ return err;
+}
+
+static int perf_parallel_engines(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ static int (* const func[])(void *arg) = {
+ perf_sync,
+ perf_many,
+ NULL,
+ };
+ const unsigned int nengines = num_uabi_engines(i915);
+ struct pm_qos_request qos = {};
+ struct intel_engine_cs *engine;
+ int (* const *fn)(void *arg);
+ struct {
+ struct perf_parallel p;
+ struct task_struct *tsk;
+ } *engines;
+ int err = 0;
+
+ engines = kcalloc(nengines, sizeof(*engines), GFP_KERNEL);
+ if (!engines)
+ return -ENOMEM;
+
+ pm_qos_add_request(&qos, PM_QOS_CPU_DMA_LATENCY, 0);
+
+ for (fn = func; *fn; fn++) {
+ char name[KSYM_NAME_LEN];
+ struct igt_live_test t;
+ unsigned int idx;
+
+ snprintf(name, sizeof(name), "%ps", *fn);
+ err = igt_live_test_begin(&t, i915, __func__, name);
+ if (err)
+ break;
+
+ atomic_set(&i915->selftest.counter, nengines);
+
+ idx = 0;
+ for_each_uabi_engine(engine, i915) {
+ intel_engine_pm_get(engine);
+
+ memset(&engines[idx].p, 0, sizeof(engines[idx].p));
+ engines[idx].p.engine = engine;
+
+ engines[idx].tsk = kthread_run(*fn, &engines[idx].p,
+ "igt:%s", engine->name);
+ if (IS_ERR(engines[idx].tsk)) {
+ err = PTR_ERR(engines[idx].tsk);
+ intel_engine_pm_put(engine);
+ break;
+ }
+ get_task_struct(engines[idx++].tsk);
+ }
+
+ yield(); /* start all threads before we kthread_stop() */
+
+ idx = 0;
+ for_each_uabi_engine(engine, i915) {
+ int status;
+
+ if (IS_ERR(engines[idx].tsk))
+ break;
+
+ status = kthread_stop(engines[idx].tsk);
+ if (status && !err)
+ err = status;
+
+ intel_engine_pm_put(engine);
+ put_task_struct(engines[idx++].tsk);
+ }
+
+ if (igt_live_test_end(&t))
+ err = -EIO;
+ if (err)
+ break;
+
+ idx = 0;
+ for_each_uabi_engine(engine, i915) {
+ struct perf_parallel *p = &engines[idx].p;
+ u64 busy = 100 * ktime_to_ns(p->busy);
+ u64 dt = ktime_to_ns(p->time);
+ int integer, decimal;
+
+ if (dt) {
+ integer = div64_u64(busy, dt);
+ busy -= integer * dt;
+ decimal = div64_u64(100 * busy, dt);
+ } else {
+ integer = 0;
+ decimal = 0;
+ }
+
+ GEM_BUG_ON(engine != p->engine);
+ pr_info("%s %5s: { count:%lu, busy:%d.%02d%%, runtime:%lldms, walltime:%lldms }\n",
+ name, engine->name, p->count, integer, decimal,
+ div_u64(p->runtime, 1000 * 1000),
+ div_u64(ktime_to_ns(p->time), 1000 * 1000));
+ idx++;
+ }
+ }
+
+ pm_qos_remove_request(&qos);
+ kfree(engines);
+ return err;
+}
+
+int i915_request_perf_selftests(struct drm_i915_private *i915)
+{
+ static const struct i915_subtest tests[] = {
+ SUBTEST(perf_parallel_engines),
+ };
+
+ if (intel_gt_is_wedged(&i915->gt))
+ return 0;
+
+ return i915_subtests(tests, i915);
+}
--
2.25.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 51+ messages in thread* [Intel-gfx] [PATCH 17/20] drm/i915/gt: Declare when we enabled timeslicing
2020-02-27 8:57 [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits Chris Wilson
` (14 preceding siblings ...)
2020-02-27 8:57 ` [Intel-gfx] [PATCH 16/20] drm/i915/selftests: Add request throughput measurement to perf Chris Wilson
@ 2020-02-27 8:57 ` Chris Wilson
2020-02-28 12:45 ` Tvrtko Ursulin
2020-02-27 8:57 ` [Intel-gfx] [PATCH 18/20] drm/i915/gt: Yield the timeslice if caught waiting on a user semaphore Chris Wilson
` (9 subsequent siblings)
25 siblings, 1 reply; 51+ messages in thread
From: Chris Wilson @ 2020-02-27 8:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Kenneth Graunke
Let userspace know if they can trust timeslicing by including it as part
of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING
v2: Only declare timeslicing if we can safely preempt userspace.
Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Kenneth Graunke <kenneth@whitecape.org>
---
drivers/gpu/drm/i915/gt/intel_engine.h | 3 ++-
drivers/gpu/drm/i915/gt/intel_engine_user.c | 5 +++++
include/uapi/drm/i915_drm.h | 1 +
3 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 29c8c03c5caa..a32dc82a90d4 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -326,7 +326,8 @@ intel_engine_has_timeslices(const struct intel_engine_cs *engine)
if (!IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION))
return false;
- return intel_engine_has_semaphores(engine);
+ return (intel_engine_has_semaphores(engine) &&
+ intel_engine_has_preemption(engine));
}
#endif /* _INTEL_RINGBUFFER_H_ */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 848decee9066..b84fdd722781 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -121,6 +121,11 @@ static void set_scheduler_caps(struct drm_i915_private *i915)
else
disabled |= BIT(map[i].sched);
}
+
+ if (intel_engine_has_timeslices(engine))
+ enabled |= I915_SCHEDULER_CAP_TIMESLICING;
+ else
+ disabled |= I915_SCHEDULER_CAP_TIMESLICING;
}
i915->caps.scheduler = enabled & ~disabled;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 2813e579b480..4f903431a3fe 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -523,6 +523,7 @@ typedef struct drm_i915_irq_wait {
#define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
#define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
#define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
+#define I915_SCHEDULER_CAP_TIMESLICING (1ul << 5)
#define I915_PARAM_HUC_STATUS 42
--
2.25.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH 17/20] drm/i915/gt: Declare when we enabled timeslicing
2020-02-27 8:57 ` [Intel-gfx] [PATCH 17/20] drm/i915/gt: Declare when we enabled timeslicing Chris Wilson
@ 2020-02-28 12:45 ` Tvrtko Ursulin
2020-02-28 13:14 ` Chris Wilson
0 siblings, 1 reply; 51+ messages in thread
From: Tvrtko Ursulin @ 2020-02-28 12:45 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: Kenneth Graunke
On 27/02/2020 08:57, Chris Wilson wrote:
> Let userspace know if they can trust timeslicing by including it as part
> of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING
>
> v2: Only declare timeslicing if we can safely preempt userspace.
>
> Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Kenneth Graunke <kenneth@whitecape.org>
> ---
> drivers/gpu/drm/i915/gt/intel_engine.h | 3 ++-
> drivers/gpu/drm/i915/gt/intel_engine_user.c | 5 +++++
> include/uapi/drm/i915_drm.h | 1 +
> 3 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
> index 29c8c03c5caa..a32dc82a90d4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -326,7 +326,8 @@ intel_engine_has_timeslices(const struct intel_engine_cs *engine)
> if (!IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION))
> return false;
>
> - return intel_engine_has_semaphores(engine);
> + return (intel_engine_has_semaphores(engine) &&
> + intel_engine_has_preemption(engine));
This could be the fixes bit.
AFAIR has_semaphores is can we preempt between batches and
has_preemption is can we preempt inside them. What was the consequence
of not considering this in has_timeslices?
> }
>
> #endif /* _INTEL_RINGBUFFER_H_ */
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> index 848decee9066..b84fdd722781 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> @@ -121,6 +121,11 @@ static void set_scheduler_caps(struct drm_i915_private *i915)
> else
> disabled |= BIT(map[i].sched);
> }
> +
> + if (intel_engine_has_timeslices(engine))
> + enabled |= I915_SCHEDULER_CAP_TIMESLICING;
> + else
> + disabled |= I915_SCHEDULER_CAP_TIMESLICING;
> }
>
> i915->caps.scheduler = enabled & ~disabled;
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 2813e579b480..4f903431a3fe 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -523,6 +523,7 @@ typedef struct drm_i915_irq_wait {
> #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
> #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
> #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
> +#define I915_SCHEDULER_CAP_TIMESLICING (1ul << 5)
And this would be the new uapi bit.
Split into two patches?
Regards,
Tvrtko
>
> #define I915_PARAM_HUC_STATUS 42
>
>
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH 17/20] drm/i915/gt: Declare when we enabled timeslicing
2020-02-28 12:45 ` Tvrtko Ursulin
@ 2020-02-28 13:14 ` Chris Wilson
0 siblings, 0 replies; 51+ messages in thread
From: Chris Wilson @ 2020-02-28 13:14 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx; +Cc: Kenneth Graunke
Quoting Tvrtko Ursulin (2020-02-28 12:45:42)
>
> On 27/02/2020 08:57, Chris Wilson wrote:
> > Let userspace know if they can trust timeslicing by including it as part
> > of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING
> >
> > v2: Only declare timeslicing if we can safely preempt userspace.
> >
> > Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing")
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Kenneth Graunke <kenneth@whitecape.org>
> > ---
> > drivers/gpu/drm/i915/gt/intel_engine.h | 3 ++-
> > drivers/gpu/drm/i915/gt/intel_engine_user.c | 5 +++++
> > include/uapi/drm/i915_drm.h | 1 +
> > 3 files changed, 8 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
> > index 29c8c03c5caa..a32dc82a90d4 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> > @@ -326,7 +326,8 @@ intel_engine_has_timeslices(const struct intel_engine_cs *engine)
> > if (!IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION))
> > return false;
> >
> > - return intel_engine_has_semaphores(engine);
> > + return (intel_engine_has_semaphores(engine) &&
> > + intel_engine_has_preemption(engine));
>
> This could be the fixes bit.
Nah, I quite liked timeslicing between requests -- but I decided that if
we are to make a statement userspace can rely on, it has to be
timeslicing works inside userspace batches.
> AFAIR has_semaphores is can we preempt between batches and
> has_preemption is can we preempt inside them. What was the consequence
> of not considering this in has_timeslices?
Right. It meant the timeslice could only take effect in the
MI_ARB_ENABLE window in between requests. That is we could break up long
amalgamations of contexts, but not the user.
So I don't think this bit is the fixes.
> > #endif /* _INTEL_RINGBUFFER_H_ */
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > index 848decee9066..b84fdd722781 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > @@ -121,6 +121,11 @@ static void set_scheduler_caps(struct drm_i915_private *i915)
> > else
> > disabled |= BIT(map[i].sched);
> > }
> > +
> > + if (intel_engine_has_timeslices(engine))
> > + enabled |= I915_SCHEDULER_CAP_TIMESLICING;
> > + else
> > + disabled |= I915_SCHEDULER_CAP_TIMESLICING;
> > }
> >
> > i915->caps.scheduler = enabled & ~disabled;
> > diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> > index 2813e579b480..4f903431a3fe 100644
> > --- a/include/uapi/drm/i915_drm.h
> > +++ b/include/uapi/drm/i915_drm.h
> > @@ -523,6 +523,7 @@ typedef struct drm_i915_irq_wait {
> > #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
> > #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
> > #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
> > +#define I915_SCHEDULER_CAP_TIMESLICING (1ul << 5)
>
> And this would be the new uapi bit.
>
> Split into two patches?
Nah. This is the Fixes: that I need to use semaphores in iris :)
And I think CAP_TIMESLICING has to mean userspace is timesliced (to the
granularity of objects at least) for it to mean anything userspace can
take advantage of.
-Chris
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^ permalink raw reply [flat|nested] 51+ messages in thread
* [Intel-gfx] [PATCH 18/20] drm/i915/gt: Yield the timeslice if caught waiting on a user semaphore
2020-02-27 8:57 [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits Chris Wilson
` (15 preceding siblings ...)
2020-02-27 8:57 ` [Intel-gfx] [PATCH 17/20] drm/i915/gt: Declare when we enabled timeslicing Chris Wilson
@ 2020-02-27 8:57 ` Chris Wilson
2020-02-27 8:57 ` [Intel-gfx] [PATCH 19/20] drm/i915/execlists: Check the sentinel is alone in the ELSP Chris Wilson
` (8 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Chris Wilson @ 2020-02-27 8:57 UTC (permalink / raw)
To: intel-gfx; +Cc: Kenneth Graunke
If we find ourselves waiting on a MI_SEMAPHORE_WAIT, either within the
user batch or in our own preamble, the engine raises a
GT_WAIT_ON_SEMAPHORE interrupt. We can unmask that interrupt and so
respond to a semaphore wait by yielding the timeslice, if we have
another context to yield to!
The only real complication is that the interrupt is only generated for
the start of the semaphore wait, and is asynchronous to our
process_csb() -- that is, we may not have registered the timeslice before
we see the interrupt. To ensure we don't miss a potential semaphore
blocking forward progress (e.g. selftests/live_timeslice_preempt) we mark
the interrupt and apply it to the next timeslice regardless of whether it
was active at the time.
v2: We use semaphores in preempt-to-busy, within the timeslicing
implementation itself! Ergo, when we do insert a preemption due to an
expired timeslice, the new context may start with the missed semaphore
flagged by the retired context and be yielded, ad infinitum. To avoid
this, read the context id at the time of the semaphore interrupt and
only yield if that context is still active.
Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 6 +++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 9 +++++
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 13 ++++++-
drivers/gpu/drm/i915/gt/intel_lrc.c | 40 +++++++++++++++++---
drivers/gpu/drm/i915/i915_reg.h | 1 +
5 files changed, 61 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 119c9cb24fd4..eec6e3245a97 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1288,6 +1288,12 @@ static void intel_engine_print_registers(struct intel_engine_cs *engine,
if (engine->id == RENDER_CLASS && IS_GEN_RANGE(dev_priv, 4, 7))
drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
+ if (HAS_EXECLISTS(dev_priv)) {
+ drm_printf(m, "\tEL_STAT_HI: 0x%08x\n",
+ ENGINE_READ(engine, RING_EXECLIST_STATUS_HI));
+ drm_printf(m, "\tEL_STAT_LO: 0x%08x\n",
+ ENGINE_READ(engine, RING_EXECLIST_STATUS_LO));
+ }
drm_printf(m, "\tRING_START: 0x%08x\n",
ENGINE_READ(engine, RING_START));
drm_printf(m, "\tRING_HEAD: 0x%08x\n",
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index b23366a81048..24cff658e6e5 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -156,6 +156,15 @@ struct intel_engine_execlists {
*/
struct i915_priolist default_priolist;
+ /**
+ * @yield: CCID at the time of the last semaphore-wait interrupt.
+ *
+ * Instead of leaving a semaphore busy-spinning on an engine, we would
+ * like to switch to another ready context, i.e. yielding the semaphore
+ * timeslice.
+ */
+ u32 yield;
+
/**
* @error_interrupt: CS Master EIR
*
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index f0e7fd95165a..875bd0392ffc 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -39,6 +39,13 @@ cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
}
}
+ if (iir & GT_WAIT_SEMAPHORE_INTERRUPT) {
+ WRITE_ONCE(engine->execlists.yield,
+ ENGINE_READ_FW(engine, RING_EXECLIST_STATUS_HI));
+ if (del_timer(&engine->execlists.timer))
+ tasklet = true;
+ }
+
if (iir & GT_CONTEXT_SWITCH_INTERRUPT)
tasklet = true;
@@ -228,7 +235,8 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
const u32 irqs =
GT_CS_MASTER_ERROR_INTERRUPT |
GT_RENDER_USER_INTERRUPT |
- GT_CONTEXT_SWITCH_INTERRUPT;
+ GT_CONTEXT_SWITCH_INTERRUPT |
+ GT_WAIT_SEMAPHORE_INTERRUPT;
struct intel_uncore *uncore = gt->uncore;
const u32 dmask = irqs << 16 | irqs;
const u32 smask = irqs << 16;
@@ -366,7 +374,8 @@ void gen8_gt_irq_postinstall(struct intel_gt *gt)
const u32 irqs =
GT_CS_MASTER_ERROR_INTERRUPT |
GT_RENDER_USER_INTERRUPT |
- GT_CONTEXT_SWITCH_INTERRUPT;
+ GT_CONTEXT_SWITCH_INTERRUPT |
+ GT_WAIT_SEMAPHORE_INTERRUPT;
const u32 gt_interrupts[] = {
irqs << GEN8_RCS_IRQ_SHIFT | irqs << GEN8_BCS_IRQ_SHIFT,
irqs << GEN8_VCS0_IRQ_SHIFT | irqs << GEN8_VCS1_IRQ_SHIFT,
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 35c5cf786726..253e89fecd95 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1728,7 +1728,8 @@ static void defer_active(struct intel_engine_cs *engine)
}
static bool
-need_timeslice(struct intel_engine_cs *engine, const struct i915_request *rq)
+need_timeslice(const struct intel_engine_cs *engine,
+ const struct i915_request *rq)
{
int hint;
@@ -1744,6 +1745,31 @@ need_timeslice(struct intel_engine_cs *engine, const struct i915_request *rq)
return hint >= effective_prio(rq);
}
+static bool
+timeslice_yield(const struct intel_engine_execlists *el,
+ const struct i915_request *rq)
+{
+ /*
+ * Once bitten, forever smitten!
+ *
+ * If the active context ever busy-waited on a semaphore,
+ * it will be treated as a hog until the end of its timeslice.
+ * The HW only sends an interrupt on the first miss, and we
+ * do know if that semaphore has been signaled, or even if it
+ * is now stuck on another semaphore. Play safe, yield if it
+ * might be stuck -- it will be given a fresh timeslice in
+ * the near future.
+ */
+ return upper_32_bits(rq->context->lrc_desc) == READ_ONCE(el->yield);
+}
+
+static bool
+timeslice_expired(const struct intel_engine_execlists *el,
+ const struct i915_request *rq)
+{
+ return timer_expired(&el->timer) || timeslice_yield(el, rq);
+}
+
static int
switch_prio(struct intel_engine_cs *engine, const struct i915_request *rq)
{
@@ -1759,8 +1785,7 @@ timeslice(const struct intel_engine_cs *engine)
return READ_ONCE(engine->props.timeslice_duration_ms);
}
-static unsigned long
-active_timeslice(const struct intel_engine_cs *engine)
+static unsigned long active_timeslice(const struct intel_engine_cs *engine)
{
const struct i915_request *rq = *engine->execlists.active;
@@ -1903,13 +1928,14 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
last = NULL;
} else if (need_timeslice(engine, last) &&
- timer_expired(&engine->execlists.timer)) {
+ timeslice_expired(execlists, last)) {
ENGINE_TRACE(engine,
- "expired last=%llx:%lld, prio=%d, hint=%d\n",
+ "expired last=%llx:%lld, prio=%d, hint=%d, yield?=%s\n",
last->fence.context,
last->fence.seqno,
last->sched.attr.priority,
- execlists->queue_priority_hint);
+ execlists->queue_priority_hint,
+ yesno(timeslice_yield(execlists, last)));
ring_set_paused(engine, 1);
defer_active(engine);
@@ -2169,6 +2195,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
}
clear_ports(port + 1, last_port - port);
+ WRITE_ONCE(execlists->yield, -1);
execlists_submit_ports(engine);
set_preempt_timeout(engine);
} else {
@@ -4417,6 +4444,7 @@ logical_ring_default_irqs(struct intel_engine_cs *engine)
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
engine->irq_keep_mask |= GT_CS_MASTER_ERROR_INTERRUPT << shift;
+ engine->irq_keep_mask |= GT_WAIT_SEMAPHORE_INTERRUPT << shift;
}
static void rcs_submission_override(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f45b5e86ec63..0b5e669c4867 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3092,6 +3092,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
#define GT_BSD_USER_INTERRUPT (1 << 12)
#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
+#define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) /* bdw+ */
#define GT_CONTEXT_SWITCH_INTERRUPT (1 << 8)
#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
--
2.25.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 51+ messages in thread* [Intel-gfx] [PATCH 19/20] drm/i915/execlists: Check the sentinel is alone in the ELSP
2020-02-27 8:57 [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits Chris Wilson
` (16 preceding siblings ...)
2020-02-27 8:57 ` [Intel-gfx] [PATCH 18/20] drm/i915/gt: Yield the timeslice if caught waiting on a user semaphore Chris Wilson
@ 2020-02-27 8:57 ` Chris Wilson
2020-02-27 8:57 ` [Intel-gfx] [PATCH 20/20] drm/i915/execlists: Reduce preempt-to-busy roundtrip delay Chris Wilson
` (7 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Chris Wilson @ 2020-02-27 8:57 UTC (permalink / raw)
To: intel-gfx
We only use sentinel requests for "preempt-to-idle" passes, so assert
that they are the only request in a new submission.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 253e89fecd95..d907b5ebc1a4 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1448,6 +1448,7 @@ assert_pending_valid(const struct intel_engine_execlists *execlists,
{
struct i915_request * const *port, *rq;
struct intel_context *ce = NULL;
+ bool sentinel = false;
trace_ports(execlists, msg, execlists->pending);
@@ -1481,6 +1482,26 @@ assert_pending_valid(const struct intel_engine_execlists *execlists,
}
ce = rq->context;
+ /*
+ * Sentinels are supposed to be lonely so they flush the
+ * current exection off the HW. Check that they are the
+ * only request in the pending submission.
+ */
+ if (sentinel) {
+ GEM_TRACE_ERR("context:%llx after sentinel in pending[%zd]\n",
+ ce->timeline->fence_context,
+ port - execlists->pending);
+ return false;
+ }
+
+ sentinel = i915_request_has_sentinel(rq);
+ if (sentinel && port != execlists->pending) {
+ GEM_TRACE_ERR("sentinel context:%llx not in prime position[%zd]\n",
+ ce->timeline->fence_context,
+ port - execlists->pending);
+ return false;
+ }
+
/* Hold tightly onto the lock to prevent concurrent retires! */
if (!spin_trylock_irqsave(&rq->lock, flags))
continue;
--
2.25.1
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^ permalink raw reply related [flat|nested] 51+ messages in thread* [Intel-gfx] [PATCH 20/20] drm/i915/execlists: Reduce preempt-to-busy roundtrip delay
2020-02-27 8:57 [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits Chris Wilson
` (17 preceding siblings ...)
2020-02-27 8:57 ` [Intel-gfx] [PATCH 19/20] drm/i915/execlists: Check the sentinel is alone in the ELSP Chris Wilson
@ 2020-02-27 8:57 ` Chris Wilson
2020-02-27 9:14 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/20] drm/i915: Skip barriers inside waits Patchwork
` (6 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Chris Wilson @ 2020-02-27 8:57 UTC (permalink / raw)
To: intel-gfx
To prevent the context from proceeding past the end of the request as we
unwind, we embed a semaphore into the footer of each request. (If the
context were to skip past the end of the request as we perform the
preemption, next time we reload the context it's RING_HEAD would be past
the RING_TAIL and instead of replaying the commands it would read the
read of the uninitialised ringbuffer.)
However, this requires us to keep the ring paused at the end of the
request until we have a change to process the preemption ack and remove
the semaphore. Our processing of acks is at the whim of ksoftirqd, and
so it is entirely possible that the GPU has to wait for the tasklet
before it can proceed with the next request.
It was suggested that we could also embed a MI_LOAD_REGISTER_MEM into
the footer to read the current RING_TAIL from the context, which would
allow us to not only avoid this round trip (and so release the context
as soon as we had submitted the preemption request to in ELSP), but also
skip using ELSP for lite-restores entirely. That has the nice benefit of
dramatically reducing contention and the frequency of interrupts when a
client submits two or more execbufs in rapid succession.
* This did not work out quite as well as anticipated due to us reloading
the new RING_TAIL from the context image moments before the HW acted
upon the ELSP. With the calamitous effect that we would submit a
preemption request with an identical RING_TAIL as the current RING_HEAD,
causing us to fail WaIdleLiteRestore and the HW stop working.
However, mmio access to RING_TAIL was defeatured in gen11 so we can only
employ this handy trick for gen8/gen9.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 23 +++--
drivers/gpu/drm/i915/gt/intel_lrc.c | 93 +++++++++++++++++++-
2 files changed, 106 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 24cff658e6e5..ae8724915320 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -488,14 +488,15 @@ struct intel_engine_cs {
/* status_notifier: list of callbacks for context-switch changes */
struct atomic_notifier_head context_status_notifier;
-#define I915_ENGINE_USING_CMD_PARSER BIT(0)
-#define I915_ENGINE_SUPPORTS_STATS BIT(1)
-#define I915_ENGINE_HAS_PREEMPTION BIT(2)
-#define I915_ENGINE_HAS_SEMAPHORES BIT(3)
-#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(4)
-#define I915_ENGINE_IS_VIRTUAL BIT(5)
-#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
-#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
+#define I915_ENGINE_REQUIRES_CMD_PARSER BIT(0)
+#define I915_ENGINE_USING_CMD_PARSER BIT(1)
+#define I915_ENGINE_SUPPORTS_STATS BIT(2)
+#define I915_ENGINE_HAS_PREEMPTION BIT(3)
+#define I915_ENGINE_HAS_SEMAPHORES BIT(4)
+#define I915_ENGINE_HAS_TAIL_LRM BIT(5)
+#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(6)
+#define I915_ENGINE_IS_VIRTUAL BIT(7)
+#define I915_ENGINE_HAS_RELATIVE_MMIO BIT(8)
unsigned int flags;
/*
@@ -592,6 +593,12 @@ intel_engine_has_semaphores(const struct intel_engine_cs *engine)
return engine->flags & I915_ENGINE_HAS_SEMAPHORES;
}
+static inline bool
+intel_engine_has_tail_lrm(const struct intel_engine_cs *engine)
+{
+ return engine->flags & I915_ENGINE_HAS_TAIL_LRM;
+}
+
static inline bool
intel_engine_needs_breadcrumb_tasklet(const struct intel_engine_cs *engine)
{
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index d907b5ebc1a4..4452c3d0ac85 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1861,6 +1861,76 @@ static inline void clear_ports(struct i915_request **ports, int count)
memset_p((void **)ports, NULL, count);
}
+static struct i915_request *
+skip_lite_restore(struct intel_engine_cs *const engine,
+ struct i915_request *first,
+ bool *submit)
+{
+ struct intel_engine_execlists *const execlists = &engine->execlists;
+ struct i915_request *last = first;
+ struct rb_node *rb;
+
+ if (!intel_engine_has_tail_lrm(engine))
+ return last;
+
+ GEM_BUG_ON(*submit);
+ while ((rb = rb_first_cached(&execlists->queue))) {
+ struct i915_priolist *p = to_priolist(rb);
+ struct i915_request *rq, *rn;
+ int i;
+
+ priolist_for_each_request_consume(rq, rn, p, i) {
+ if (!can_merge_rq(last, rq))
+ goto out;
+
+ if (__i915_request_submit(rq)) {
+ *submit = true;
+ last = rq;
+ }
+ }
+
+ rb_erase_cached(&p->node, &execlists->queue);
+ i915_priolist_free(p);
+ }
+out:
+ if (*submit) {
+ ring_set_paused(engine, 1);
+
+ /*
+ * If we are quick and the current context hasn't yet completed
+ * its request, we can just tell it to extend the RING_TAIL
+ * onto the next without having to submit a new ELSP.
+ */
+ if (!i915_request_completed(first)) {
+ struct i915_request **port;
+
+ ENGINE_TRACE(engine,
+ "eliding lite-restore last=%llx:%lld->%lld, current %d\n",
+ first->fence.context,
+ first->fence.seqno,
+ last->fence.seqno,
+ hwsp_seqno(last));
+ GEM_BUG_ON(first->context != last->context);
+
+ for (port = (struct i915_request **)execlists->active;
+ *port != first;
+ port++)
+ ;
+
+ GEM_BUG_ON(first == last);
+ WRITE_ONCE(*port, i915_request_get(last));
+ execlists_update_context(last);
+
+ i915_request_put(first);
+ *submit = false;
+ }
+
+ ring_set_paused(engine, 0);
+ }
+
+ return last;
+}
+
static void execlists_dequeue(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
@@ -1998,6 +2068,8 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
return;
}
+
+ last = skip_lite_restore(engine, last, &submit);
}
}
@@ -4224,15 +4296,28 @@ static u32 *emit_preempt_busywait(struct i915_request *request, u32 *cs)
return cs;
}
+static u32 *emit_lrm_tail(struct i915_request *request, u32 *cs)
+{
+ *cs++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_USE_GGTT;
+ *cs++ = i915_mmio_reg_offset(RING_TAIL(request->engine->mmio_base));
+ *cs++ = i915_ggtt_offset(request->context->state) +
+ LRC_STATE_PN * PAGE_SIZE +
+ CTX_RING_TAIL * sizeof(u32);
+ *cs++ = 0;
+
+ return cs;
+}
+
static __always_inline u32*
-gen8_emit_fini_breadcrumb_footer(struct i915_request *request,
- u32 *cs)
+gen8_emit_fini_breadcrumb_footer(struct i915_request *request, u32 *cs)
{
*cs++ = MI_USER_INTERRUPT;
*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
if (intel_engine_has_semaphores(request->engine))
cs = emit_preempt_busywait(request, cs);
+ if (intel_engine_has_tail_lrm(request->engine))
+ cs = emit_lrm_tail(request, cs);
request->tail = intel_ring_offset(request, cs);
assert_ring_tail_valid(request->ring, request->tail);
@@ -4321,6 +4406,8 @@ static u32 *gen12_emit_preempt_busywait(struct i915_request *request, u32 *cs)
static __always_inline u32*
gen12_emit_fini_breadcrumb_footer(struct i915_request *request, u32 *cs)
{
+ GEM_BUG_ON(intel_engine_has_tail_lrm(request->engine));
+
*cs++ = MI_USER_INTERRUPT;
*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
@@ -4387,6 +4474,8 @@ void intel_execlists_set_default_submission(struct intel_engine_cs *engine)
engine->flags |= I915_ENGINE_HAS_SEMAPHORES;
if (HAS_LOGICAL_RING_PREEMPTION(engine->i915))
engine->flags |= I915_ENGINE_HAS_PREEMPTION;
+ if (INTEL_GEN(engine->i915) < 11)
+ engine->flags |= I915_ENGINE_HAS_TAIL_LRM;
}
if (INTEL_GEN(engine->i915) >= 12)
--
2.25.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 51+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/20] drm/i915: Skip barriers inside waits
2020-02-27 8:57 [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits Chris Wilson
` (18 preceding siblings ...)
2020-02-27 8:57 ` [Intel-gfx] [PATCH 20/20] drm/i915/execlists: Reduce preempt-to-busy roundtrip delay Chris Wilson
@ 2020-02-27 9:14 ` Patchwork
2020-02-27 9:45 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
` (5 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Patchwork @ 2020-02-27 9:14 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [01/20] drm/i915: Skip barriers inside waits
URL : https://patchwork.freedesktop.org/series/73999/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7e51c69c481c drm/i915: Skip barriers inside waits
c38fa802dbde drm/i915/perf: Mark up the racy use of perf->exclusive_stream
99d09399016d drm/i915/perf: Manually acquire engine-wakeref around use of kernel_context
620ed478d877 drm/i915/perf: Wait for lrc_reconfigure on disable
6ea5a0b4ac2e drm/i915/gem: Consolidate ctx->engines[] release
645f9d790e24 drm/i915/gt: Prevent allocation on a banned context
8139afa5553c drm/i915/gem: Check that the context wasn't closed during setup
ea172d1def13 drm/i915/selftests: Disable heartbeat around manual pulse tests
1e35652986b0 drm/i915/gt: Reset queue_priority_hint after wedging
-:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#12:
<0> [574.303565] i915_sel-6278 2.... 481822445us : __i915_subtests: Running intel_execlists_live_selftests/live_error_interrupt
total: 0 errors, 1 warnings, 0 checks, 10 lines checked
eb47d53f2699 drm/i915/gt: Pull marking vm as closed underneath the vm->mutex
-:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#12:
References: 00de702c6c6f ("drm/i915: Check that the vma hasn't been closed before we insert it")
-:12: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 00de702c6c6f ("drm/i915: Check that the vma hasn't been closed before we insert it")'
#12:
References: 00de702c6c6f ("drm/i915: Check that the vma hasn't been closed before we insert it")
total: 1 errors, 1 warnings, 0 checks, 26 lines checked
b4dae8ef2ab9 drm/i915: Protect i915_request_await_start from early waits
37b9d01ab40f drm/i915/selftests: Verify LRC isolation
-:449: WARNING:MEMORY_BARRIER: memory barrier without comment
#449: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:5179:
+ wmb();
total: 0 errors, 1 warnings, 0 checks, 557 lines checked
7c5ae8cee59f drm/i915/selftests: Check recovery from corrupted LRC
481fd56c20dc drm/i915/selftests: Wait for the kernel context switch
558c7595b054 drm/i915/selftests: Be a little more lenient for reset workers
e88a1a284017 drm/i915/selftests: Add request throughput measurement to perf
-:90: WARNING:LINE_SPACING: Missing a blank line after declarations
#90: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1515:
+ struct intel_context *ce;
+ IGT_TIMEOUT(end_time);
-:157: WARNING:LINE_SPACING: Missing a blank line after declarations
#157: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1582:
+ struct intel_context *ce;
+ IGT_TIMEOUT(end_time);
-:213: WARNING:LINE_SPACING: Missing a blank line after declarations
#213: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1638:
+ struct drm_i915_private *i915 = arg;
+ static int (* const func[])(void *arg) = {
-:221: WARNING:LINE_SPACING: Missing a blank line after declarations
#221: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1646:
+ struct intel_engine_cs *engine;
+ int (* const *fn)(void *arg);
-:263: WARNING:YIELD: Using yield() is generally wrong. See yield() kernel-doc (sched/core.c)
#263: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1688:
+ yield(); /* start all threads before we kthread_stop() */
total: 0 errors, 5 warnings, 0 checks, 301 lines checked
6dded72da559 drm/i915/gt: Declare when we enabled timeslicing
462b6fb118f9 drm/i915/gt: Yield the timeslice if caught waiting on a user semaphore
fff3931b5bef drm/i915/execlists: Check the sentinel is alone in the ELSP
109102637575 drm/i915/execlists: Reduce preempt-to-busy roundtrip delay
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 51+ messages in thread* [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [01/20] drm/i915: Skip barriers inside waits
2020-02-27 8:57 [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits Chris Wilson
` (19 preceding siblings ...)
2020-02-27 9:14 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/20] drm/i915: Skip barriers inside waits Patchwork
@ 2020-02-27 9:45 ` Patchwork
2020-02-27 15:06 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/20] drm/i915: Skip barriers inside waits (rev4) Patchwork
` (4 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Patchwork @ 2020-02-27 9:45 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [01/20] drm/i915: Skip barriers inside waits
URL : https://patchwork.freedesktop.org/series/73999/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8013 -> Patchwork_16729
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_16729 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_16729, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_16729:
### IGT changes ###
#### Possible regressions ####
* igt@core_auth@basic-auth:
- fi-kbl-r: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-kbl-r/igt@core_auth@basic-auth.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-kbl-r/igt@core_auth@basic-auth.html
- fi-bwr-2160: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-bwr-2160/igt@core_auth@basic-auth.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-bwr-2160/igt@core_auth@basic-auth.html
- fi-bdw-5557u: [PASS][5] -> [INCOMPLETE][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-bdw-5557u/igt@core_auth@basic-auth.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-bdw-5557u/igt@core_auth@basic-auth.html
- fi-skl-guc: [PASS][7] -> [INCOMPLETE][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-skl-guc/igt@core_auth@basic-auth.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-skl-guc/igt@core_auth@basic-auth.html
- fi-kbl-8809g: [PASS][9] -> [INCOMPLETE][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-kbl-8809g/igt@core_auth@basic-auth.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-kbl-8809g/igt@core_auth@basic-auth.html
- fi-kbl-guc: [PASS][11] -> [INCOMPLETE][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-kbl-guc/igt@core_auth@basic-auth.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-kbl-guc/igt@core_auth@basic-auth.html
- fi-icl-dsi: [PASS][13] -> [INCOMPLETE][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-icl-dsi/igt@core_auth@basic-auth.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-icl-dsi/igt@core_auth@basic-auth.html
- fi-kbl-7500u: [PASS][15] -> [INCOMPLETE][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-kbl-7500u/igt@core_auth@basic-auth.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-kbl-7500u/igt@core_auth@basic-auth.html
- fi-skl-6600u: [PASS][17] -> [INCOMPLETE][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-skl-6600u/igt@core_auth@basic-auth.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-skl-6600u/igt@core_auth@basic-auth.html
- fi-icl-u2: [PASS][19] -> [INCOMPLETE][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-icl-u2/igt@core_auth@basic-auth.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-icl-u2/igt@core_auth@basic-auth.html
- fi-hsw-4770: [PASS][21] -> [INCOMPLETE][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-hsw-4770/igt@core_auth@basic-auth.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-hsw-4770/igt@core_auth@basic-auth.html
- fi-cfl-8700k: [PASS][23] -> [INCOMPLETE][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-cfl-8700k/igt@core_auth@basic-auth.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-cfl-8700k/igt@core_auth@basic-auth.html
- fi-snb-2520m: [PASS][25] -> [INCOMPLETE][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-snb-2520m/igt@core_auth@basic-auth.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-snb-2520m/igt@core_auth@basic-auth.html
- fi-skl-lmem: [PASS][27] -> [INCOMPLETE][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-skl-lmem/igt@core_auth@basic-auth.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-skl-lmem/igt@core_auth@basic-auth.html
- fi-skl-6700k2: [PASS][29] -> [INCOMPLETE][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-skl-6700k2/igt@core_auth@basic-auth.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-skl-6700k2/igt@core_auth@basic-auth.html
- fi-ivb-3770: [PASS][31] -> [INCOMPLETE][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-ivb-3770/igt@core_auth@basic-auth.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-ivb-3770/igt@core_auth@basic-auth.html
- fi-cfl-guc: [PASS][33] -> [INCOMPLETE][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-cfl-guc/igt@core_auth@basic-auth.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-cfl-guc/igt@core_auth@basic-auth.html
- fi-icl-guc: [PASS][35] -> [INCOMPLETE][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-icl-guc/igt@core_auth@basic-auth.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-icl-guc/igt@core_auth@basic-auth.html
- fi-ilk-650: [PASS][37] -> [INCOMPLETE][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-ilk-650/igt@core_auth@basic-auth.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-ilk-650/igt@core_auth@basic-auth.html
- fi-kbl-soraka: [PASS][39] -> [INCOMPLETE][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-kbl-soraka/igt@core_auth@basic-auth.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-kbl-soraka/igt@core_auth@basic-auth.html
- fi-bsw-n3050: [PASS][41] -> [INCOMPLETE][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-bsw-n3050/igt@core_auth@basic-auth.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-bsw-n3050/igt@core_auth@basic-auth.html
- fi-hsw-peppy: [PASS][43] -> [INCOMPLETE][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-hsw-peppy/igt@core_auth@basic-auth.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-hsw-peppy/igt@core_auth@basic-auth.html
- fi-hsw-4770r: [PASS][45] -> [INCOMPLETE][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-hsw-4770r/igt@core_auth@basic-auth.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-hsw-4770r/igt@core_auth@basic-auth.html
- fi-kbl-x1275: [PASS][47] -> [INCOMPLETE][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-kbl-x1275/igt@core_auth@basic-auth.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-kbl-x1275/igt@core_auth@basic-auth.html
- fi-icl-y: [PASS][49] -> [INCOMPLETE][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-icl-y/igt@core_auth@basic-auth.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-icl-y/igt@core_auth@basic-auth.html
- fi-bsw-nick: [PASS][51] -> [INCOMPLETE][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-bsw-nick/igt@core_auth@basic-auth.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-bsw-nick/igt@core_auth@basic-auth.html
- fi-cfl-8109u: [PASS][53] -> [INCOMPLETE][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-cfl-8109u/igt@core_auth@basic-auth.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-cfl-8109u/igt@core_auth@basic-auth.html
- fi-blb-e6850: [PASS][55] -> [INCOMPLETE][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-blb-e6850/igt@core_auth@basic-auth.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-blb-e6850/igt@core_auth@basic-auth.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@core_auth@basic-auth:
- {fi-kbl-7560u}: NOTRUN -> [INCOMPLETE][57]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-kbl-7560u/igt@core_auth@basic-auth.html
- {fi-tgl-dsi}: [PASS][58] -> [INCOMPLETE][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-tgl-dsi/igt@core_auth@basic-auth.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-tgl-dsi/igt@core_auth@basic-auth.html
- {fi-tgl-u}: [PASS][60] -> [INCOMPLETE][61]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-tgl-u/igt@core_auth@basic-auth.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-tgl-u/igt@core_auth@basic-auth.html
- {fi-ehl-1}: [PASS][62] -> [INCOMPLETE][63]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-ehl-1/igt@core_auth@basic-auth.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-ehl-1/igt@core_auth@basic-auth.html
Known issues
------------
Here are the changes found in Patchwork_16729 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@core_auth@basic-auth:
- fi-byt-j1900: [PASS][64] -> [INCOMPLETE][65] ([i915#45])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-byt-j1900/igt@core_auth@basic-auth.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-byt-j1900/igt@core_auth@basic-auth.html
- fi-pnv-d510: [PASS][66] -> [INCOMPLETE][67] ([i915#299])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-pnv-d510/igt@core_auth@basic-auth.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-pnv-d510/igt@core_auth@basic-auth.html
- fi-apl-guc: [PASS][68] -> [INCOMPLETE][69] ([fdo#103927])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-apl-guc/igt@core_auth@basic-auth.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-apl-guc/igt@core_auth@basic-auth.html
- fi-cml-u2: [PASS][70] -> [INCOMPLETE][71] ([i915#283])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-cml-u2/igt@core_auth@basic-auth.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-cml-u2/igt@core_auth@basic-auth.html
- fi-bxt-dsi: [PASS][72] -> [INCOMPLETE][73] ([fdo#103927])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-bxt-dsi/igt@core_auth@basic-auth.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-bxt-dsi/igt@core_auth@basic-auth.html
- fi-byt-n2820: [PASS][74] -> [INCOMPLETE][75] ([i915#45])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-byt-n2820/igt@core_auth@basic-auth.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-byt-n2820/igt@core_auth@basic-auth.html
- fi-elk-e7500: [PASS][76] -> [INCOMPLETE][77] ([i915#66])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-elk-e7500/igt@core_auth@basic-auth.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-elk-e7500/igt@core_auth@basic-auth.html
- fi-cml-s: [PASS][78] -> [INCOMPLETE][79] ([i915#283])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-cml-s/igt@core_auth@basic-auth.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-cml-s/igt@core_auth@basic-auth.html
- fi-snb-2600: [PASS][80] -> [INCOMPLETE][81] ([i915#82])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-snb-2600/igt@core_auth@basic-auth.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-snb-2600/igt@core_auth@basic-auth.html
- fi-tgl-y: [PASS][82] -> [INCOMPLETE][83] ([CI#94])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-tgl-y/igt@core_auth@basic-auth.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-tgl-y/igt@core_auth@basic-auth.html
- fi-gdg-551: [PASS][84] -> [INCOMPLETE][85] ([i915#172])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-gdg-551/igt@core_auth@basic-auth.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-gdg-551/igt@core_auth@basic-auth.html
- fi-glk-dsi: [PASS][86] -> [INCOMPLETE][87] ([i915#58] / [k.org#198133])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8013/fi-glk-dsi/igt@core_auth@basic-auth.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/fi-glk-dsi/igt@core_auth@basic-auth.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[i915#172]: https://gitlab.freedesktop.org/drm/intel/issues/172
[i915#283]: https://gitlab.freedesktop.org/drm/intel/issues/283
[i915#299]: https://gitlab.freedesktop.org/drm/intel/issues/299
[i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45
[i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
[i915#66]: https://gitlab.freedesktop.org/drm/intel/issues/66
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (51 -> 45)
------------------------------
Additional (1): fi-kbl-7560u
Missing (7): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-bsw-kefka fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8013 -> Patchwork_16729
CI-20190529: 20190529
CI_DRM_8013: ddbaa8ebcf171da63385dccb8a6b4d0209c2f6fb @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5471: 668afe52887a164ee6a12fd1c898bc1c9086cf3e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16729: 1091026375756085f64dd88c011703d2b020be68 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
109102637575 drm/i915/execlists: Reduce preempt-to-busy roundtrip delay
fff3931b5bef drm/i915/execlists: Check the sentinel is alone in the ELSP
462b6fb118f9 drm/i915/gt: Yield the timeslice if caught waiting on a user semaphore
6dded72da559 drm/i915/gt: Declare when we enabled timeslicing
e88a1a284017 drm/i915/selftests: Add request throughput measurement to perf
558c7595b054 drm/i915/selftests: Be a little more lenient for reset workers
481fd56c20dc drm/i915/selftests: Wait for the kernel context switch
7c5ae8cee59f drm/i915/selftests: Check recovery from corrupted LRC
37b9d01ab40f drm/i915/selftests: Verify LRC isolation
b4dae8ef2ab9 drm/i915: Protect i915_request_await_start from early waits
eb47d53f2699 drm/i915/gt: Pull marking vm as closed underneath the vm->mutex
1e35652986b0 drm/i915/gt: Reset queue_priority_hint after wedging
ea172d1def13 drm/i915/selftests: Disable heartbeat around manual pulse tests
8139afa5553c drm/i915/gem: Check that the context wasn't closed during setup
645f9d790e24 drm/i915/gt: Prevent allocation on a banned context
6ea5a0b4ac2e drm/i915/gem: Consolidate ctx->engines[] release
620ed478d877 drm/i915/perf: Wait for lrc_reconfigure on disable
99d09399016d drm/i915/perf: Manually acquire engine-wakeref around use of kernel_context
c38fa802dbde drm/i915/perf: Mark up the racy use of perf->exclusive_stream
7e51c69c481c drm/i915: Skip barriers inside waits
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16729/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 51+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/20] drm/i915: Skip barriers inside waits (rev4)
2020-02-27 8:57 [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits Chris Wilson
` (20 preceding siblings ...)
2020-02-27 9:45 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2020-02-27 15:06 ` Patchwork
2020-02-27 15:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (3 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Patchwork @ 2020-02-27 15:06 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [01/20] drm/i915: Skip barriers inside waits (rev4)
URL : https://patchwork.freedesktop.org/series/73999/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ea6f01e92c61 drm/i915: Skip barriers inside waits
b03376b455cc drm/i915/perf: Mark up the racy use of perf->exclusive_stream
f20fed23b607 drm/i915/perf: Manually acquire engine-wakeref around use of kernel_context
98bae29ebe79 drm/i915/perf: Wait for lrc_reconfigure on disable
47888c782e0c drm/i915/gem: Consolidate ctx->engines[] release
94b9a31f328b drm/i915/gt: Prevent allocation on a banned context
68e1c6076e91 drm/i915/gem: Check that the context wasn't closed during setup
695b915be561 drm/i915/selftests: Disable heartbeat around manual pulse tests
03901330ffff drm/i915/gt: Reset queue_priority_hint after wedging
-:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#12:
<0> [574.303565] i915_sel-6278 2.... 481822445us : __i915_subtests: Running intel_execlists_live_selftests/live_error_interrupt
total: 0 errors, 1 warnings, 0 checks, 10 lines checked
19d8a9ec5a90 drm/i915/gt: Pull marking vm as closed underneath the vm->mutex
-:12: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#12:
References: 00de702c6c6f ("drm/i915: Check that the vma hasn't been closed before we insert it")
-:12: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 00de702c6c6f ("drm/i915: Check that the vma hasn't been closed before we insert it")'
#12:
References: 00de702c6c6f ("drm/i915: Check that the vma hasn't been closed before we insert it")
total: 1 errors, 1 warnings, 0 checks, 26 lines checked
d144797bcc6e drm/i915: Protect i915_request_await_start from early waits
0258eb86abee drm/i915/selftests: Verify LRC isolation
-:449: WARNING:MEMORY_BARRIER: memory barrier without comment
#449: FILE: drivers/gpu/drm/i915/gt/selftest_lrc.c:5179:
+ wmb();
total: 0 errors, 1 warnings, 0 checks, 557 lines checked
dac7e7aa2e04 drm/i915/selftests: Check recovery from corrupted LRC
097feb8cc312 drm/i915/selftests: Wait for the kernel context switch
f6ebc42863d7 drm/i915/selftests: Be a little more lenient for reset workers
cceba24157d6 drm/i915/selftests: Add request throughput measurement to perf
-:90: WARNING:LINE_SPACING: Missing a blank line after declarations
#90: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1515:
+ struct intel_context *ce;
+ IGT_TIMEOUT(end_time);
-:157: WARNING:LINE_SPACING: Missing a blank line after declarations
#157: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1582:
+ struct intel_context *ce;
+ IGT_TIMEOUT(end_time);
-:213: WARNING:LINE_SPACING: Missing a blank line after declarations
#213: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1638:
+ struct drm_i915_private *i915 = arg;
+ static int (* const func[])(void *arg) = {
-:221: WARNING:LINE_SPACING: Missing a blank line after declarations
#221: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1646:
+ struct intel_engine_cs *engine;
+ int (* const *fn)(void *arg);
-:263: WARNING:YIELD: Using yield() is generally wrong. See yield() kernel-doc (sched/core.c)
#263: FILE: drivers/gpu/drm/i915/selftests/i915_request.c:1688:
+ yield(); /* start all threads before we kthread_stop() */
total: 0 errors, 5 warnings, 0 checks, 301 lines checked
ad7bfc55d410 drm/i915/gt: Declare when we enabled timeslicing
9f8c2239da44 drm/i915/gt: Yield the timeslice if caught waiting on a user semaphore
8744e278c5f7 drm/i915/execlists: Check the sentinel is alone in the ELSP
720aff89c6c8 drm/i915/execlists: Reduce preempt-to-busy roundtrip delay
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 51+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/20] drm/i915: Skip barriers inside waits (rev4)
2020-02-27 8:57 [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits Chris Wilson
` (21 preceding siblings ...)
2020-02-27 15:06 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/20] drm/i915: Skip barriers inside waits (rev4) Patchwork
@ 2020-02-27 15:37 ` Patchwork
2020-02-27 22:38 ` [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits Andi Shyti
` (2 subsequent siblings)
25 siblings, 0 replies; 51+ messages in thread
From: Patchwork @ 2020-02-27 15:37 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [01/20] drm/i915: Skip barriers inside waits (rev4)
URL : https://patchwork.freedesktop.org/series/73999/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8018 -> Patchwork_16731
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_16731:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gt_lrc:
- {fi-tgl-dsi}: [DMESG-FAIL][1] ([i915#1233]) -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/fi-tgl-dsi/igt@i915_selftest@live@gt_lrc.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/fi-tgl-dsi/igt@i915_selftest@live@gt_lrc.html
- {fi-tgl-u}: [DMESG-FAIL][3] ([i915#1233]) -> [DMESG-FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/fi-tgl-u/igt@i915_selftest@live@gt_lrc.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/fi-tgl-u/igt@i915_selftest@live@gt_lrc.html
Known issues
------------
Here are the changes found in Patchwork_16731 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@gem_contexts:
- fi-cfl-8700k: [PASS][5] -> [INCOMPLETE][6] ([i915#424])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/fi-cfl-8700k/igt@i915_selftest@live@gem_contexts.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/fi-cfl-8700k/igt@i915_selftest@live@gem_contexts.html
#### Warnings ####
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][7] ([fdo#111096] / [i915#323]) -> [FAIL][8] ([fdo#111407])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[i915#1233]: https://gitlab.freedesktop.org/drm/intel/issues/1233
[i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
[i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424
Participating hosts (49 -> 43)
------------------------------
Additional (1): fi-byt-n2820
Missing (7): fi-ilk-m540 fi-byt-squawks fi-glk-dsi fi-bsw-cyan fi-ctg-p8600 fi-tgl-y fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8018 -> Patchwork_16731
CI-20190529: 20190529
CI_DRM_8018: d2d7fd43fafd159b7d9d957340e4ed9775ab20b0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5473: d22b3507ff2678a05d69d47c0ddf6f0e72ee7ffd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16731: 720aff89c6c8efa0deb0c662afc100e8a713db0a @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
720aff89c6c8 drm/i915/execlists: Reduce preempt-to-busy roundtrip delay
8744e278c5f7 drm/i915/execlists: Check the sentinel is alone in the ELSP
9f8c2239da44 drm/i915/gt: Yield the timeslice if caught waiting on a user semaphore
ad7bfc55d410 drm/i915/gt: Declare when we enabled timeslicing
cceba24157d6 drm/i915/selftests: Add request throughput measurement to perf
f6ebc42863d7 drm/i915/selftests: Be a little more lenient for reset workers
097feb8cc312 drm/i915/selftests: Wait for the kernel context switch
dac7e7aa2e04 drm/i915/selftests: Check recovery from corrupted LRC
0258eb86abee drm/i915/selftests: Verify LRC isolation
d144797bcc6e drm/i915: Protect i915_request_await_start from early waits
19d8a9ec5a90 drm/i915/gt: Pull marking vm as closed underneath the vm->mutex
03901330ffff drm/i915/gt: Reset queue_priority_hint after wedging
695b915be561 drm/i915/selftests: Disable heartbeat around manual pulse tests
68e1c6076e91 drm/i915/gem: Check that the context wasn't closed during setup
94b9a31f328b drm/i915/gt: Prevent allocation on a banned context
47888c782e0c drm/i915/gem: Consolidate ctx->engines[] release
98bae29ebe79 drm/i915/perf: Wait for lrc_reconfigure on disable
f20fed23b607 drm/i915/perf: Manually acquire engine-wakeref around use of kernel_context
b03376b455cc drm/i915/perf: Mark up the racy use of perf->exclusive_stream
ea6f01e92c61 drm/i915: Skip barriers inside waits
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits
2020-02-27 8:57 [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits Chris Wilson
` (22 preceding siblings ...)
2020-02-27 15:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-02-27 22:38 ` Andi Shyti
2020-02-28 11:53 ` Tvrtko Ursulin
2020-02-28 16:33 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/20] drm/i915: Skip barriers inside waits (rev4) Patchwork
25 siblings, 0 replies; 51+ messages in thread
From: Andi Shyti @ 2020-02-27 22:38 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
Hi Cris,
> Attaching to the i915_active barrier is a two stage process, and a flush
> is only effective when the barrier is activation. Thus it is possible
> for us to see a barrier, and attempt to flush, only for our flush to
> have no effect. As such, before attempting to activate signaling on the
> fence we need to double check it is a fence!
>
> Fixes: d13a31770077 ("drm/i915: Flush idle barriers when waiting")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@intel.com>
Andi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits
2020-02-27 8:57 [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits Chris Wilson
` (23 preceding siblings ...)
2020-02-27 22:38 ` [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits Andi Shyti
@ 2020-02-28 11:53 ` Tvrtko Ursulin
2020-02-28 12:08 ` Chris Wilson
2020-02-28 16:33 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/20] drm/i915: Skip barriers inside waits (rev4) Patchwork
25 siblings, 1 reply; 51+ messages in thread
From: Tvrtko Ursulin @ 2020-02-28 11:53 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 27/02/2020 08:57, Chris Wilson wrote:
> Attaching to the i915_active barrier is a two stage process, and a flush
> is only effective when the barrier is activation. Thus it is possible
> for us to see a barrier, and attempt to flush, only for our flush to
> have no effect. As such, before attempting to activate signaling on the
> fence we need to double check it is a fence!
>
> Fixes: d13a31770077 ("drm/i915: Flush idle barriers when waiting")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
> drivers/gpu/drm/i915/i915_active.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_active.c b/drivers/gpu/drm/i915/i915_active.c
> index 0b12d5023800..7b3d6c12ad61 100644
> --- a/drivers/gpu/drm/i915/i915_active.c
> +++ b/drivers/gpu/drm/i915/i915_active.c
> @@ -453,6 +453,9 @@ static void enable_signaling(struct i915_active_fence *active)
> {
> struct dma_fence *fence;
>
> + if (unlikely(is_barrier(active)))
> + return;
> +
> fence = i915_active_fence_get(active);
> if (!fence)
> return;
>
So that smp_rmb() is not really effective, I mean the race is wider than
that. I was worried about that.. now I need to figure out where it
starts and where it ends (the race).
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 51+ messages in thread* Re: [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits
2020-02-28 11:53 ` Tvrtko Ursulin
@ 2020-02-28 12:08 ` Chris Wilson
0 siblings, 0 replies; 51+ messages in thread
From: Chris Wilson @ 2020-02-28 12:08 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx
Quoting Tvrtko Ursulin (2020-02-28 11:53:19)
>
> On 27/02/2020 08:57, Chris Wilson wrote:
> > Attaching to the i915_active barrier is a two stage process, and a flush
> > is only effective when the barrier is activation. Thus it is possible
> > for us to see a barrier, and attempt to flush, only for our flush to
> > have no effect. As such, before attempting to activate signaling on the
> > fence we need to double check it is a fence!
> >
> > Fixes: d13a31770077 ("drm/i915: Flush idle barriers when waiting")
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_active.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_active.c b/drivers/gpu/drm/i915/i915_active.c
> > index 0b12d5023800..7b3d6c12ad61 100644
> > --- a/drivers/gpu/drm/i915/i915_active.c
> > +++ b/drivers/gpu/drm/i915/i915_active.c
> > @@ -453,6 +453,9 @@ static void enable_signaling(struct i915_active_fence *active)
> > {
> > struct dma_fence *fence;
> >
> > + if (unlikely(is_barrier(active)))
> > + return;
> > +
> > fence = i915_active_fence_get(active);
> > if (!fence)
> > return;
> >
>
> So that smp_rmb() is not really effective, I mean the race is wider than
> that. I was worried about that.. now I need to figure out where it
> starts and where it ends (the race).
That smp_rmb matches the update when we actually replace the barrier
with the fence. But, yes, the reuse_idle_barrier() has interesting
implications. There's no use after free and the iterator is technically
safe, but the flush isn't quite the flush I had hoped for.
-Chris
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 51+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [01/20] drm/i915: Skip barriers inside waits (rev4)
2020-02-27 8:57 [Intel-gfx] [PATCH 01/20] drm/i915: Skip barriers inside waits Chris Wilson
` (24 preceding siblings ...)
2020-02-28 11:53 ` Tvrtko Ursulin
@ 2020-02-28 16:33 ` Patchwork
25 siblings, 0 replies; 51+ messages in thread
From: Patchwork @ 2020-02-28 16:33 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [01/20] drm/i915: Skip barriers inside waits (rev4)
URL : https://patchwork.freedesktop.org/series/73999/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8018_full -> Patchwork_16731_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_16731_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_16731_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_16731_full:
### IGT changes ###
#### Possible regressions ####
* {igt@i915_selftest@perf@request} (NEW):
- shard-iclb: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-iclb2/igt@i915_selftest@perf@request.html
- shard-skl: NOTRUN -> [INCOMPLETE][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-skl1/igt@i915_selftest@perf@request.html
- shard-tglb: NOTRUN -> [INCOMPLETE][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-tglb7/igt@i915_selftest@perf@request.html
* {igt@i915_selftest@perf_request} (NEW):
- shard-iclb: NOTRUN -> [SKIP][4]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-iclb1/igt@i915_selftest@perf_request.html
* igt@runner@aborted:
- shard-tglb: NOTRUN -> [FAIL][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-tglb7/igt@runner@aborted.html
#### Warnings ####
* igt@i915_selftest@live@gt_lrc:
- shard-tglb: [DMESG-FAIL][6] ([i915#1233]) -> [DMESG-FAIL][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-tglb1/igt@i915_selftest@live@gt_lrc.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-tglb3/igt@i915_selftest@live@gt_lrc.html
New tests
---------
New tests have been introduced between CI_DRM_8018_full and Patchwork_16731_full:
### New IGT tests (6) ###
* igt@drm_mm@all:
- Statuses :
- Exec time: [None] s
* igt@i915_selftest@mock:
- Statuses :
- Exec time: [None] s
* igt@i915_selftest@perf:
- Statuses :
- Exec time: [None] s
* igt@i915_selftest@perf@request:
- Statuses : 7 incomplete(s)
- Exec time: [0.0] s
* igt@i915_selftest@perf_request:
- Statuses : 4 skip(s)
- Exec time: [0.0] s
* igt@kms_selftest@all:
- Statuses :
- Exec time: [None] s
Known issues
------------
Here are the changes found in Patchwork_16731_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-snb: [PASS][8] -> [FAIL][9] ([i915#1148])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-snb2/igt@gem_ctx_exec@basic-nohangcheck.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-snb2/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_persistence@close-replace-race:
- shard-kbl: [PASS][10] -> [INCOMPLETE][11] ([fdo#103665] / [i915#1291])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-kbl4/igt@gem_ctx_persistence@close-replace-race.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-kbl4/igt@gem_ctx_persistence@close-replace-race.html
* igt@gem_ctx_shared@exec-shared-gtt-bsd1:
- shard-tglb: [PASS][12] -> [FAIL][13] ([i915#616])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-tglb6/igt@gem_ctx_shared@exec-shared-gtt-bsd1.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-tglb1/igt@gem_ctx_shared@exec-shared-gtt-bsd1.html
* igt@gem_exec_schedule@implicit-read-write-bsd:
- shard-iclb: [PASS][14] -> [SKIP][15] ([i915#677])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-iclb6/igt@gem_exec_schedule@implicit-read-write-bsd.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-iclb1/igt@gem_exec_schedule@implicit-read-write-bsd.html
* igt@gem_exec_schedule@in-order-bsd:
- shard-iclb: [PASS][16] -> [SKIP][17] ([fdo#112146])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-iclb6/igt@gem_exec_schedule@in-order-bsd.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-iclb1/igt@gem_exec_schedule@in-order-bsd.html
* igt@i915_pm_rps@waitboost:
- shard-iclb: [PASS][18] -> [FAIL][19] ([i915#413])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-iclb2/igt@i915_pm_rps@waitboost.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-iclb6/igt@i915_pm_rps@waitboost.html
* igt@i915_selftest@live@hangcheck:
- shard-apl: [PASS][20] -> [INCOMPLETE][21] ([fdo#103927])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-apl7/igt@i915_selftest@live@hangcheck.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-apl3/igt@i915_selftest@live@hangcheck.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [PASS][22] -> [DMESG-WARN][23] ([i915#180])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-apl2/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@i915_suspend@forcewake:
- shard-kbl: [PASS][24] -> [DMESG-WARN][25] ([i915#180]) +1 similar issue
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-kbl3/igt@i915_suspend@forcewake.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-kbl2/igt@i915_suspend@forcewake.html
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled:
- shard-skl: [PASS][26] -> [FAIL][27] ([i915#52] / [i915#54])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-skl8/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-skl9/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-untiled.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-skl: [PASS][28] -> [INCOMPLETE][29] ([i915#69])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-skl7/igt@kms_fbcon_fbt@psr-suspend.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-skl5/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [PASS][30] -> [FAIL][31] ([i915#1188]) +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-skl10/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][32] -> [FAIL][33] ([fdo#108145])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-skl8/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [PASS][34] -> [SKIP][35] ([fdo#109441]) +2 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-iclb6/igt@kms_psr@psr2_primary_page_flip.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][36] -> [FAIL][37] ([i915#31])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-apl2/igt@kms_setmode@basic.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-apl6/igt@kms_setmode@basic.html
- shard-kbl: [PASS][38] -> [FAIL][39] ([i915#31])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-kbl2/igt@kms_setmode@basic.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-kbl3/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-b-query-forked-hang:
- shard-kbl: [PASS][40] -> [DMESG-WARN][41] ([i915#62] / [i915#92]) +5 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-kbl7/igt@kms_vblank@pipe-b-query-forked-hang.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-kbl6/igt@kms_vblank@pipe-b-query-forked-hang.html
* igt@perf_pmu@busy-accuracy-2-vcs1:
- shard-iclb: [PASS][42] -> [SKIP][43] ([fdo#112080]) +10 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-iclb2/igt@perf_pmu@busy-accuracy-2-vcs1.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-iclb6/igt@perf_pmu@busy-accuracy-2-vcs1.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [PASS][44] -> [SKIP][45] ([fdo#109276]) +23 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-iclb2/igt@prime_vgem@fence-wait-bsd2.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-iclb6/igt@prime_vgem@fence-wait-bsd2.html
#### Possible fixes ####
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [SKIP][46] ([fdo#110841]) -> [PASS][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-iclb2/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-iclb8/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_ctx_shared@q-independent-blt:
- shard-tglb: [FAIL][48] -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-tglb7/igt@gem_ctx_shared@q-independent-blt.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-tglb6/igt@gem_ctx_shared@q-independent-blt.html
* igt@gem_exec_balancer@hang:
- shard-tglb: [FAIL][50] ([i915#1277]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-tglb1/igt@gem_exec_balancer@hang.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-tglb3/igt@gem_exec_balancer@hang.html
* igt@gem_exec_parallel@vcs1-fds:
- shard-iclb: [SKIP][52] ([fdo#112080]) -> [PASS][53] +10 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-iclb6/igt@gem_exec_parallel@vcs1-fds.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-iclb1/igt@gem_exec_parallel@vcs1-fds.html
* igt@gem_exec_schedule@implicit-both-bsd1:
- shard-iclb: [SKIP][54] ([fdo#109276] / [i915#677]) -> [PASS][55] +2 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-iclb6/igt@gem_exec_schedule@implicit-both-bsd1.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-iclb1/igt@gem_exec_schedule@implicit-both-bsd1.html
* igt@gem_exec_schedule@pi-distinct-iova-bsd:
- shard-iclb: [SKIP][56] ([i915#677]) -> [PASS][57] +2 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-iclb2/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-iclb8/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [SKIP][58] ([fdo#112146]) -> [PASS][59] +6 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-iclb2/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-iclb6/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-apl: [FAIL][60] ([i915#644]) -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-apl6/igt@gem_ppgtt@flink-and-close-vma-leak.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-apl8/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@i915_suspend@fence-restore-untiled:
- shard-kbl: [DMESG-WARN][62] ([i915#180]) -> [PASS][63] +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-kbl3/igt@i915_suspend@fence-restore-untiled.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-kbl1/igt@i915_suspend@fence-restore-untiled.html
* igt@kms_cursor_crc@pipe-c-cursor-256x85-offscreen:
- shard-skl: [FAIL][64] ([i915#54]) -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-skl3/igt@kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-skl8/igt@kms_cursor_crc@pipe-c-cursor-256x85-offscreen.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [FAIL][66] ([fdo#108145]) -> [PASS][67]
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-skl9/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][68] ([fdo#109441]) -> [PASS][69] +4 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-iclb4/igt@kms_psr@psr2_no_drrs.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-apl: [DMESG-WARN][70] ([i915#180]) -> [PASS][71] +2 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-apl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-apl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [SKIP][72] ([fdo#109276]) -> [PASS][73] +15 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-iclb6/igt@prime_busy@hang-bsd2.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-iclb1/igt@prime_busy@hang-bsd2.html
#### Warnings ####
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [DMESG-WARN][74] ([i915#716]) -> [INCOMPLETE][75] ([i915#58] / [k.org#198133])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-glk9/igt@gen9_exec_parse@allowed-all.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-glk3/igt@gen9_exec_parse@allowed-all.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [SKIP][76] ([fdo#109349]) -> [DMESG-WARN][77] ([i915#1226])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-iclb4/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_flip@flip-vs-suspend:
- shard-kbl: [DMESG-WARN][78] ([i915#180]) -> [DMESG-WARN][79] ([i915#62] / [i915#92])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8018/shard-kbl2/igt@kms_flip@flip-vs-suspend.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/shard-kbl6/igt@kms_flip@flip-vs-suspend.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[i915#1148]: https://gitlab.freedesktop.org/drm/intel/issues/1148
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226
[i915#1233]: https://gitlab.freedesktop.org/drm/intel/issues/1233
[i915#1277]: https://gitlab.freedesktop.org/drm/intel/issues/1277
[i915#1291]: https://gitlab.freedesktop.org/drm/intel/issues/1291
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#413]: https://gitlab.freedesktop.org/drm/intel/issues/413
[i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
[i915#616]: https://gitlab.freedesktop.org/drm/intel/issues/616
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8018 -> Patchwork_16731
CI-20190529: 20190529
CI_DRM_8018: d2d7fd43fafd159b7d9d957340e4ed9775ab20b0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5473: d22b3507ff2678a05d69d47c0ddf6f0e72ee7ffd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16731: 720aff89c6c8efa0deb0c662afc100e8a713db0a @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16731/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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