From: Manasi Navare <manasi.d.navare@intel.com>
To: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v1 3/3] drm/i915: Remove unneeded hack now for CDCLK
Date: Mon, 16 Mar 2020 16:51:23 -0700 [thread overview]
Message-ID: <20200316235123.GB24231@intel.com> (raw)
In-Reply-To: <20200316113744.31203-4-stanislav.lisovskiy@intel.com>
On Mon, Mar 16, 2020 at 01:37:44PM +0200, Stanislav Lisovskiy wrote:
> No need to bump up CDCLK now, as it is now correctly
> calculated, accounting for DBuf BW as BSpec says.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Logic looks good,
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 12 ------------
> 1 file changed, 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index f0dcea4d6357..45469f6833b8 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2055,18 +2055,6 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> /* Account for additional needs from the planes */
> min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
>
> - /*
> - * HACK. Currently for TGL platforms we calculate
> - * min_cdclk initially based on pixel_rate divided
> - * by 2, accounting for also plane requirements,
> - * however in some cases the lowest possible CDCLK
> - * doesn't work and causing the underruns.
> - * Explicitly stating here that this seems to be currently
> - * rather a Hack, than final solution.
> - */
> - if (IS_TIGERLAKE(dev_priv))
> - min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);
> -
> /*
> * Similar story as with skl_write_plane_wm and intel_enable_sagv
> * - in some certain driver parts, we don't have any guarantee that
> --
> 2.24.1.485.gad05a3d8e5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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next prev parent reply other threads:[~2020-03-16 23:49 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-16 11:37 [Intel-gfx] [PATCH v1 0/3] Consider DBuf bandwidth when calculating CDCLK Stanislav Lisovskiy
2020-03-16 11:37 ` [Intel-gfx] [PATCH v1 1/3] drm/i915: Decouple cdclk calculation from modeset checks Stanislav Lisovskiy
2020-03-16 23:36 ` Manasi Navare
2020-03-17 13:21 ` Ville Syrjälä
2020-03-16 11:37 ` [Intel-gfx] [PATCH v1 2/3] drm/i915: Adjust CDCLK accordingly to our DBuf bw needs Stanislav Lisovskiy
2020-03-16 22:43 ` [Intel-gfx] [PATCH v2 " Stanislav Lisovskiy
2020-03-17 13:46 ` Ville Syrjälä
2020-03-17 14:40 ` Lisovskiy, Stanislav
2020-03-16 11:37 ` [Intel-gfx] [PATCH v1 3/3] drm/i915: Remove unneeded hack now for CDCLK Stanislav Lisovskiy
2020-03-16 23:51 ` Manasi Navare [this message]
2020-03-16 20:06 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Consider DBuf bandwidth when calculating CDCLK Patchwork
2020-03-16 20:34 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-03-17 0:36 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for Consider DBuf bandwidth when calculating CDCLK (rev2) Patchwork
2020-03-17 10:43 ` Lisovskiy, Stanislav
2020-03-18 8:33 ` Arkadiusz Hiler
2020-03-18 8:43 ` Lisovskiy, Stanislav
2020-03-18 8:55 ` Arkadiusz Hiler
2020-03-18 9:00 ` Lisovskiy, Stanislav
2020-03-17 0:56 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-03-17 9:26 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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