Re: [Intel-gfx] [PATCH v20 05/10] drm/i915: Extract gen specific functions from intel_can_enable_sagv

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Thu, Mar 26, 2020 at 08:10:00PM +0200, Stanislav Lisovskiy wrote:
> Addressing one of the comments, recommending to extract platform
> specific code from intel_can_enable_sagv as a preparation, before
> we are going to add support for tgl+.
> 
> Current code in intel_can_enable_sagv is valid only for skl,
> so this patch adds also proper support for icl, subsequent
> patches will add support for tgl+, combined with other required
> changes.
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 89 ++++++++++++++++++++++-----------
>  1 file changed, 61 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f8d62d1977ac..64193b098175 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3757,41 +3757,24 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
>  	return 0;
>  }
>  
> -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> +static bool icl_can_enable_sagv_on_pipe(struct intel_crtc_state *crtc_state)

icl_crtc_can_enable_sagv()/etc. would be more consistent with existing
practices. crtc_state can be const.

>  {
> -	struct drm_device *dev = state->base.dev;
> +	struct drm_device *dev = crtc_state->uapi.crtc->dev;

IMO just remove this 'dev' variable.

>  	struct drm_i915_private *dev_priv = to_i915(dev);
>  	struct intel_crtc *crtc;
>  	struct intel_plane *plane;
> -	struct intel_crtc_state *crtc_state;
> -	enum pipe pipe;
> +	struct intel_plane_state *plane_state;

const

>  	int level, latency;
>  
> -	if (!intel_has_sagv(dev_priv))
> -		return false;
> +	crtc = to_intel_crtc(crtc_state->uapi.crtc);

Initialize when declaring.

>  
> -	/*
> -	 * If there are no active CRTCs, no additional checks need be performed
> -	 */
> -	if (hweight8(state->active_pipes) == 0)
> -		return true;
> -
> -	/*
> -	 * SKL+ workaround: bspec recommends we disable SAGV when we have
> -	 * more then one pipe enabled
> -	 */
> -	if (hweight8(state->active_pipes) > 1)
> -		return false;
> -
> -	/* Since we're now guaranteed to only have one active CRTC... */
> -	pipe = ffs(state->active_pipes) - 1;
> -	crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> -	crtc_state = to_intel_crtc_state(crtc->base.state);

We seem to be missing a hw.active check.

> -
> -	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> +	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
> +		DRM_DEBUG_KMS("No SAGV for interlaced mode on pipe %c\n",
> +			      pipe_name(crtc->pipe));
>  		return false;
> +	}
>  
> -	for_each_intel_plane_on_crtc(dev, crtc, plane) {
> +	intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
>  		struct skl_plane_wm *wm =
>  			&crtc_state->wm.skl.optimal.planes[plane->id];
>  
> @@ -3807,7 +3790,7 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
>  		latency = dev_priv->wm.skl_latency[level];
>  
>  		if (skl_needs_memory_bw_wa(dev_priv) &&
> -		    plane->base.state->fb->modifier ==
> +		    plane_state->uapi.fb->modifier ==
>  		    I915_FORMAT_MOD_X_TILED)
>  			latency += 15;
>  
> @@ -3816,8 +3799,58 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
>  		 * incur memory latencies higher than sagv_block_time_us we
>  		 * can't enable SAGV.
>  		 */
> -		if (latency < dev_priv->sagv_block_time_us)
> +		if (latency < dev_priv->sagv_block_time_us) {
> +			DRM_DEBUG_KMS("Latency %d < sagv block time %d, no SAGV for pipe %c\n",
> +				      latency, dev_priv->sagv_block_time_us, pipe_name(crtc->pipe));
>  			return false;

How much noise will these debugs generate?

> +		}
> +	}
> +
> +	return true;
> +}
> +
> +static bool skl_can_enable_sagv_on_pipe(struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
> +
> +	/*
> +	 * It has been recommended that for Gen 9 we switch SAGV off when
> +	 * multiple pipes are used.
> +	 */
> +	if (hweight8(state->active_pipes) > 1)
> +		return false;
> +
> +	/*
> +	 * Besides active pipe limitation, rest of checks pretty much match ICL
> +	 * so no need to duplicate code
> +	 */
> +	return icl_can_enable_sagv_on_pipe(crtc_state);
> +}
> +
> +bool intel_can_enable_sagv(struct intel_atomic_state *state)
> +{
> +	struct drm_device *dev = state->base.dev;

Pls don't add needless 'dev' variables.

> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct intel_crtc *crtc;
> +	struct intel_crtc_state *crtc_state;

const

> +	int i;
> +
> +	if (!intel_has_sagv(dev_priv))
> +		return false;
> +
> +	/*
> +	 * If there are no active CRTCs, no additional checks need be performed
> +	 */
> +	if (hweight8(state->active_pipes) == 0)
> +		return true;

Seems pointless.

> +
> +	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {

Hmm. I think this is now temporarily busted since we only consider
the crtcs in the state. Would seem like we need to introduce the
sagv bitmaks first/at the same time as we do this.

> +		if (INTEL_GEN(dev_priv) <= 9) {
> +			if (!skl_can_enable_sagv_on_pipe(crtc_state))
> +				return false;
> +		} else if (!icl_can_enable_sagv_on_pipe(crtc_state)) {
> +			return false;
> +		}

Very hard to read if-else construct. Plase make it consistent for both
branches, and put the icl+ case first.

>  	}
>  
>  	return true;
> -- 
> 2.24.1.485.gad05a3d8e5

-- 
Ville Syrjälä
Intel
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