From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: jani.nikula@intel.com, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v20 08/10] drm/i915: Rename bw_state to new_bw_state
Date: Thu, 2 Apr 2020 20:30:29 +0300 [thread overview]
Message-ID: <20200402173029.GF13686@intel.com> (raw)
In-Reply-To: <20200326181005.11775-9-stanislav.lisovskiy@intel.com>
On Thu, Mar 26, 2020 at 08:10:03PM +0200, Stanislav Lisovskiy wrote:
> That is a preparation patch before next one where we
> introduce old_bw_state and a bunch of other changes
> as well.
> In a review comment it was suggested to split out
> at least that renaming into a separate patch, what
> is done here.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bw.c | 24 ++++++++++++------------
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index a8b2038db4d2..d16771dd2b10 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -418,7 +418,7 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_crtc_state *new_crtc_state, *old_crtc_state;
> - struct intel_bw_state *bw_state = NULL;
> + struct intel_bw_state *new_bw_state = NULL;
> unsigned int data_rate, max_data_rate;
> unsigned int num_active_planes;
> struct intel_crtc *crtc;
> @@ -447,29 +447,29 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
> old_active_planes == new_active_planes)
> continue;
>
> - bw_state = intel_atomic_get_bw_state(state);
> - if (IS_ERR(bw_state))
> - return PTR_ERR(bw_state);
> + new_bw_state = intel_atomic_get_bw_state(state);
^
Pls remove the spurious space while at it.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> + if (IS_ERR(new_bw_state))
> + return PTR_ERR(new_bw_state);
>
> - bw_state->data_rate[crtc->pipe] = new_data_rate;
> - bw_state->num_active_planes[crtc->pipe] = new_active_planes;
> + new_bw_state->data_rate[crtc->pipe] = new_data_rate;
> + new_bw_state->num_active_planes[crtc->pipe] = new_active_planes;
>
> drm_dbg_kms(&dev_priv->drm,
> "pipe %c data rate %u num active planes %u\n",
> pipe_name(crtc->pipe),
> - bw_state->data_rate[crtc->pipe],
> - bw_state->num_active_planes[crtc->pipe]);
> + new_bw_state->data_rate[crtc->pipe],
> + new_bw_state->num_active_planes[crtc->pipe]);
> }
>
> - if (!bw_state)
> + if (!new_bw_state)
> return 0;
>
> - ret = intel_atomic_lock_global_state(&bw_state->base);
> + ret = intel_atomic_lock_global_state(&new_bw_state->base);
> if (ret)
> return ret;
>
> - data_rate = intel_bw_data_rate(dev_priv, bw_state);
> - num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
> + data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
> + num_active_planes = intel_bw_num_active_planes(dev_priv, new_bw_state);
>
> max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
>
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
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next prev parent reply other threads:[~2020-04-02 17:30 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-26 18:09 [Intel-gfx] [PATCH v20 00/10] SAGV support for Gen12+ Stanislav Lisovskiy
2020-03-26 18:09 ` [Intel-gfx] [PATCH v20 01/10] drm/i915: Start passing latency as parameter Stanislav Lisovskiy
2020-03-26 18:09 ` [Intel-gfx] [PATCH v20 02/10] drm/i915: Eliminate magic numbers "0" and "1" from color plane Stanislav Lisovskiy
2020-04-02 16:17 ` Ville Syrjälä
2020-04-02 16:28 ` Lisovskiy, Stanislav
2020-04-02 16:41 ` Ville Syrjälä
2020-04-03 15:41 ` [Intel-gfx] [PATCH v21 " Stanislav Lisovskiy
2020-03-26 18:09 ` [Intel-gfx] [PATCH v20 03/10] drm/i915: Introduce skl_plane_wm_level accessor Stanislav Lisovskiy
2020-03-26 18:09 ` [Intel-gfx] [PATCH v20 04/10] drm/i915: Add intel_atomic_get_bw_*_state helpers Stanislav Lisovskiy
2020-04-02 16:20 ` Ville Syrjälä
2020-04-02 16:49 ` Ville Syrjälä
2020-04-03 6:11 ` [Intel-gfx] [PATCH v21 " Stanislav Lisovskiy
2020-04-03 6:15 ` Stanislav Lisovskiy
2020-03-26 18:10 ` [Intel-gfx] [PATCH v20 05/10] drm/i915: Extract gen specific functions from intel_can_enable_sagv Stanislav Lisovskiy
2020-04-02 16:44 ` Ville Syrjälä
2020-04-03 6:20 ` [Intel-gfx] [PATCH v21 " Stanislav Lisovskiy
2020-04-07 19:01 ` Ville Syrjälä
2020-04-08 7:58 ` Lisovskiy, Stanislav
2020-04-08 14:55 ` Ville Syrjälä
2020-04-08 15:54 ` Lisovskiy, Stanislav
2020-04-08 16:18 ` Lisovskiy, Stanislav
2020-04-09 15:58 ` Ville Syrjälä
2020-03-26 18:10 ` [Intel-gfx] [PATCH v20 06/10] drm/i915: Add proper SAGV support for TGL+ Stanislav Lisovskiy
2020-03-26 18:39 ` Stanislav Lisovskiy
2020-04-02 17:22 ` Ville Syrjälä
2020-04-03 6:29 ` [Intel-gfx] [PATCH v21 " Stanislav Lisovskiy
2020-04-03 15:43 ` Stanislav Lisovskiy
2020-03-26 18:10 ` [Intel-gfx] [PATCH v20 07/10] drm/i915: Added required new PCode commands Stanislav Lisovskiy
2020-04-02 17:27 ` Ville Syrjälä
2020-04-03 6:32 ` [Intel-gfx] [PATCH v21 " Stanislav Lisovskiy
2020-03-26 18:10 ` [Intel-gfx] [PATCH v20 08/10] drm/i915: Rename bw_state to new_bw_state Stanislav Lisovskiy
2020-04-02 17:30 ` Ville Syrjälä [this message]
2020-04-03 6:34 ` [Intel-gfx] [PATCH v21 " Stanislav Lisovskiy
2020-03-26 18:10 ` [Intel-gfx] [PATCH v20 09/10] drm/i915: Restrict qgv points which don't have enough bandwidth Stanislav Lisovskiy
2020-03-26 18:36 ` Stanislav Lisovskiy
2020-04-02 17:50 ` Ville Syrjälä
2020-04-03 6:37 ` [Intel-gfx] [PATCH v21 " Stanislav Lisovskiy
2020-04-03 16:41 ` Stanislav Lisovskiy
2020-03-26 18:10 ` [Intel-gfx] [PATCH v20 10/10] drm/i915: Enable SAGV support for Gen12 Stanislav Lisovskiy
2020-03-26 20:59 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for SAGV support for Gen12+ (rev3) Patchwork
2020-03-26 21:26 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-03-27 11:58 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-04-03 6:19 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for SAGV support for Gen12+ (rev4) Patchwork
2020-04-03 6:22 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for SAGV support for Gen12+ (rev5) Patchwork
2020-04-03 6:50 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for SAGV support for Gen12+ (rev10) Patchwork
2020-04-03 6:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-04-03 7:16 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-04-03 16:29 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for SAGV support for Gen12+ (rev12) Patchwork
2020-04-03 16:40 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for SAGV support for Gen12+ (rev10) Patchwork
2020-04-03 17:05 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for SAGV support for Gen12+ (rev13) Patchwork
2020-04-03 17:29 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-04-04 2:33 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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