[Intel-gfx] [PATCH v6 0/7] Asynchronous flip implementation for i915

[Intel-gfx] [PATCH v6 0/7] Asynchronous flip implementation for i915

[Karthik B S]

Without async flip support in the kernel, fullscreen apps where game
resolution is equal to the screen resolution, must perform an extra blit
per frame prior to flipping.

Asynchronous page flips will also boost the FPS of Mesa benchmarks.

v2: -Few patches have been squashed and patches have been shuffled as
     per the reviews on the previous version.

v3: -Few patches have been squashed and patches have been shuffled as
     per the reviews on the previous version.

v4: -Made changes to fix the sequence and time stamp issue as per the
     comments received on the previous version.
    -Timestamps are calculated using the flip done time stamp and current
     timestamp. Here I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP flag is used
     for timestamp calculations.
    -Event is sent from the interrupt handler immediately using this
     updated timestamps and sequence.
    -Added more state checks as async flip should only allow change in plane
     surface address and nothing else should be allowed to change.
    -Added a separate plane hook for async flip.
    -Need to find a way to reject fbc enabling if it comes as part of this
     flip as bspec states that changes to FBC are not allowed.

v5: -Fixed the Checkpatch and sparse warnings.

v6: -Reverted back to the old timestamping code as per the feedback received.
    -Added documentation.

Test-with: <20200806132935.23293-1-karthik.b.s@intel.com>

Karthik B S (7):
  drm/i915: Add enable/disable flip done and flip done handler
  drm/i915: Add support for async flips in I915
  drm/i915: Add checks specific to async flips
  drm/i915: Do not call drm_crtc_arm_vblank_event in async flips
  drm/i915: Add dedicated plane hook for async flip case
  Documentation/gpu: Add asynchronous flip documentation for i915
  drm/i915: Enable async flips in i915

 Documentation/gpu/i915.rst                   |   6 +
 drivers/gpu/drm/i915/display/intel_display.c | 127 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_sprite.c  |  33 ++++-
 drivers/gpu/drm/i915/i915_irq.c              |  52 ++++++++
 drivers/gpu/drm/i915/i915_irq.h              |   2 +
 drivers/gpu/drm/i915/i915_reg.h              |   1 +
 6 files changed, 220 insertions(+), 1 deletion(-)

-- 
2.22.0

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[Intel-gfx] [PATCH v6 1/7] drm/i915: Add enable/disable flip done and flip done handler

[Karthik B S]

Add enable/disable flip done functions and the flip done handler
function which handles the flip done interrupt.

Enable the flip done interrupt in IER.

Enable flip done function is called before writing the
surface address register as the write to this register triggers
the flip done interrupt

Flip done handler is used to send the page flip event as soon as the
surface address is written as per the requirement of async flips.
The interrupt is disabled after the event is sent.

v2: -Change function name from icl_* to skl_* (Paulo)
    -Move flip handler to this patch (Paulo)
    -Remove vblank_put() (Paulo)
    -Enable flip done interrupt for gen9+ only (Paulo)
    -Enable flip done interrupt in power_well_post_enable hook (Paulo)
    -Removed the event check in flip done handler to handle async
     flips without pageflip events.

v3: -Move skl_disable_flip_done out of interrupt handler (Paulo)
    -Make the pending vblank event NULL in the beginning of
     flip_done_handler to remove sporadic WARN_ON that is seen.

v4: -Calculate timestamps using flip done time stamp and current
     timestamp for async flips (Ville)

v5: -Fix the sparse warning by making the function 'g4x_get_flip_counter'
     static.(Reported-by: kernel test robot <lkp@intel.com>)
    -Fix the typo in commit message.

v6: -Revert back to old time stamping code.
    -Remove the break while calling skl_enable_flip_done. (Paulo)

Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c |  8 +++
 drivers/gpu/drm/i915/i915_irq.c              | 52 ++++++++++++++++++++
 drivers/gpu/drm/i915/i915_irq.h              |  2 +
 3 files changed, 62 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 522c772a2111..1ac2e6f27597 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15562,6 +15562,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 
 	intel_dbuf_pre_plane_update(state);
 
+	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+		if (new_crtc_state->uapi.async_flip)
+			skl_enable_flip_done(&crtc->base);
+	}
+
 	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
 	dev_priv->display.commit_modeset_enables(state);
 
@@ -15583,6 +15588,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	drm_atomic_helper_wait_for_flip_done(dev, &state->base);
 
 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+		if (new_crtc_state->uapi.async_flip)
+			skl_disable_flip_done(&crtc->base);
+
 		if (new_crtc_state->hw.active &&
 		    !needs_modeset(new_crtc_state) &&
 		    !new_crtc_state->preload_luts &&
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index f113fe44572b..6cc129b031d3 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1296,6 +1296,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
 			     u32 crc4) {}
 #endif
 
+static void flip_done_handler(struct drm_i915_private *dev_priv,
+			      unsigned int pipe)
+{
+	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
+	struct drm_crtc_state *crtc_state = crtc->base.state;
+	struct drm_pending_vblank_event *e = crtc_state->event;
+	struct drm_device *dev = &dev_priv->drm;
+	unsigned long irqflags;
+
+	spin_lock_irqsave(&dev->event_lock, irqflags);
+
+	crtc_state->event = NULL;
+
+	drm_crtc_send_vblank_event(&crtc->base, e);
+
+	spin_unlock_irqrestore(&dev->event_lock, irqflags);
+}
 
 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
 				     enum pipe pipe)
@@ -2390,6 +2407,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 		if (iir & GEN8_PIPE_VBLANK)
 			intel_handle_vblank(dev_priv, pipe);
 
+		if (iir & GEN9_PIPE_PLANE1_FLIP_DONE)
+			flip_done_handler(dev_priv, pipe);
+
 		if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
 			hsw_pipe_crc_irq_handler(dev_priv, pipe);
 
@@ -2711,6 +2731,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc)
 	return 0;
 }
 
+void skl_enable_flip_done(struct drm_crtc *crtc)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
+	unsigned long irqflags;
+
+	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+
+	bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
+
+	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
+
 /* Called from drm generic code, passed 'crtc' which
  * we use as a pipe index
  */
@@ -2771,6 +2804,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc)
 	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 }
 
+void skl_disable_flip_done(struct drm_crtc *crtc)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+	enum pipe pipe = to_intel_crtc(crtc)->pipe;
+	unsigned long irqflags;
+
+	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+
+	bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
+
+	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
+
 static void ibx_irq_reset(struct drm_i915_private *dev_priv)
 {
 	struct intel_uncore *uncore = &dev_priv->uncore;
@@ -2981,6 +3027,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 	u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
 	enum pipe pipe;
 
+	if (INTEL_GEN(dev_priv) >= 9)
+		extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE;
+
 	spin_lock_irq(&dev_priv->irq_lock);
 
 	if (!intel_irqs_enabled(dev_priv)) {
@@ -3459,6 +3508,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 	de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
 					   GEN8_PIPE_FIFO_UNDERRUN;
 
+	if (INTEL_GEN(dev_priv) >= 9)
+		de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE;
+
 	de_port_enables = de_port_masked;
 	if (IS_GEN9_LP(dev_priv))
 		de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
index 25f25cd95818..2f10c8135116 100644
--- a/drivers/gpu/drm/i915/i915_irq.h
+++ b/drivers/gpu/drm/i915/i915_irq.h
@@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc);
 int i965_enable_vblank(struct drm_crtc *crtc);
 int ilk_enable_vblank(struct drm_crtc *crtc);
 int bdw_enable_vblank(struct drm_crtc *crtc);
+void skl_enable_flip_done(struct drm_crtc *crtc);
 void i8xx_disable_vblank(struct drm_crtc *crtc);
 void i915gm_disable_vblank(struct drm_crtc *crtc);
 void i965_disable_vblank(struct drm_crtc *crtc);
 void ilk_disable_vblank(struct drm_crtc *crtc);
 void bdw_disable_vblank(struct drm_crtc *crtc);
+void skl_disable_flip_done(struct drm_crtc *crtc);
 
 void gen2_irq_reset(struct intel_uncore *uncore);
 void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
-- 
2.22.0

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Re: [Intel-gfx] [PATCH v6 1/7] drm/i915: Add enable/disable flip done and flip done handler

[Ville Syrjälä]

On Fri, Aug 07, 2020 at 03:05:45PM +0530, Karthik B S wrote:
> Add enable/disable flip done functions and the flip done handler
> function which handles the flip done interrupt.
> 
> Enable the flip done interrupt in IER.
> 
> Enable flip done function is called before writing the
> surface address register as the write to this register triggers
> the flip done interrupt
> 
> Flip done handler is used to send the page flip event as soon as the
> surface address is written as per the requirement of async flips.
> The interrupt is disabled after the event is sent.
> 
> v2: -Change function name from icl_* to skl_* (Paulo)
>     -Move flip handler to this patch (Paulo)
>     -Remove vblank_put() (Paulo)
>     -Enable flip done interrupt for gen9+ only (Paulo)
>     -Enable flip done interrupt in power_well_post_enable hook (Paulo)
>     -Removed the event check in flip done handler to handle async
>      flips without pageflip events.
> 
> v3: -Move skl_disable_flip_done out of interrupt handler (Paulo)
>     -Make the pending vblank event NULL in the beginning of
>      flip_done_handler to remove sporadic WARN_ON that is seen.
> 
> v4: -Calculate timestamps using flip done time stamp and current
>      timestamp for async flips (Ville)
> 
> v5: -Fix the sparse warning by making the function 'g4x_get_flip_counter'
>      static.(Reported-by: kernel test robot <lkp@intel.com>)
>     -Fix the typo in commit message.
> 
> v6: -Revert back to old time stamping code.
>     -Remove the break while calling skl_enable_flip_done. (Paulo)
> 
> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c |  8 +++
>  drivers/gpu/drm/i915/i915_irq.c              | 52 ++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_irq.h              |  2 +
>  3 files changed, 62 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 522c772a2111..1ac2e6f27597 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15562,6 +15562,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  
>  	intel_dbuf_pre_plane_update(state);
>  
> +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> +		if (new_crtc_state->uapi.async_flip)
> +			skl_enable_flip_done(&crtc->base);
> +	}
> +
>  	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
>  	dev_priv->display.commit_modeset_enables(state);
>  
> @@ -15583,6 +15588,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  	drm_atomic_helper_wait_for_flip_done(dev, &state->base);
>  
>  	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> +		if (new_crtc_state->uapi.async_flip)
> +			skl_disable_flip_done(&crtc->base);

Where do we wait for the flip done? Can't see such code anywhere.

> +
>  		if (new_crtc_state->hw.active &&
>  		    !needs_modeset(new_crtc_state) &&
>  		    !new_crtc_state->preload_luts &&
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index f113fe44572b..6cc129b031d3 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1296,6 +1296,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
>  			     u32 crc4) {}
>  #endif
>  
> +static void flip_done_handler(struct drm_i915_private *dev_priv,
> +			      unsigned int pipe)
> +{
> +	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> +	struct drm_crtc_state *crtc_state = crtc->base.state;
> +	struct drm_pending_vblank_event *e = crtc_state->event;
> +	struct drm_device *dev = &dev_priv->drm;
> +	unsigned long irqflags;
> +
> +	spin_lock_irqsave(&dev->event_lock, irqflags);
> +
> +	crtc_state->event = NULL;
> +
> +	drm_crtc_send_vblank_event(&crtc->base, e);
> +
> +	spin_unlock_irqrestore(&dev->event_lock, irqflags);
> +}
>  
>  static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
>  				     enum pipe pipe)
> @@ -2390,6 +2407,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
>  		if (iir & GEN8_PIPE_VBLANK)
>  			intel_handle_vblank(dev_priv, pipe);
>  
> +		if (iir & GEN9_PIPE_PLANE1_FLIP_DONE)
> +			flip_done_handler(dev_priv, pipe);
> +
>  		if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
>  			hsw_pipe_crc_irq_handler(dev_priv, pipe);
>  
> @@ -2711,6 +2731,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc)
>  	return 0;
>  }
>  
> +void skl_enable_flip_done(struct drm_crtc *crtc)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> +	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> +	unsigned long irqflags;
> +
> +	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> +
> +	bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
> +
> +	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> +}
> +
>  /* Called from drm generic code, passed 'crtc' which
>   * we use as a pipe index
>   */
> @@ -2771,6 +2804,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc)
>  	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>  }
>  
> +void skl_disable_flip_done(struct drm_crtc *crtc)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> +	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> +	unsigned long irqflags;
> +
> +	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> +
> +	bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
> +
> +	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> +}
> +
>  static void ibx_irq_reset(struct drm_i915_private *dev_priv)
>  {
>  	struct intel_uncore *uncore = &dev_priv->uncore;
> @@ -2981,6 +3027,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
>  	u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
>  	enum pipe pipe;
>  
> +	if (INTEL_GEN(dev_priv) >= 9)
> +		extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE;
> +
>  	spin_lock_irq(&dev_priv->irq_lock);
>  
>  	if (!intel_irqs_enabled(dev_priv)) {
> @@ -3459,6 +3508,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>  	de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
>  					   GEN8_PIPE_FIFO_UNDERRUN;
>  
> +	if (INTEL_GEN(dev_priv) >= 9)
> +		de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE;
> +
>  	de_port_enables = de_port_masked;
>  	if (IS_GEN9_LP(dev_priv))
>  		de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
> diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
> index 25f25cd95818..2f10c8135116 100644
> --- a/drivers/gpu/drm/i915/i915_irq.h
> +++ b/drivers/gpu/drm/i915/i915_irq.h
> @@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc);
>  int i965_enable_vblank(struct drm_crtc *crtc);
>  int ilk_enable_vblank(struct drm_crtc *crtc);
>  int bdw_enable_vblank(struct drm_crtc *crtc);
> +void skl_enable_flip_done(struct drm_crtc *crtc);
>  void i8xx_disable_vblank(struct drm_crtc *crtc);
>  void i915gm_disable_vblank(struct drm_crtc *crtc);
>  void i965_disable_vblank(struct drm_crtc *crtc);
>  void ilk_disable_vblank(struct drm_crtc *crtc);
>  void bdw_disable_vblank(struct drm_crtc *crtc);
> +void skl_disable_flip_done(struct drm_crtc *crtc);
>  
>  void gen2_irq_reset(struct intel_uncore *uncore);
>  void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
> -- 
> 2.22.0

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v6 1/7] drm/i915: Add enable/disable flip done and flip done handler

[Karthik B S]

On 9/1/2020 4:42 PM, Ville Syrjälä wrote:
> On Fri, Aug 07, 2020 at 03:05:45PM +0530, Karthik B S wrote:
>> Add enable/disable flip done functions and the flip done handler
>> function which handles the flip done interrupt.
>>
>> Enable the flip done interrupt in IER.
>>
>> Enable flip done function is called before writing the
>> surface address register as the write to this register triggers
>> the flip done interrupt
>>
>> Flip done handler is used to send the page flip event as soon as the
>> surface address is written as per the requirement of async flips.
>> The interrupt is disabled after the event is sent.
>>
>> v2: -Change function name from icl_* to skl_* (Paulo)
>>      -Move flip handler to this patch (Paulo)
>>      -Remove vblank_put() (Paulo)
>>      -Enable flip done interrupt for gen9+ only (Paulo)
>>      -Enable flip done interrupt in power_well_post_enable hook (Paulo)
>>      -Removed the event check in flip done handler to handle async
>>       flips without pageflip events.
>>
>> v3: -Move skl_disable_flip_done out of interrupt handler (Paulo)
>>      -Make the pending vblank event NULL in the beginning of
>>       flip_done_handler to remove sporadic WARN_ON that is seen.
>>
>> v4: -Calculate timestamps using flip done time stamp and current
>>       timestamp for async flips (Ville)
>>
>> v5: -Fix the sparse warning by making the function 'g4x_get_flip_counter'
>>       static.(Reported-by: kernel test robot <lkp@intel.com>)
>>      -Fix the typo in commit message.
>>
>> v6: -Revert back to old time stamping code.
>>      -Remove the break while calling skl_enable_flip_done. (Paulo)
>>
>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display.c |  8 +++
>>   drivers/gpu/drm/i915/i915_irq.c              | 52 ++++++++++++++++++++
>>   drivers/gpu/drm/i915/i915_irq.h              |  2 +
>>   3 files changed, 62 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 522c772a2111..1ac2e6f27597 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -15562,6 +15562,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>>   
>>   	intel_dbuf_pre_plane_update(state);
>>   
>> +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>> +		if (new_crtc_state->uapi.async_flip)
>> +			skl_enable_flip_done(&crtc->base);
>> +	}
>> +
>>   	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
>>   	dev_priv->display.commit_modeset_enables(state);
>>   
>> @@ -15583,6 +15588,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>>   	drm_atomic_helper_wait_for_flip_done(dev, &state->base);
>>   
>>   	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>> +		if (new_crtc_state->uapi.async_flip)
>> +			skl_disable_flip_done(&crtc->base);
> 
> Where do we wait for the flip done? Can't see such code anywhere.
> 

Thanks for the review.
My understanding is that drm_atomic_helper_wait_for_flip_done should 
take care of waiting for flip done.
Am I missing something? should there be a separate wait?

Thanks,
Karthik.B.S
>> +
>>   		if (new_crtc_state->hw.active &&
>>   		    !needs_modeset(new_crtc_state) &&
>>   		    !new_crtc_state->preload_luts &&
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> index f113fe44572b..6cc129b031d3 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -1296,6 +1296,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
>>   			     u32 crc4) {}
>>   #endif
>>   
>> +static void flip_done_handler(struct drm_i915_private *dev_priv,
>> +			      unsigned int pipe)
>> +{
>> +	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
>> +	struct drm_crtc_state *crtc_state = crtc->base.state;
>> +	struct drm_pending_vblank_event *e = crtc_state->event;
>> +	struct drm_device *dev = &dev_priv->drm;
>> +	unsigned long irqflags;
>> +
>> +	spin_lock_irqsave(&dev->event_lock, irqflags);
>> +
>> +	crtc_state->event = NULL;
>> +
>> +	drm_crtc_send_vblank_event(&crtc->base, e);
>> +
>> +	spin_unlock_irqrestore(&dev->event_lock, irqflags);
>> +}
>>   
>>   static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
>>   				     enum pipe pipe)
>> @@ -2390,6 +2407,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
>>   		if (iir & GEN8_PIPE_VBLANK)
>>   			intel_handle_vblank(dev_priv, pipe);
>>   
>> +		if (iir & GEN9_PIPE_PLANE1_FLIP_DONE)
>> +			flip_done_handler(dev_priv, pipe);
>> +
>>   		if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
>>   			hsw_pipe_crc_irq_handler(dev_priv, pipe);
>>   
>> @@ -2711,6 +2731,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc)
>>   	return 0;
>>   }
>>   
>> +void skl_enable_flip_done(struct drm_crtc *crtc)
>> +{
>> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>> +	enum pipe pipe = to_intel_crtc(crtc)->pipe;
>> +	unsigned long irqflags;
>> +
>> +	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
>> +
>> +	bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
>> +
>> +	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>> +}
>> +
>>   /* Called from drm generic code, passed 'crtc' which
>>    * we use as a pipe index
>>    */
>> @@ -2771,6 +2804,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc)
>>   	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>>   }
>>   
>> +void skl_disable_flip_done(struct drm_crtc *crtc)
>> +{
>> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>> +	enum pipe pipe = to_intel_crtc(crtc)->pipe;
>> +	unsigned long irqflags;
>> +
>> +	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
>> +
>> +	bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
>> +
>> +	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>> +}
>> +
>>   static void ibx_irq_reset(struct drm_i915_private *dev_priv)
>>   {
>>   	struct intel_uncore *uncore = &dev_priv->uncore;
>> @@ -2981,6 +3027,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
>>   	u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
>>   	enum pipe pipe;
>>   
>> +	if (INTEL_GEN(dev_priv) >= 9)
>> +		extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE;
>> +
>>   	spin_lock_irq(&dev_priv->irq_lock);
>>   
>>   	if (!intel_irqs_enabled(dev_priv)) {
>> @@ -3459,6 +3508,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>>   	de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
>>   					   GEN8_PIPE_FIFO_UNDERRUN;
>>   
>> +	if (INTEL_GEN(dev_priv) >= 9)
>> +		de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE;
>> +
>>   	de_port_enables = de_port_masked;
>>   	if (IS_GEN9_LP(dev_priv))
>>   		de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
>> diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
>> index 25f25cd95818..2f10c8135116 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.h
>> +++ b/drivers/gpu/drm/i915/i915_irq.h
>> @@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc);
>>   int i965_enable_vblank(struct drm_crtc *crtc);
>>   int ilk_enable_vblank(struct drm_crtc *crtc);
>>   int bdw_enable_vblank(struct drm_crtc *crtc);
>> +void skl_enable_flip_done(struct drm_crtc *crtc);
>>   void i8xx_disable_vblank(struct drm_crtc *crtc);
>>   void i915gm_disable_vblank(struct drm_crtc *crtc);
>>   void i965_disable_vblank(struct drm_crtc *crtc);
>>   void ilk_disable_vblank(struct drm_crtc *crtc);
>>   void bdw_disable_vblank(struct drm_crtc *crtc);
>> +void skl_disable_flip_done(struct drm_crtc *crtc);
>>   
>>   void gen2_irq_reset(struct intel_uncore *uncore);
>>   void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
>> -- 
>> 2.22.0
> 
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Re: [Intel-gfx] [PATCH v6 1/7] drm/i915: Add enable/disable flip done and flip done handler

[Ville Syrjälä]

On Fri, Aug 07, 2020 at 03:05:45PM +0530, Karthik B S wrote:
> Add enable/disable flip done functions and the flip done handler
> function which handles the flip done interrupt.
> 
> Enable the flip done interrupt in IER.
> 
> Enable flip done function is called before writing the
> surface address register as the write to this register triggers
> the flip done interrupt
> 
> Flip done handler is used to send the page flip event as soon as the
> surface address is written as per the requirement of async flips.
> The interrupt is disabled after the event is sent.
> 
> v2: -Change function name from icl_* to skl_* (Paulo)
>     -Move flip handler to this patch (Paulo)
>     -Remove vblank_put() (Paulo)
>     -Enable flip done interrupt for gen9+ only (Paulo)
>     -Enable flip done interrupt in power_well_post_enable hook (Paulo)
>     -Removed the event check in flip done handler to handle async
>      flips without pageflip events.
> 
> v3: -Move skl_disable_flip_done out of interrupt handler (Paulo)
>     -Make the pending vblank event NULL in the beginning of
>      flip_done_handler to remove sporadic WARN_ON that is seen.
> 
> v4: -Calculate timestamps using flip done time stamp and current
>      timestamp for async flips (Ville)
> 
> v5: -Fix the sparse warning by making the function 'g4x_get_flip_counter'
>      static.(Reported-by: kernel test robot <lkp@intel.com>)
>     -Fix the typo in commit message.
> 
> v6: -Revert back to old time stamping code.
>     -Remove the break while calling skl_enable_flip_done. (Paulo)
> 
> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c |  8 +++
>  drivers/gpu/drm/i915/i915_irq.c              | 52 ++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_irq.h              |  2 +
>  3 files changed, 62 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 522c772a2111..1ac2e6f27597 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15562,6 +15562,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  
>  	intel_dbuf_pre_plane_update(state);
>  
> +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> +		if (new_crtc_state->uapi.async_flip)
> +			skl_enable_flip_done(&crtc->base);
> +	}
> +
>  	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
>  	dev_priv->display.commit_modeset_enables(state);
>  
> @@ -15583,6 +15588,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  	drm_atomic_helper_wait_for_flip_done(dev, &state->base);
>  
>  	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> +		if (new_crtc_state->uapi.async_flip)
> +			skl_disable_flip_done(&crtc->base);
> +
>  		if (new_crtc_state->hw.active &&
>  		    !needs_modeset(new_crtc_state) &&
>  		    !new_crtc_state->preload_luts &&
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index f113fe44572b..6cc129b031d3 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1296,6 +1296,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
>  			     u32 crc4) {}
>  #endif
>  
> +static void flip_done_handler(struct drm_i915_private *dev_priv,
> +			      unsigned int pipe)
> +{
> +	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> +	struct drm_crtc_state *crtc_state = crtc->base.state;
> +	struct drm_pending_vblank_event *e = crtc_state->event;
> +	struct drm_device *dev = &dev_priv->drm;
> +	unsigned long irqflags;
> +
> +	spin_lock_irqsave(&dev->event_lock, irqflags);
> +
> +	crtc_state->event = NULL;
> +
> +	drm_crtc_send_vblank_event(&crtc->base, e);

The timestamp is going to be wrong here. We should perhaps just sample
the current time+frame counter here.

> +
> +	spin_unlock_irqrestore(&dev->event_lock, irqflags);
> +}
>  
>  static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
>  				     enum pipe pipe)
> @@ -2390,6 +2407,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
>  		if (iir & GEN8_PIPE_VBLANK)
>  			intel_handle_vblank(dev_priv, pipe);
>  
> +		if (iir & GEN9_PIPE_PLANE1_FLIP_DONE)
> +			flip_done_handler(dev_priv, pipe);
> +
>  		if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
>  			hsw_pipe_crc_irq_handler(dev_priv, pipe);
>  
> @@ -2711,6 +2731,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc)
>  	return 0;
>  }
>  
> +void skl_enable_flip_done(struct drm_crtc *crtc)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> +	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> +	unsigned long irqflags;
> +
> +	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> +
> +	bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
> +
> +	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> +}
> +
>  /* Called from drm generic code, passed 'crtc' which
>   * we use as a pipe index
>   */
> @@ -2771,6 +2804,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc)
>  	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>  }
>  
> +void skl_disable_flip_done(struct drm_crtc *crtc)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> +	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> +	unsigned long irqflags;
> +
> +	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> +
> +	bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
> +
> +	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> +}
> +
>  static void ibx_irq_reset(struct drm_i915_private *dev_priv)
>  {
>  	struct intel_uncore *uncore = &dev_priv->uncore;
> @@ -2981,6 +3027,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
>  	u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
>  	enum pipe pipe;
>  
> +	if (INTEL_GEN(dev_priv) >= 9)
> +		extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE;
> +
>  	spin_lock_irq(&dev_priv->irq_lock);
>  
>  	if (!intel_irqs_enabled(dev_priv)) {
> @@ -3459,6 +3508,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>  	de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
>  					   GEN8_PIPE_FIFO_UNDERRUN;
>  
> +	if (INTEL_GEN(dev_priv) >= 9)
> +		de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE;
> +
>  	de_port_enables = de_port_masked;
>  	if (IS_GEN9_LP(dev_priv))
>  		de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
> diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
> index 25f25cd95818..2f10c8135116 100644
> --- a/drivers/gpu/drm/i915/i915_irq.h
> +++ b/drivers/gpu/drm/i915/i915_irq.h
> @@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc);
>  int i965_enable_vblank(struct drm_crtc *crtc);
>  int ilk_enable_vblank(struct drm_crtc *crtc);
>  int bdw_enable_vblank(struct drm_crtc *crtc);
> +void skl_enable_flip_done(struct drm_crtc *crtc);
>  void i8xx_disable_vblank(struct drm_crtc *crtc);
>  void i915gm_disable_vblank(struct drm_crtc *crtc);
>  void i965_disable_vblank(struct drm_crtc *crtc);
>  void ilk_disable_vblank(struct drm_crtc *crtc);
>  void bdw_disable_vblank(struct drm_crtc *crtc);
> +void skl_disable_flip_done(struct drm_crtc *crtc);
>  
>  void gen2_irq_reset(struct intel_uncore *uncore);
>  void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
> -- 
> 2.22.0

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v6 1/7] drm/i915: Add enable/disable flip done and flip done handler

[Karthik B S]

On 9/1/2020 5:10 PM, Ville Syrjälä wrote:
> On Fri, Aug 07, 2020 at 03:05:45PM +0530, Karthik B S wrote:
>> Add enable/disable flip done functions and the flip done handler
>> function which handles the flip done interrupt.
>>
>> Enable the flip done interrupt in IER.
>>
>> Enable flip done function is called before writing the
>> surface address register as the write to this register triggers
>> the flip done interrupt
>>
>> Flip done handler is used to send the page flip event as soon as the
>> surface address is written as per the requirement of async flips.
>> The interrupt is disabled after the event is sent.
>>
>> v2: -Change function name from icl_* to skl_* (Paulo)
>>      -Move flip handler to this patch (Paulo)
>>      -Remove vblank_put() (Paulo)
>>      -Enable flip done interrupt for gen9+ only (Paulo)
>>      -Enable flip done interrupt in power_well_post_enable hook (Paulo)
>>      -Removed the event check in flip done handler to handle async
>>       flips without pageflip events.
>>
>> v3: -Move skl_disable_flip_done out of interrupt handler (Paulo)
>>      -Make the pending vblank event NULL in the beginning of
>>       flip_done_handler to remove sporadic WARN_ON that is seen.
>>
>> v4: -Calculate timestamps using flip done time stamp and current
>>       timestamp for async flips (Ville)
>>
>> v5: -Fix the sparse warning by making the function 'g4x_get_flip_counter'
>>       static.(Reported-by: kernel test robot <lkp@intel.com>)
>>      -Fix the typo in commit message.
>>
>> v6: -Revert back to old time stamping code.
>>      -Remove the break while calling skl_enable_flip_done. (Paulo)
>>
>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display.c |  8 +++
>>   drivers/gpu/drm/i915/i915_irq.c              | 52 ++++++++++++++++++++
>>   drivers/gpu/drm/i915/i915_irq.h              |  2 +
>>   3 files changed, 62 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 522c772a2111..1ac2e6f27597 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -15562,6 +15562,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>>   
>>   	intel_dbuf_pre_plane_update(state);
>>   
>> +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>> +		if (new_crtc_state->uapi.async_flip)
>> +			skl_enable_flip_done(&crtc->base);
>> +	}
>> +
>>   	/* Now enable the clocks, plane, pipe, and connectors that we set up. */
>>   	dev_priv->display.commit_modeset_enables(state);
>>   
>> @@ -15583,6 +15588,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>>   	drm_atomic_helper_wait_for_flip_done(dev, &state->base);
>>   
>>   	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>> +		if (new_crtc_state->uapi.async_flip)
>> +			skl_disable_flip_done(&crtc->base);
>> +
>>   		if (new_crtc_state->hw.active &&
>>   		    !needs_modeset(new_crtc_state) &&
>>   		    !new_crtc_state->preload_luts &&
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> index f113fe44572b..6cc129b031d3 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -1296,6 +1296,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
>>   			     u32 crc4) {}
>>   #endif
>>   
>> +static void flip_done_handler(struct drm_i915_private *dev_priv,
>> +			      unsigned int pipe)
>> +{
>> +	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
>> +	struct drm_crtc_state *crtc_state = crtc->base.state;
>> +	struct drm_pending_vblank_event *e = crtc_state->event;
>> +	struct drm_device *dev = &dev_priv->drm;
>> +	unsigned long irqflags;
>> +
>> +	spin_lock_irqsave(&dev->event_lock, irqflags);
>> +
>> +	crtc_state->event = NULL;
>> +
>> +	drm_crtc_send_vblank_event(&crtc->base, e);
> 
> The timestamp is going to be wrong here. We should perhaps just sample
> the current time+frame counter here.
> 

Thanks for the review.
Tried updating the proper timestamp in the previous version(V5) of the 
series by using flip timestamp. Feeback received was that userspace 
doesn't use this.Also trying to align to the current AMD implementation, 
where the timestamp corresponds to the previous vblank timestamp.

In V5, we had tried by updating the sequence(by using flip counter), but 
the feedback received was that the sequence shouldn't change and it 
should always reflect the frame counter.Thus, in our current 
implementation we do not make any changes to the sequence.So, even if 
there is any update in time stamp it doesn't get reflected, even after 
calling drm_update_vblank_count.

As userspace is not interested in this (as per the previous mail 
discussions, I've updated the kernel documentation also with this 
detail), should we implement this?

Thanks,
Karthik.B.S
>> +
>> +	spin_unlock_irqrestore(&dev->event_lock, irqflags);
>> +}
>>   
>>   static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
>>   				     enum pipe pipe)
>> @@ -2390,6 +2407,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
>>   		if (iir & GEN8_PIPE_VBLANK)
>>   			intel_handle_vblank(dev_priv, pipe);
>>   
>> +		if (iir & GEN9_PIPE_PLANE1_FLIP_DONE)
>> +			flip_done_handler(dev_priv, pipe);
>> +
>>   		if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
>>   			hsw_pipe_crc_irq_handler(dev_priv, pipe);
>>   
>> @@ -2711,6 +2731,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc)
>>   	return 0;
>>   }
>>   
>> +void skl_enable_flip_done(struct drm_crtc *crtc)
>> +{
>> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>> +	enum pipe pipe = to_intel_crtc(crtc)->pipe;
>> +	unsigned long irqflags;
>> +
>> +	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
>> +
>> +	bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
>> +
>> +	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>> +}
>> +
>>   /* Called from drm generic code, passed 'crtc' which
>>    * we use as a pipe index
>>    */
>> @@ -2771,6 +2804,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc)
>>   	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>>   }
>>   
>> +void skl_disable_flip_done(struct drm_crtc *crtc)
>> +{
>> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>> +	enum pipe pipe = to_intel_crtc(crtc)->pipe;
>> +	unsigned long irqflags;
>> +
>> +	spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
>> +
>> +	bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
>> +
>> +	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>> +}
>> +
>>   static void ibx_irq_reset(struct drm_i915_private *dev_priv)
>>   {
>>   	struct intel_uncore *uncore = &dev_priv->uncore;
>> @@ -2981,6 +3027,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
>>   	u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
>>   	enum pipe pipe;
>>   
>> +	if (INTEL_GEN(dev_priv) >= 9)
>> +		extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE;
>> +
>>   	spin_lock_irq(&dev_priv->irq_lock);
>>   
>>   	if (!intel_irqs_enabled(dev_priv)) {
>> @@ -3459,6 +3508,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>>   	de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
>>   					   GEN8_PIPE_FIFO_UNDERRUN;
>>   
>> +	if (INTEL_GEN(dev_priv) >= 9)
>> +		de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE;
>> +
>>   	de_port_enables = de_port_masked;
>>   	if (IS_GEN9_LP(dev_priv))
>>   		de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
>> diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
>> index 25f25cd95818..2f10c8135116 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.h
>> +++ b/drivers/gpu/drm/i915/i915_irq.h
>> @@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc);
>>   int i965_enable_vblank(struct drm_crtc *crtc);
>>   int ilk_enable_vblank(struct drm_crtc *crtc);
>>   int bdw_enable_vblank(struct drm_crtc *crtc);
>> +void skl_enable_flip_done(struct drm_crtc *crtc);
>>   void i8xx_disable_vblank(struct drm_crtc *crtc);
>>   void i915gm_disable_vblank(struct drm_crtc *crtc);
>>   void i965_disable_vblank(struct drm_crtc *crtc);
>>   void ilk_disable_vblank(struct drm_crtc *crtc);
>>   void bdw_disable_vblank(struct drm_crtc *crtc);
>> +void skl_disable_flip_done(struct drm_crtc *crtc);
>>   
>>   void gen2_irq_reset(struct intel_uncore *uncore);
>>   void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
>> -- 
>> 2.22.0
> 
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[Intel-gfx] [PATCH v6 2/7] drm/i915: Add support for async flips in I915

[Karthik B S]

Set the Async Address Update Enable bit in plane ctl
when async flip is requested.

v2: -Move the Async flip enablement to individual patch (Paulo)

v3: -Rebased.

v4: -Add separate plane hook for async flip case (Ville)

v5: -Rebased.

v6: -Move the plane hook to separate patch. (Paulo)
    -Remove the early return in skl_plane_ctl. (Paulo)

Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 3 +++
 drivers/gpu/drm/i915/i915_reg.h              | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1ac2e6f27597..ce2b0c14a073 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4768,6 +4768,9 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
 
 	plane_ctl = PLANE_CTL_ENABLE;
 
+	if (crtc_state->uapi.async_flip)
+		plane_ctl |= PLANE_CTL_ASYNC_FLIP;
+
 	if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
 		plane_ctl |= skl_plane_ctl_alpha(plane_state);
 		plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e85c6fc1f3cb..3f88d9ac90a8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6924,6 +6924,7 @@ enum {
 #define   PLANE_CTL_TILED_X			(1 << 10)
 #define   PLANE_CTL_TILED_Y			(4 << 10)
 #define   PLANE_CTL_TILED_YF			(5 << 10)
+#define   PLANE_CTL_ASYNC_FLIP			(1 << 9)
 #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
 #define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
 #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */
-- 
2.22.0

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Re: [Intel-gfx] [PATCH v6 2/7] drm/i915: Add support for async flips in I915

[Ville Syrjälä]

On Fri, Aug 07, 2020 at 03:05:46PM +0530, Karthik B S wrote:
> Set the Async Address Update Enable bit in plane ctl
> when async flip is requested.
> 
> v2: -Move the Async flip enablement to individual patch (Paulo)
> 
> v3: -Rebased.
> 
> v4: -Add separate plane hook for async flip case (Ville)
> 
> v5: -Rebased.
> 
> v6: -Move the plane hook to separate patch. (Paulo)
>     -Remove the early return in skl_plane_ctl. (Paulo)
> 
> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 3 +++
>  drivers/gpu/drm/i915/i915_reg.h              | 1 +
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 1ac2e6f27597..ce2b0c14a073 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4768,6 +4768,9 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
>  
>  	plane_ctl = PLANE_CTL_ENABLE;
>  
> +	if (crtc_state->uapi.async_flip)
> +		plane_ctl |= PLANE_CTL_ASYNC_FLIP;

Hmm. We might want to put that into skl_plane_ctl_crtc() since it's
a crtc-wide thing,

> +
>  	if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
>  		plane_ctl |= skl_plane_ctl_alpha(plane_state);
>  		plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e85c6fc1f3cb..3f88d9ac90a8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6924,6 +6924,7 @@ enum {
>  #define   PLANE_CTL_TILED_X			(1 << 10)
>  #define   PLANE_CTL_TILED_Y			(4 << 10)
>  #define   PLANE_CTL_TILED_YF			(5 << 10)
> +#define   PLANE_CTL_ASYNC_FLIP			(1 << 9)
>  #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
>  #define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
>  #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */
> -- 
> 2.22.0

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v6 2/7] drm/i915: Add support for async flips in I915

[Karthik B S]

On 9/1/2020 4:45 PM, Ville Syrjälä wrote:
> On Fri, Aug 07, 2020 at 03:05:46PM +0530, Karthik B S wrote:
>> Set the Async Address Update Enable bit in plane ctl
>> when async flip is requested.
>>
>> v2: -Move the Async flip enablement to individual patch (Paulo)
>>
>> v3: -Rebased.
>>
>> v4: -Add separate plane hook for async flip case (Ville)
>>
>> v5: -Rebased.
>>
>> v6: -Move the plane hook to separate patch. (Paulo)
>>      -Remove the early return in skl_plane_ctl. (Paulo)
>>
>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display.c | 3 +++
>>   drivers/gpu/drm/i915/i915_reg.h              | 1 +
>>   2 files changed, 4 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 1ac2e6f27597..ce2b0c14a073 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -4768,6 +4768,9 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
>>   
>>   	plane_ctl = PLANE_CTL_ENABLE;
>>   
>> +	if (crtc_state->uapi.async_flip)
>> +		plane_ctl |= PLANE_CTL_ASYNC_FLIP;
> 
> Hmm. We might want to put that into skl_plane_ctl_crtc() since it's
> a crtc-wide thing,
> 

Thanks for the review.
Sure, I'll move this.

Thanks,
Karthik.B.S
>> +
>>   	if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
>>   		plane_ctl |= skl_plane_ctl_alpha(plane_state);
>>   		plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index e85c6fc1f3cb..3f88d9ac90a8 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -6924,6 +6924,7 @@ enum {
>>   #define   PLANE_CTL_TILED_X			(1 << 10)
>>   #define   PLANE_CTL_TILED_Y			(4 << 10)
>>   #define   PLANE_CTL_TILED_YF			(5 << 10)
>> +#define   PLANE_CTL_ASYNC_FLIP			(1 << 9)
>>   #define   PLANE_CTL_FLIP_HORIZONTAL		(1 << 8)
>>   #define   PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE	(1 << 4) /* TGL+ */
>>   #define   PLANE_CTL_ALPHA_MASK			(0x3 << 4) /* Pre-GLK */
>> -- 
>> 2.22.0
> 
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[Intel-gfx] [PATCH v6 3/7] drm/i915: Add checks specific to async flips

[Karthik B S]

If flip is requested on any other plane, reject it.

Make sure there is no change in fbc, offset and framebuffer modifiers
when async flip is requested.

If any of these are modified, reject async flip.

v2: -Replace DRM_ERROR (Paulo)
    -Add check for changes in OFFSET, FBC, RC(Paulo)

v3: -Removed TODO as benchmarking tests have been run now.

v4: -Added more state checks for async flip (Ville)
    -Moved intel_atomic_check_async to the end of intel_atomic_check
     as the plane checks needs to pass before this. (Ville)
    -Removed crtc_state->enable_fbc check. (Ville)
    -Set the I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP flag for async
     flip case as scanline counter is not reliable here.

v5: -Fix typo and other check patch errors seen in CI
     in 'intel_atomic_check_async' function.

v6: -Don't call intel_atomic_check_async multiple times. (Ville)
    -Remove the check for n_planes in intel_atomic_check_async
    -Added documentation for async flips. (Paulo)

Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 113 +++++++++++++++++++
 1 file changed, 113 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ce2b0c14a073..9629c751d2af 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14832,6 +14832,110 @@ static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
 	return false;
 }
 
+/**
+ * DOC: asynchronous flip implementation
+ *
+ * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
+ * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
+ * Correspondingly, support is currently added for primary plane only.
+ *
+ * Async flip can only change the plane surface address, so anything else
+ * changing is rejected from the intel_atomic_check_async() function.
+ * Once this check is cleared, flip done interrupt is enabled using
+ * the skl_enable_flip_done() function.
+ *
+ * As soon as the surface address register is written, flip done interrupt is
+ * generated and the requested events are sent to the usersapce in the interrupt
+ * handler itself. The timestamp and sequence sent during the flip done event
+ * correspond to the last vblank and have no relation to the actual time when
+ * the flip done event was sent.
+ */
+
+static int intel_atomic_check_async(struct intel_atomic_state *state)
+{
+	struct intel_crtc_state *old_crtc_state, *new_crtc_state;
+	struct intel_plane_state *new_plane_state, *old_plane_state;
+	struct intel_crtc *crtc;
+	struct intel_plane *intel_plane;
+	int i;
+
+	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+					    new_crtc_state, i) {
+		if (needs_modeset(new_crtc_state)) {
+			DRM_DEBUG_KMS("Modeset Required. Async flip not supported\n");
+			return -EINVAL;
+		}
+
+		if (!new_crtc_state->uapi.active) {
+			DRM_DEBUG_KMS("CRTC inactive\n");
+			return -EINVAL;
+		}
+		if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
+			DRM_DEBUG_KMS("Active planes cannot be changed during async flip\n");
+			return -EINVAL;
+		}
+	}
+
+	for_each_oldnew_intel_plane_in_state(state, intel_plane, old_plane_state,
+					     new_plane_state, i) {
+		/*TODO: Async flip is only supported through the page flip IOCTL
+		 * as of now. So support currently added for primary plane only.
+		 * Support for other planes should be added when async flip is
+		 * enabled in the atomic IOCTL path.
+		 */
+		if (intel_plane->id != PLANE_PRIMARY)
+			return -EINVAL;
+
+		if (old_plane_state->color_plane[0].x !=
+		    new_plane_state->color_plane[0].x ||
+		    old_plane_state->color_plane[0].y !=
+		    new_plane_state->color_plane[0].y) {
+			DRM_DEBUG_KMS("Offsets cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->uapi.fb->modifier !=
+		    new_plane_state->uapi.fb->modifier) {
+			DRM_DEBUG_KMS("Framebuffer modifiers cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->uapi.fb->format !=
+		    new_plane_state->uapi.fb->format) {
+			DRM_DEBUG_KMS("Framebuffer format cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (intel_wm_need_update(old_plane_state, new_plane_state)) {
+			DRM_DEBUG_KMS("WM update not allowed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->uapi.alpha != new_plane_state->uapi.alpha) {
+			DRM_DEBUG_KMS("Alpha value cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->uapi.pixel_blend_mode !=
+		    new_plane_state->uapi.pixel_blend_mode) {
+			DRM_DEBUG_KMS("Pixel blend mode cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->uapi.color_encoding != new_plane_state->uapi.color_encoding) {
+			DRM_DEBUG_KMS("Color encoding cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+
+		if (old_plane_state->uapi.color_range != new_plane_state->uapi.color_range) {
+			DRM_DEBUG_KMS("Color range cannot be changed in async flip\n");
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
 /**
  * intel_atomic_check - validate state object
  * @dev: drm device
@@ -15011,6 +15115,15 @@ static int intel_atomic_check(struct drm_device *dev,
 				       "[modeset]" : "[fastset]");
 	}
 
+	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+		if (new_crtc_state->uapi.async_flip) {
+			ret = intel_atomic_check_async(state);
+			if (ret)
+				goto fail;
+
+			break;
+		}
+	}
 	return 0;
 
  fail:
-- 
2.22.0

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Re: [Intel-gfx] [PATCH v6 3/7] drm/i915: Add checks specific to async flips

[Ville Syrjälä]

On Fri, Aug 07, 2020 at 03:05:47PM +0530, Karthik B S wrote:
> If flip is requested on any other plane, reject it.
> 
> Make sure there is no change in fbc, offset and framebuffer modifiers
> when async flip is requested.
> 
> If any of these are modified, reject async flip.
> 
> v2: -Replace DRM_ERROR (Paulo)
>     -Add check for changes in OFFSET, FBC, RC(Paulo)
> 
> v3: -Removed TODO as benchmarking tests have been run now.
> 
> v4: -Added more state checks for async flip (Ville)
>     -Moved intel_atomic_check_async to the end of intel_atomic_check
>      as the plane checks needs to pass before this. (Ville)
>     -Removed crtc_state->enable_fbc check. (Ville)
>     -Set the I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP flag for async
>      flip case as scanline counter is not reliable here.
> 
> v5: -Fix typo and other check patch errors seen in CI
>      in 'intel_atomic_check_async' function.
> 
> v6: -Don't call intel_atomic_check_async multiple times. (Ville)
>     -Remove the check for n_planes in intel_atomic_check_async
>     -Added documentation for async flips. (Paulo)
> 
> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 113 +++++++++++++++++++
>  1 file changed, 113 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index ce2b0c14a073..9629c751d2af 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14832,6 +14832,110 @@ static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
>  	return false;
>  }
>  
> +/**
> + * DOC: asynchronous flip implementation
> + *
> + * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
> + * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
> + * Correspondingly, support is currently added for primary plane only.
> + *
> + * Async flip can only change the plane surface address, so anything else
> + * changing is rejected from the intel_atomic_check_async() function.
> + * Once this check is cleared, flip done interrupt is enabled using
> + * the skl_enable_flip_done() function.
> + *
> + * As soon as the surface address register is written, flip done interrupt is
> + * generated and the requested events are sent to the usersapce in the interrupt
> + * handler itself. The timestamp and sequence sent during the flip done event
> + * correspond to the last vblank and have no relation to the actual time when
> + * the flip done event was sent.
> + */
> +
> +static int intel_atomic_check_async(struct intel_atomic_state *state)
> +{
> +	struct intel_crtc_state *old_crtc_state, *new_crtc_state;
> +	struct intel_plane_state *new_plane_state, *old_plane_state;
> +	struct intel_crtc *crtc;
> +	struct intel_plane *intel_plane;

s/intel_plane/plane/

> +	int i;
> +
> +	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> +					    new_crtc_state, i) {
> +		if (needs_modeset(new_crtc_state)) {
> +			DRM_DEBUG_KMS("Modeset Required. Async flip not supported\n");
> +			return -EINVAL;
> +		}
> +
> +		if (!new_crtc_state->uapi.active) {
> +			DRM_DEBUG_KMS("CRTC inactive\n");
> +			return -EINVAL;
> +		}

All the uapi.foo stuff should be hw.foo most likely.

> +		if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
> +			DRM_DEBUG_KMS("Active planes cannot be changed during async flip\n");
> +			return -EINVAL;
> +		}
> +	}
> +
> +	for_each_oldnew_intel_plane_in_state(state, intel_plane, old_plane_state,
> +					     new_plane_state, i) {
> +		/*TODO: Async flip is only supported through the page flip IOCTL
> +		 * as of now. So support currently added for primary plane only.
> +		 * Support for other planes should be added when async flip is
> +		 * enabled in the atomic IOCTL path.
> +		 */
> +		if (intel_plane->id != PLANE_PRIMARY)
> +			return -EINVAL;
> +
> +		if (old_plane_state->color_plane[0].x !=
> +		    new_plane_state->color_plane[0].x ||
> +		    old_plane_state->color_plane[0].y !=
> +		    new_plane_state->color_plane[0].y) {
> +			DRM_DEBUG_KMS("Offsets cannot be changed in async flip\n");
> +			return -EINVAL;
> +		}
> +
> +		if (old_plane_state->uapi.fb->modifier !=
> +		    new_plane_state->uapi.fb->modifier) {
> +			DRM_DEBUG_KMS("Framebuffer modifiers cannot be changed in async flip\n");
> +			return -EINVAL;
> +		}
> +
> +		if (old_plane_state->uapi.fb->format !=
> +		    new_plane_state->uapi.fb->format) {
> +			DRM_DEBUG_KMS("Framebuffer format cannot be changed in async flip\n");
> +			return -EINVAL;
> +		}
> +
> +		if (intel_wm_need_update(old_plane_state, new_plane_state)) {

That function is meant for pre-g4x wm hacks only. Do not use.

> +			DRM_DEBUG_KMS("WM update not allowed in async flip\n");
> +			return -EINVAL;
> +		}
> +
> +		if (old_plane_state->uapi.alpha != new_plane_state->uapi.alpha) {
> +			DRM_DEBUG_KMS("Alpha value cannot be changed in async flip\n");
> +			return -EINVAL;
> +		}
> +
> +		if (old_plane_state->uapi.pixel_blend_mode !=
> +		    new_plane_state->uapi.pixel_blend_mode) {
> +			DRM_DEBUG_KMS("Pixel blend mode cannot be changed in async flip\n");
> +			return -EINVAL;
> +		}
> +
> +		if (old_plane_state->uapi.color_encoding != new_plane_state->uapi.color_encoding) {
> +			DRM_DEBUG_KMS("Color encoding cannot be changed in async flip\n");
> +			return -EINVAL;
> +		}
> +
> +		if (old_plane_state->uapi.color_range != new_plane_state->uapi.color_range) {
> +			DRM_DEBUG_KMS("Color range cannot be changed in async flip\n");
> +			return -EINVAL;
> +		}

Seems to be missing at least a dst coordinate check.

Not sure we can allow async flip with linear buffers. Older hw at least
had issues with that.

> +	}
> +
> +	return 0;
> +}
> +
>  /**
>   * intel_atomic_check - validate state object
>   * @dev: drm device
> @@ -15011,6 +15115,15 @@ static int intel_atomic_check(struct drm_device *dev,
>  				       "[modeset]" : "[fastset]");
>  	}
>  
> +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> +		if (new_crtc_state->uapi.async_flip) {
> +			ret = intel_atomic_check_async(state);
> +			if (ret)
> +				goto fail;
> +
> +			break;

Why would we break here?

> +		}
> +	}
>  	return 0;
>  
>   fail:
> -- 
> 2.22.0

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v6 3/7] drm/i915: Add checks specific to async flips

[Karthik B S]

On 9/1/2020 4:51 PM, Ville Syrjälä wrote:
> On Fri, Aug 07, 2020 at 03:05:47PM +0530, Karthik B S wrote:
>> If flip is requested on any other plane, reject it.
>>
>> Make sure there is no change in fbc, offset and framebuffer modifiers
>> when async flip is requested.
>>
>> If any of these are modified, reject async flip.
>>
>> v2: -Replace DRM_ERROR (Paulo)
>>      -Add check for changes in OFFSET, FBC, RC(Paulo)
>>
>> v3: -Removed TODO as benchmarking tests have been run now.
>>
>> v4: -Added more state checks for async flip (Ville)
>>      -Moved intel_atomic_check_async to the end of intel_atomic_check
>>       as the plane checks needs to pass before this. (Ville)
>>      -Removed crtc_state->enable_fbc check. (Ville)
>>      -Set the I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP flag for async
>>       flip case as scanline counter is not reliable here.
>>
>> v5: -Fix typo and other check patch errors seen in CI
>>       in 'intel_atomic_check_async' function.
>>
>> v6: -Don't call intel_atomic_check_async multiple times. (Ville)
>>      -Remove the check for n_planes in intel_atomic_check_async
>>      -Added documentation for async flips. (Paulo)
>>
>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display.c | 113 +++++++++++++++++++
>>   1 file changed, 113 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index ce2b0c14a073..9629c751d2af 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -14832,6 +14832,110 @@ static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
>>   	return false;
>>   }
>>   
>> +/**
>> + * DOC: asynchronous flip implementation
>> + *
>> + * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
>> + * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
>> + * Correspondingly, support is currently added for primary plane only.
>> + *
>> + * Async flip can only change the plane surface address, so anything else
>> + * changing is rejected from the intel_atomic_check_async() function.
>> + * Once this check is cleared, flip done interrupt is enabled using
>> + * the skl_enable_flip_done() function.
>> + *
>> + * As soon as the surface address register is written, flip done interrupt is
>> + * generated and the requested events are sent to the usersapce in the interrupt
>> + * handler itself. The timestamp and sequence sent during the flip done event
>> + * correspond to the last vblank and have no relation to the actual time when
>> + * the flip done event was sent.
>> + */
>> +
>> +static int intel_atomic_check_async(struct intel_atomic_state *state)
>> +{
>> +	struct intel_crtc_state *old_crtc_state, *new_crtc_state;
>> +	struct intel_plane_state *new_plane_state, *old_plane_state;
>> +	struct intel_crtc *crtc;
>> +	struct intel_plane *intel_plane;
> 
> s/intel_plane/plane/
> 

Thanks for the review.
I will update this.
>> +	int i;
>> +
>> +	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>> +					    new_crtc_state, i) {
>> +		if (needs_modeset(new_crtc_state)) {
>> +			DRM_DEBUG_KMS("Modeset Required. Async flip not supported\n");
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (!new_crtc_state->uapi.active) {
>> +			DRM_DEBUG_KMS("CRTC inactive\n");
>> +			return -EINVAL;
>> +		}
> 
> All the uapi.foo stuff should be hw.foo most likely.
>
Will update this.

>> +		if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
>> +			DRM_DEBUG_KMS("Active planes cannot be changed during async flip\n");
>> +			return -EINVAL;
>> +		}
>> +	}
>> +
>> +	for_each_oldnew_intel_plane_in_state(state, intel_plane, old_plane_state,
>> +					     new_plane_state, i) {
>> +		/*TODO: Async flip is only supported through the page flip IOCTL
>> +		 * as of now. So support currently added for primary plane only.
>> +		 * Support for other planes should be added when async flip is
>> +		 * enabled in the atomic IOCTL path.
>> +		 */
>> +		if (intel_plane->id != PLANE_PRIMARY)
>> +			return -EINVAL;
>> +
>> +		if (old_plane_state->color_plane[0].x !=
>> +		    new_plane_state->color_plane[0].x ||
>> +		    old_plane_state->color_plane[0].y !=
>> +		    new_plane_state->color_plane[0].y) {
>> +			DRM_DEBUG_KMS("Offsets cannot be changed in async flip\n");
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (old_plane_state->uapi.fb->modifier !=
>> +		    new_plane_state->uapi.fb->modifier) {
>> +			DRM_DEBUG_KMS("Framebuffer modifiers cannot be changed in async flip\n");
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (old_plane_state->uapi.fb->format !=
>> +		    new_plane_state->uapi.fb->format) {
>> +			DRM_DEBUG_KMS("Framebuffer format cannot be changed in async flip\n");
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (intel_wm_need_update(old_plane_state, new_plane_state)) {
> 
> That function is meant for pre-g4x wm hacks only. Do not use.
> 

Sure. Will put the checks present in the intel_wm_need_update function 
explicitly here.
>> +			DRM_DEBUG_KMS("WM update not allowed in async flip\n");
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (old_plane_state->uapi.alpha != new_plane_state->uapi.alpha) {
>> +			DRM_DEBUG_KMS("Alpha value cannot be changed in async flip\n");
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (old_plane_state->uapi.pixel_blend_mode !=
>> +		    new_plane_state->uapi.pixel_blend_mode) {
>> +			DRM_DEBUG_KMS("Pixel blend mode cannot be changed in async flip\n");
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (old_plane_state->uapi.color_encoding != new_plane_state->uapi.color_encoding) {
>> +			DRM_DEBUG_KMS("Color encoding cannot be changed in async flip\n");
>> +			return -EINVAL;
>> +		}
>> +
>> +		if (old_plane_state->uapi.color_range != new_plane_state->uapi.color_range) {
>> +			DRM_DEBUG_KMS("Color range cannot be changed in async flip\n");
>> +			return -EINVAL;
>> +		}
> 
> Seems to be missing at least a dst coordinate check.
> 

Sure, will add this. I hadn't added it as it would be covered in the 
previous wm check. Will update it.
> Not sure we can allow async flip with linear buffers. Older hw at least
> had issues with that.
> 

I did not find any restrictions regarding this on bspec.
 From the bspec, "Changes to stride, pixel, format, RenderCompression, 
FBC, etc. are not allowed"
In IGT, we're currently using x-tiled buffer. Will confirm this via IGT 
and if required add a check for this.
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>>   /**
>>    * intel_atomic_check - validate state object
>>    * @dev: drm device
>> @@ -15011,6 +15115,15 @@ static int intel_atomic_check(struct drm_device *dev,
>>   				       "[modeset]" : "[fastset]");
>>   	}
>>   
>> +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>> +		if (new_crtc_state->uapi.async_flip) {
>> +			ret = intel_atomic_check_async(state);
>> +			if (ret)
>> +				goto fail;
>> +
>> +			break;
> 
> Why would we break here?
> 

Calling this multiple times is redundant, so put a break here.
Would you suggest handling this differently?

Thanks,
Karthik.B.S
>> +		}
>> +	}
>>   	return 0;
>>   
>>    fail:
>> -- 
>> 2.22.0
> 
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[Intel-gfx] [PATCH v6 4/7] drm/i915: Do not call drm_crtc_arm_vblank_event in async flips

[Karthik B S]

Since the flip done event will be sent in the flip_done_handler,
no need to add the event to the list and delay it for later.

v2: -Moved the async check above vblank_get as it
     was causing issues for PSR.

v3: -No need to wait for vblank to pass, as this wait was causing a
     16ms delay once every few flips.

v4: -Rebased.

v5: -Rebased.

v6: -Rebased.

Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_sprite.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index c26ca029fc0a..2b2d96c59d7f 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -93,6 +93,9 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
 	DEFINE_WAIT(wait);
 	u32 psr_status;
 
+	if (new_crtc_state->uapi.async_flip)
+		goto irq_disable;
+
 	vblank_start = adjusted_mode->crtc_vblank_start;
 	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
 		vblank_start = DIV_ROUND_UP(vblank_start, 2);
@@ -206,7 +209,7 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
 	 * Would be slightly nice to just grab the vblank count and arm the
 	 * event outside of the critical section - the spinlock might spin for a
 	 * while ... */
-	if (new_crtc_state->uapi.event) {
+	if (new_crtc_state->uapi.event && !new_crtc_state->uapi.async_flip) {
 		drm_WARN_ON(&dev_priv->drm,
 			    drm_crtc_vblank_get(&crtc->base) != 0);
 
@@ -220,6 +223,9 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
 
 	local_irq_enable();
 
+	if (new_crtc_state->uapi.async_flip)
+		return;
+
 	if (intel_vgpu_active(dev_priv))
 		return;
 
-- 
2.22.0

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Re: [Intel-gfx] [PATCH v6 4/7] drm/i915: Do not call drm_crtc_arm_vblank_event in async flips

[Ville Syrjälä]

On Fri, Aug 07, 2020 at 03:05:48PM +0530, Karthik B S wrote:
> Since the flip done event will be sent in the flip_done_handler,
> no need to add the event to the list and delay it for later.
> 
> v2: -Moved the async check above vblank_get as it
>      was causing issues for PSR.
> 
> v3: -No need to wait for vblank to pass, as this wait was causing a
>      16ms delay once every few flips.
> 
> v4: -Rebased.
> 
> v5: -Rebased.
> 
> v6: -Rebased.
> 
> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_sprite.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index c26ca029fc0a..2b2d96c59d7f 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -93,6 +93,9 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
>  	DEFINE_WAIT(wait);
>  	u32 psr_status;
>  
> +	if (new_crtc_state->uapi.async_flip)
> +		goto irq_disable;

We shouldn't really need the irq disable at all if we don't do the
vblank evade. And if we only write ctl+surf then atomicity is already
guaranteed by the hw.

> +
>  	vblank_start = adjusted_mode->crtc_vblank_start;
>  	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
>  		vblank_start = DIV_ROUND_UP(vblank_start, 2);
> @@ -206,7 +209,7 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
>  	 * Would be slightly nice to just grab the vblank count and arm the
>  	 * event outside of the critical section - the spinlock might spin for a
>  	 * while ... */
> -	if (new_crtc_state->uapi.event) {
> +	if (new_crtc_state->uapi.event && !new_crtc_state->uapi.async_flip) {
>  		drm_WARN_ON(&dev_priv->drm,
>  			    drm_crtc_vblank_get(&crtc->base) != 0);
>  
> @@ -220,6 +223,9 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
>  
>  	local_irq_enable();
>  
> +	if (new_crtc_state->uapi.async_flip)
> +		return;
> +
>  	if (intel_vgpu_active(dev_priv))
>  		return;
>  
> -- 
> 2.22.0

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v6 4/7] drm/i915: Do not call drm_crtc_arm_vblank_event in async flips

[Karthik B S]

On 9/1/2020 4:53 PM, Ville Syrjälä wrote:
> On Fri, Aug 07, 2020 at 03:05:48PM +0530, Karthik B S wrote:
>> Since the flip done event will be sent in the flip_done_handler,
>> no need to add the event to the list and delay it for later.
>>
>> v2: -Moved the async check above vblank_get as it
>>       was causing issues for PSR.
>>
>> v3: -No need to wait for vblank to pass, as this wait was causing a
>>       16ms delay once every few flips.
>>
>> v4: -Rebased.
>>
>> v5: -Rebased.
>>
>> v6: -Rebased.
>>
>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_sprite.c | 8 +++++++-
>>   1 file changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
>> index c26ca029fc0a..2b2d96c59d7f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>> @@ -93,6 +93,9 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
>>   	DEFINE_WAIT(wait);
>>   	u32 psr_status;
>>   
>> +	if (new_crtc_state->uapi.async_flip)
>> +		goto irq_disable;
> 
> We shouldn't really need the irq disable at all if we don't do the
> vblank evade. And if we only write ctl+surf then atomicity is already
> guaranteed by the hw.
> 

Thanks for the review.
Sure, will return directly after this check.

Thanks,
Karthik.B.S
>> +
>>   	vblank_start = adjusted_mode->crtc_vblank_start;
>>   	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
>>   		vblank_start = DIV_ROUND_UP(vblank_start, 2);
>> @@ -206,7 +209,7 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
>>   	 * Would be slightly nice to just grab the vblank count and arm the
>>   	 * event outside of the critical section - the spinlock might spin for a
>>   	 * while ... */
>> -	if (new_crtc_state->uapi.event) {
>> +	if (new_crtc_state->uapi.event && !new_crtc_state->uapi.async_flip) {
>>   		drm_WARN_ON(&dev_priv->drm,
>>   			    drm_crtc_vblank_get(&crtc->base) != 0);
>>   
>> @@ -220,6 +223,9 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
>>   
>>   	local_irq_enable();
>>   
>> +	if (new_crtc_state->uapi.async_flip)
>> +		return;
>> +
>>   	if (intel_vgpu_active(dev_priv))
>>   		return;
>>   
>> -- 
>> 2.22.0
> 
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[Intel-gfx] [PATCH v6 5/7] drm/i915: Add dedicated plane hook for async flip case

[Karthik B S]

This hook is added to avoid writing other plane registers in case of
async flips, so that we do not write the double buffered registers
during async surface address update.

Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_sprite.c | 25 +++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 2b2d96c59d7f..1c03546a4d2a 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -609,6 +609,24 @@ icl_program_input_csc(struct intel_plane *plane,
 			  PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
 }
 
+static void
+skl_program_async_surface_address(struct drm_i915_private *dev_priv,
+				  const struct intel_plane_state *plane_state,
+				  enum pipe pipe, enum plane_id plane_id,
+				  u32 surf_addr)
+{
+	unsigned long irqflags;
+	u32 plane_ctl = plane_state->ctl;
+
+	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+
+	intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
+	intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
+			  intel_plane_ggtt_offset(plane_state) + surf_addr);
+
+	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+}
+
 static void
 skl_program_plane(struct intel_plane *plane,
 		  const struct intel_crtc_state *crtc_state,
@@ -637,6 +655,13 @@ skl_program_plane(struct intel_plane *plane,
 	u32 keymsk, keymax;
 	u32 plane_ctl = plane_state->ctl;
 
+	/* During Async flip, no other updates are allowed */
+	if (crtc_state->uapi.async_flip) {
+		skl_program_async_surface_address(dev_priv, plane_state,
+						  pipe, plane_id, surf_addr);
+		return;
+	}
+
 	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
 
 	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
-- 
2.22.0

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Re: [Intel-gfx] [PATCH v6 5/7] drm/i915: Add dedicated plane hook for async flip case

[Ville Syrjälä]

On Fri, Aug 07, 2020 at 03:05:49PM +0530, Karthik B S wrote:
> This hook is added to avoid writing other plane registers in case of
> async flips, so that we do not write the double buffered registers
> during async surface address update.
> 
> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_sprite.c | 25 +++++++++++++++++++++
>  1 file changed, 25 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
> index 2b2d96c59d7f..1c03546a4d2a 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
> @@ -609,6 +609,24 @@ icl_program_input_csc(struct intel_plane *plane,
>  			  PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
>  }
>  
> +static void
> +skl_program_async_surface_address(struct drm_i915_private *dev_priv,
> +				  const struct intel_plane_state *plane_state,
> +				  enum pipe pipe, enum plane_id plane_id,
> +				  u32 surf_addr)
> +{
> +	unsigned long irqflags;
> +	u32 plane_ctl = plane_state->ctl;

Need the bits from skl_plane_ctl_crtc() too.

> +
> +	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> +
> +	intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
> +	intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
> +			  intel_plane_ggtt_offset(plane_state) + surf_addr);
> +
> +	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> +}
> +
>  static void
>  skl_program_plane(struct intel_plane *plane,
>  		  const struct intel_crtc_state *crtc_state,
> @@ -637,6 +655,13 @@ skl_program_plane(struct intel_plane *plane,
>  	u32 keymsk, keymax;
>  	u32 plane_ctl = plane_state->ctl;
>  
> +	/* During Async flip, no other updates are allowed */
> +	if (crtc_state->uapi.async_flip) {
> +		skl_program_async_surface_address(dev_priv, plane_state,
> +						  pipe, plane_id, surf_addr);
> +		return;
> +	}

I'd suggest adding a vfunc for this. Should be able to call it from
intel_update_plane(). That way we don't need to patch it into each
and every .update_plane() implementation.


> +
>  	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
>  
>  	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> -- 
> 2.22.0

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] [PATCH v6 5/7] drm/i915: Add dedicated plane hook for async flip case

[Karthik B S]

On 9/1/2020 4:57 PM, Ville Syrjälä wrote:
> On Fri, Aug 07, 2020 at 03:05:49PM +0530, Karthik B S wrote:
>> This hook is added to avoid writing other plane registers in case of
>> async flips, so that we do not write the double buffered registers
>> during async surface address update.
>>
>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_sprite.c | 25 +++++++++++++++++++++
>>   1 file changed, 25 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
>> index 2b2d96c59d7f..1c03546a4d2a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_sprite.c
>> +++ b/drivers/gpu/drm/i915/display/intel_sprite.c
>> @@ -609,6 +609,24 @@ icl_program_input_csc(struct intel_plane *plane,
>>   			  PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
>>   }
>>   
>> +static void
>> +skl_program_async_surface_address(struct drm_i915_private *dev_priv,
>> +				  const struct intel_plane_state *plane_state,
>> +				  enum pipe pipe, enum plane_id plane_id,
>> +				  u32 surf_addr)
>> +{
>> +	unsigned long irqflags;
>> +	u32 plane_ctl = plane_state->ctl;
> 
> Need the bits from skl_plane_ctl_crtc() too.

Thanks for the review.
Sure, I'll update this.
> 
>> +
>> +	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
>> +
>> +	intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
>> +	intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
>> +			  intel_plane_ggtt_offset(plane_state) + surf_addr);
>> +
>> +	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
>> +}
>> +
>>   static void
>>   skl_program_plane(struct intel_plane *plane,
>>   		  const struct intel_crtc_state *crtc_state,
>> @@ -637,6 +655,13 @@ skl_program_plane(struct intel_plane *plane,
>>   	u32 keymsk, keymax;
>>   	u32 plane_ctl = plane_state->ctl;
>>   
>> +	/* During Async flip, no other updates are allowed */
>> +	if (crtc_state->uapi.async_flip) {
>> +		skl_program_async_surface_address(dev_priv, plane_state,
>> +						  pipe, plane_id, surf_addr);
>> +		return;
>> +	}
> 
> I'd suggest adding a vfunc for this. Should be able to call it from
> intel_update_plane(). That way we don't need to patch it into each
> and every .update_plane() implementation.
> 

Sure. I will add a vfunc for this in intel_plane and call it directly 
from intel_update_plane()

Thanks,
Karthik.B.S
> 
>> +
>>   	plane_ctl |= skl_plane_ctl_crtc(crtc_state);
>>   
>>   	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
>> -- 
>> 2.22.0
> 
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[Intel-gfx] [PATCH v6 6/7] Documentation/gpu: Add asynchronous flip documentation for i915

[Karthik B S]

Add the details of the implementation of asynchronous flips for i915.

Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 Documentation/gpu/i915.rst | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst
index 33cc6ddf8f64..84ead508f7ad 100644
--- a/Documentation/gpu/i915.rst
+++ b/Documentation/gpu/i915.rst
@@ -118,6 +118,12 @@ Atomic Plane Helpers
 .. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c
    :internal:
 
+Asynchronous Page Flip
+----------------------
+
+.. kernel-doc:: drivers/gpu/drm/i915/display/intel_display.c
+   :doc: asynchronous flip implementation
+
 Output Probing
 --------------
 
-- 
2.22.0

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[Intel-gfx] [PATCH v6 7/7] drm/i915: Enable async flips in i915

[Karthik B S]

Enable asynchronous flips in i915 for gen9+ platforms.

v2: -Async flip enablement should be a stand alone patch (Paulo)

v3: -Move the patch to the end of the serires (Paulo)

v4: -Rebased.

v5: -Rebased.

v6: -Rebased.

Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 9629c751d2af..3574b2700b99 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17901,6 +17901,9 @@ static void intel_mode_config_init(struct drm_i915_private *i915)
 
 	mode_config->funcs = &intel_mode_funcs;
 
+	if (INTEL_GEN(i915) >= 9)
+		mode_config->async_page_flip = true;
+
 	/*
 	 * Maximum framebuffer dimensions, chosen to match
 	 * the maximum render engine surface size on gen4+.
-- 
2.22.0

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[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Asynchronous flip implementation for i915 (rev6)

[Patchwork]

== Series Details ==

Series: Asynchronous flip implementation for i915 (rev6)
URL   : https://patchwork.freedesktop.org/series/74386/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be checked separately.


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[Intel-gfx] ✓ Fi.CI.BAT: success for Asynchronous flip implementation for i915 (rev6)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 6403 bytes --]

== Series Details ==

Series: Asynchronous flip implementation for i915 (rev6)
URL   : https://patchwork.freedesktop.org/series/74386/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8856 -> Patchwork_18320
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/index.html

Known issues
------------

  Here are the changes found in Patchwork_18320 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_module_load@reload:
    - fi-byt-j1900:       [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/fi-byt-j1900/igt@i915_module_load@reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/fi-byt-j1900/igt@i915_module_load@reload.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@execlists:
    - fi-skl-6600u:       [INCOMPLETE][3] ([CI#80] / [i915#1795]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/fi-skl-6600u/igt@i915_selftest@live@execlists.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/fi-skl-6600u/igt@i915_selftest@live@execlists.html
    - fi-icl-y:           [INCOMPLETE][5] ([i915#2276]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/fi-icl-y/igt@i915_selftest@live@execlists.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/fi-icl-y/igt@i915_selftest@live@execlists.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - {fi-tgl-dsi}:       [DMESG-WARN][7] ([i915#1982]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/fi-tgl-dsi/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/fi-tgl-dsi/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1:
    - fi-icl-u2:          [DMESG-WARN][9] ([i915#1982]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html

  * igt@kms_flip@basic-flip-vs-wf_vblank@c-hdmi-a2:
    - fi-skl-guc:         [DMESG-WARN][11] ([i915#2203]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/fi-skl-guc/igt@kms_flip@basic-flip-vs-wf_vblank@c-hdmi-a2.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/fi-skl-guc/igt@kms_flip@basic-flip-vs-wf_vblank@c-hdmi-a2.html

  
#### Warnings ####

  * igt@gem_exec_suspend@basic-s0:
    - fi-kbl-x1275:       [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html

  * igt@gem_exec_suspend@basic-s3:
    - fi-kbl-x1275:       [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#1982] / [i915#62] / [i915#92] / [i915#95])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/fi-kbl-x1275/igt@gem_exec_suspend@basic-s3.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/fi-kbl-x1275/igt@gem_exec_suspend@basic-s3.html

  * igt@i915_pm_rpm@module-reload:
    - fi-kbl-x1275:       [DMESG-FAIL][17] ([i915#62]) -> [SKIP][18] ([fdo#109271])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html

  * igt@kms_force_connector_basic@force-edid:
    - fi-kbl-x1275:       [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#62] / [i915#92]) +3 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/fi-kbl-x1275/igt@kms_force_connector_basic@force-edid.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1795]: https://gitlab.freedesktop.org/drm/intel/issues/1795
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
  [i915#2268]: https://gitlab.freedesktop.org/drm/intel/issues/2268
  [i915#2276]: https://gitlab.freedesktop.org/drm/intel/issues/2276
  [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
  [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (44 -> 38)
------------------------------

  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * IGT: IGT_5764 -> IGTPW_4861
  * Linux: CI_DRM_8856 -> Patchwork_18320

  CI-20190529: 20190529
  CI_DRM_8856: 238c742f0beea85fc171bfc3eef05cf284af6d4d @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_4861: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4861/index.html
  IGT_5764: 0f91c80b4c809cf48afff65a2ea68590389aa5ba @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18320: 4f2669d75a4cad149edc1f11f7dc1c05eb56815e @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

4f2669d75a4c drm/i915: Enable async flips in i915
a4e35292a259 Documentation/gpu: Add asynchronous flip documentation for i915
27d0a036ee99 drm/i915: Add dedicated plane hook for async flip case
62398754b0b1 drm/i915: Do not call drm_crtc_arm_vblank_event in async flips
ef309bd93925 drm/i915: Add checks specific to async flips
43e5f81deedb drm/i915: Add support for async flips in I915
0ec4755ab95b drm/i915: Add enable/disable flip done and flip done handler

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/index.html

[-- Attachment #1.2: Type: text/html, Size: 8258 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

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[Intel-gfx] ✓ Fi.CI.IGT: success for Asynchronous flip implementation for i915 (rev6)

[Patchwork]

[-- Attachment #1.1: Type: text/plain, Size: 23213 bytes --]

== Series Details ==

Series: Asynchronous flip implementation for i915 (rev6)
URL   : https://patchwork.freedesktop.org/series/74386/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8856_full -> Patchwork_18320_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_18320_full:

### IGT changes ###

#### Possible regressions ####

  * {igt@kms_async_flips@async-flip-with-page-flip-events} (NEW):
    - shard-kbl:          NOTRUN -> [FAIL][1] +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-kbl2/igt@kms_async_flips@async-flip-with-page-flip-events.html
    - shard-glk:          NOTRUN -> [FAIL][2] +1 similar issue
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-glk5/igt@kms_async_flips@async-flip-with-page-flip-events.html

  * {igt@kms_async_flips@test-time-stamp} (NEW):
    - shard-skl:          NOTRUN -> [FAIL][3] +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-skl4/igt@kms_async_flips@test-time-stamp.html

  
New tests
---------

  New tests have been introduced between CI_DRM_8856_full and Patchwork_18320_full:

### New IGT tests (3) ###

  * igt@kms_async_flips@async-flip-with-page-flip-events:
    - Statuses : 3 fail(s) 3 pass(s) 2 skip(s)
    - Exec time: [0.0, 3.00] s

  * igt@kms_async_flips@async-flip-without-page-flip-events:
    - Statuses : 6 pass(s) 2 skip(s)
    - Exec time: [0.0, 3.00] s

  * igt@kms_async_flips@test-time-stamp:
    - Statuses : 4 fail(s) 2 pass(s) 2 skip(s)
    - Exec time: [0.0, 0.34] s

  

Known issues
------------

  Here are the changes found in Patchwork_18320_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_whisper@basic-queues-all:
    - shard-glk:          [PASS][4] -> [DMESG-WARN][5] ([i915#118] / [i915#95])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-glk3/igt@gem_exec_whisper@basic-queues-all.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-glk5/igt@gem_exec_whisper@basic-queues-all.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-snb:          [PASS][6] -> [DMESG-WARN][7] ([i915#42])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-snb6/igt@gem_workarounds@suspend-resume-fd.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-snb1/igt@gem_workarounds@suspend-resume-fd.html

  * igt@kms_atomic_interruptible@legacy-dpms:
    - shard-snb:          [PASS][8] -> [SKIP][9] ([fdo#109271])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-snb1/igt@kms_atomic_interruptible@legacy-dpms.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-snb4/igt@kms_atomic_interruptible@legacy-dpms.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-kbl:          [PASS][10] -> [DMESG-WARN][11] ([i915#180]) +9 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_cursor_crc@pipe-b-cursor-128x128-random:
    - shard-skl:          [PASS][12] -> [SKIP][13] ([fdo#109271]) +18 similar issues
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-skl7/igt@kms_cursor_crc@pipe-b-cursor-128x128-random.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-skl1/igt@kms_cursor_crc@pipe-b-cursor-128x128-random.html

  * igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge:
    - shard-skl:          [PASS][14] -> [DMESG-WARN][15] ([i915#1982]) +45 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-skl6/igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-skl8/igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
    - shard-tglb:         [PASS][16] -> [DMESG-WARN][17] ([i915#1982]) +2 similar issues
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-tglb3/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-tglb1/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-kbl:          [PASS][18] -> [INCOMPLETE][19] ([i915#155])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_hdr@bpc-switch:
    - shard-skl:          [PASS][20] -> [FAIL][21] ([i915#1188])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-skl1/igt@kms_hdr@bpc-switch.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-skl9/igt@kms_hdr@bpc-switch.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c:
    - shard-skl:          [PASS][22] -> [FAIL][23] ([i915#53])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-skl5/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-skl7/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-skl:          [PASS][24] -> [INCOMPLETE][25] ([i915#198])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-skl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-skl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_psr@cursor_mmap_gtt:
    - shard-skl:          [PASS][26] -> [CRASH][27] ([i915#2212])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-skl4/igt@kms_psr@cursor_mmap_gtt.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-skl1/igt@kms_psr@cursor_mmap_gtt.html

  * igt@kms_psr@psr2_cursor_plane_move:
    - shard-iclb:         [PASS][28] -> [SKIP][29] ([fdo#109441]) +1 similar issue
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-iclb1/igt@kms_psr@psr2_cursor_plane_move.html

  * igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
    - shard-tglb:         [PASS][30] -> [INCOMPLETE][31] ([i915#1602] / [i915#1887] / [i915#456])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-tglb1/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-tglb1/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html

  * igt@kms_vblank@pipe-b-wait-forked-hang:
    - shard-apl:          [PASS][32] -> [DMESG-WARN][33] ([i915#1635] / [i915#1982])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-apl3/igt@kms_vblank@pipe-b-wait-forked-hang.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-apl8/igt@kms_vblank@pipe-b-wait-forked-hang.html

  * igt@prime_busy@hang-wait@bcs0:
    - shard-hsw:          [PASS][34] -> [FAIL][35] ([i915#2258]) +6 similar issues
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-hsw8/igt@prime_busy@hang-wait@bcs0.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-hsw8/igt@prime_busy@hang-wait@bcs0.html

  
#### Possible fixes ####

  * igt@gem_exec_balancer@bonded-early:
    - shard-kbl:          [FAIL][36] ([i915#2079]) -> [PASS][37]
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-kbl6/igt@gem_exec_balancer@bonded-early.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-kbl2/igt@gem_exec_balancer@bonded-early.html

  * igt@gem_sync@basic-all:
    - shard-glk:          [DMESG-WARN][38] ([i915#118] / [i915#95]) -> [PASS][39] +2 similar issues
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-glk1/igt@gem_sync@basic-all.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-glk1/igt@gem_sync@basic-all.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-skl:          [FAIL][40] ([i915#454]) -> [PASS][41]
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-skl9/igt@i915_pm_dc@dc6-psr.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-skl2/igt@i915_pm_dc@dc6-psr.html

  * igt@kms_big_fb@linear-32bpp-rotate-180:
    - shard-skl:          [DMESG-WARN][42] ([i915#1982]) -> [PASS][43] +32 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-skl6/igt@kms_big_fb@linear-32bpp-rotate-180.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-skl8/igt@kms_big_fb@linear-32bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-90:
    - shard-apl:          [DMESG-WARN][44] ([i915#1635] / [i915#1982]) -> [PASS][45] +1 similar issue
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-apl4/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-apl3/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html

  * igt@kms_cursor_legacy@pipe-c-torture-move:
    - shard-tglb:         [DMESG-WARN][46] ([i915#128]) -> [PASS][47]
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-tglb2/igt@kms_cursor_legacy@pipe-c-torture-move.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-tglb6/igt@kms_cursor_legacy@pipe-c-torture-move.html

  * igt@kms_draw_crc@fill-fb:
    - shard-skl:          [FAIL][48] ([i915#52]) -> [PASS][49]
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-skl9/igt@kms_draw_crc@fill-fb.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-skl4/igt@kms_draw_crc@fill-fb.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp1:
    - shard-apl:          [FAIL][50] ([i915#1635] / [i915#79]) -> [PASS][51]
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-apl8/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp1.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-apl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp1.html

  * igt@kms_flip@flip-vs-suspend-interruptible@b-edp1:
    - shard-skl:          [INCOMPLETE][52] -> [PASS][53]
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-skl4/igt@kms_flip@flip-vs-suspend-interruptible@b-edp1.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-skl4/igt@kms_flip@flip-vs-suspend-interruptible@b-edp1.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc:
    - shard-iclb:         [DMESG-WARN][54] ([i915#1982]) -> [PASS][55]
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
    - shard-kbl:          [DMESG-WARN][56] ([i915#1982]) -> [PASS][57] +1 similar issue
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-kbl3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
    - shard-glk:          [FAIL][58] ([i915#49]) -> [PASS][59]
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-glk5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-glk3/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc:
    - shard-tglb:         [DMESG-WARN][60] ([i915#1982]) -> [PASS][61] +1 similar issue
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-skl:          [FAIL][62] ([i915#49]) -> [PASS][63]
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-skl:          [DMESG-FAIL][64] ([i915#1982] / [i915#83]) -> [PASS][65]
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-skl4/igt@kms_panel_fitting@atomic-fastset.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-skl7/igt@kms_panel_fitting@atomic-fastset.html
    - shard-iclb:         [FAIL][66] ([i915#83]) -> [PASS][67]
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-iclb6/igt@kms_panel_fitting@atomic-fastset.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-iclb8/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_plane@plane-position-hole-dpms-pipe-a-planes:
    - shard-skl:          [SKIP][68] ([fdo#109271]) -> [PASS][69] +1 similar issue
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-skl4/igt@kms_plane@plane-position-hole-dpms-pipe-a-planes.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-skl2/igt@kms_plane@plane-position-hole-dpms-pipe-a-planes.html

  * igt@kms_psr@psr2_no_drrs:
    - shard-iclb:         [SKIP][70] ([fdo#109441]) -> [PASS][71] +1 similar issue
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-iclb4/igt@kms_psr@psr2_no_drrs.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-iclb2/igt@kms_psr@psr2_no_drrs.html

  * igt@kms_vblank@pipe-a-accuracy-idle:
    - shard-glk:          [FAIL][72] ([i915#43]) -> [PASS][73]
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-glk3/igt@kms_vblank@pipe-a-accuracy-idle.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-glk3/igt@kms_vblank@pipe-a-accuracy-idle.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-kbl:          [DMESG-WARN][74] ([i915#180]) -> [PASS][75] +1 similar issue
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-kbl2/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  * igt@prime_busy@hang@bcs0:
    - shard-hsw:          [FAIL][76] ([i915#2258]) -> [PASS][77] +2 similar issues
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-hsw4/igt@prime_busy@hang@bcs0.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-hsw1/igt@prime_busy@hang@bcs0.html

  * {igt@syncobj_timeline@etime-multi-wait-all-for-submit-submitted}:
    - shard-hsw:          [TIMEOUT][78] ([i915#1958]) -> [PASS][79] +3 similar issues
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-hsw8/igt@syncobj_timeline@etime-multi-wait-all-for-submit-submitted.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-hsw7/igt@syncobj_timeline@etime-multi-wait-all-for-submit-submitted.html

  * igt@syncobj_wait@invalid-wait-zero-handles:
    - shard-snb:          [TIMEOUT][80] ([i915#1958]) -> [PASS][81] +4 similar issues
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-snb4/igt@syncobj_wait@invalid-wait-zero-handles.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-snb4/igt@syncobj_wait@invalid-wait-zero-handles.html

  
#### Warnings ####

  * igt@i915_pm_dc@dc3co-vpb-simulation:
    - shard-iclb:         [SKIP][82] ([i915#588]) -> [SKIP][83] ([i915#658])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-iclb1/igt@i915_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_color_chamelium@pipe-b-ctm-0-5:
    - shard-hsw:          [TIMEOUT][84] ([i915#1958]) -> [SKIP][85] ([fdo#109271] / [fdo#111827])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-hsw8/igt@kms_color_chamelium@pipe-b-ctm-0-5.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-hsw2/igt@kms_color_chamelium@pipe-b-ctm-0-5.html
    - shard-snb:          [TIMEOUT][86] ([i915#1958]) -> [SKIP][87] ([fdo#109271] / [fdo#111827])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-snb4/igt@kms_color_chamelium@pipe-b-ctm-0-5.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-snb6/igt@kms_color_chamelium@pipe-b-ctm-0-5.html

  * igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic:
    - shard-skl:          [DMESG-WARN][88] ([i915#1982]) -> [SKIP][89] ([fdo#109271]) +3 similar issues
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-skl1/igt@kms_cursor_legacy@flip-vs-cursor-crc-atomic.html

  * igt@kms_flip_tiling@flip-changes-tiling-yf:
    - shard-skl:          [DMESG-WARN][90] ([i915#1982]) -> [FAIL][91] ([i915#699])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-skl4/igt@kms_flip_tiling@flip-changes-tiling-yf.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-skl7/igt@kms_flip_tiling@flip-changes-tiling-yf.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt:
    - shard-snb:          [SKIP][92] ([fdo#109271]) -> [TIMEOUT][93] ([i915#1958]) +2 similar issues
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-snb2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-snb2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
    - shard-skl:          [DMESG-FAIL][94] ([fdo#108145] / [i915#1982]) -> [FAIL][95] ([fdo#108145] / [i915#265])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-alpha-7efc.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-alpha-7efc.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
    - shard-skl:          [FAIL][96] ([fdo#108145] / [i915#265]) -> [DMESG-FAIL][97] ([fdo#108145] / [i915#1982])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [SKIP][98] ([fdo#109271]) -> [FAIL][99] ([fdo#108145] / [i915#265])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8856/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#128]: https://gitlab.freedesktop.org/drm/intel/issues/128
  [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
  [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
  [i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#1887]: https://gitlab.freedesktop.org/drm/intel/issues/1887
  [i915#1958]: https://gitlab.freedesktop.org/drm/intel/issues/1958
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2079]: https://gitlab.freedesktop.org/drm/intel/issues/2079
  [i915#2212]: https://gitlab.freedesktop.org/drm/intel/issues/2212
  [i915#2258]: https://gitlab.freedesktop.org/drm/intel/issues/2258
  [i915#2310]: https://gitlab.freedesktop.org/drm/intel/issues/2310
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#42]: https://gitlab.freedesktop.org/drm/intel/issues/42
  [i915#43]: https://gitlab.freedesktop.org/drm/intel/issues/43
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
  [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
  [i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
  [i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53
  [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#699]: https://gitlab.freedesktop.org/drm/intel/issues/699
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#83]: https://gitlab.freedesktop.org/drm/intel/issues/83
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * IGT: IGT_5764 -> IGTPW_4861
  * Linux: CI_DRM_8856 -> Patchwork_18320

  CI-20190529: 20190529
  CI_DRM_8856: 238c742f0beea85fc171bfc3eef05cf284af6d4d @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_4861: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4861/index.html
  IGT_5764: 0f91c80b4c809cf48afff65a2ea68590389aa5ba @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_18320: 4f2669d75a4cad149edc1f11f7dc1c05eb56815e @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18320/index.html

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