From: Uma Shankar <uma.shankar@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [v7 01/10] drm/i915/display: Add HDR Capability detection for LSPCON
Date: Tue, 6 Oct 2020 18:36:45 +0530 [thread overview]
Message-ID: <20201006130654.331-2-uma.shankar@intel.com> (raw)
In-Reply-To: <20201006130654.331-1-uma.shankar@intel.com>
LSPCON firmware exposes HDR capability through LPCON_CAPABILITIES
DPCD register. LSPCON implementations capable of supporting
HDR set HDR_CAPABILITY bit in LSPCON_CAPABILITIES to 1. This patch
reads the same, detects the HDR capability and adds this to
intel_lspcon struct.
v2: Addressed Jani Nikula's review comment and fixed the HDR
capability detection logic
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
.../drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_lspcon.c | 30 +++++++++++++++++++
2 files changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index d5dc18cb8c39..fb8cfc0981d6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1398,6 +1398,7 @@ struct intel_lspcon {
bool active;
enum drm_lspcon_mode mode;
enum lspcon_vendor vendor;
+ bool hdr_supported;
};
struct intel_digital_port {
diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c
index ee95fc353a56..f92962195698 100644
--- a/drivers/gpu/drm/i915/display/intel_lspcon.c
+++ b/drivers/gpu/drm/i915/display/intel_lspcon.c
@@ -35,6 +35,8 @@
#define LSPCON_VENDOR_PARADE_OUI 0x001CF8
#define LSPCON_VENDOR_MCA_OUI 0x0060AD
+#define DPCD_MCA_LSPCON_HDR_STATUS 0x70003
+
/* AUX addresses to write MCA AVI IF */
#define LSPCON_MCA_AVI_IF_WRITE_OFFSET 0x5C0
#define LSPCON_MCA_AVI_IF_CTRL 0x5DF
@@ -104,6 +106,32 @@ static bool lspcon_detect_vendor(struct intel_lspcon *lspcon)
return true;
}
+static void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon)
+{
+ struct intel_digital_port *intel_dig_port =
+ container_of(lspcon, struct intel_digital_port, lspcon);
+ struct drm_device *dev = intel_dig_port->base.base.dev;
+ struct intel_dp *dp = lspcon_to_intel_dp(lspcon);
+ u8 hdr_caps;
+ int ret;
+
+ /* Enable HDR for MCA based LSPCON devices */
+ if (lspcon->vendor == LSPCON_VENDOR_MCA)
+ ret = drm_dp_dpcd_read(&dp->aux, DPCD_MCA_LSPCON_HDR_STATUS,
+ &hdr_caps, 1);
+ else
+ return;
+
+ if (ret < 0) {
+ drm_dbg_kms(dev, "hdr capability detection failed\n");
+ lspcon->hdr_supported = false;
+ return;
+ } else if (hdr_caps & 0x1) {
+ drm_dbg_kms(dev, "lspcon capable of HDR\n");
+ lspcon->hdr_supported = true;
+ }
+}
+
static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon *lspcon)
{
enum drm_lspcon_mode current_mode;
@@ -554,6 +582,8 @@ static bool lspcon_init(struct intel_digital_port *dig_port)
return false;
}
+ lspcon_detect_hdr_capability(lspcon);
+
connector->ycbcr_420_allowed = true;
lspcon->active = true;
DRM_DEBUG_KMS("Success: LSPCON init\n");
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-10-06 12:33 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-06 13:06 [Intel-gfx] [v7 00/10] Enable HDR on MCA LSPCON based Gen9 devices Uma Shankar
2020-10-06 13:06 ` Uma Shankar [this message]
2020-10-08 10:54 ` [Intel-gfx] [v7 01/10] drm/i915/display: Add HDR Capability detection for LSPCON Ville Syrjälä
2020-10-08 11:29 ` Shankar, Uma
2020-10-06 13:06 ` [Intel-gfx] [v7 02/10] drm/i915/display: Enable HDR on gen9 devices with MCA Lspcon Uma Shankar
2020-10-06 13:06 ` [Intel-gfx] [v7 03/10] drm/i915/display: Attach HDR property for capable Gen9 devices Uma Shankar
2020-10-06 13:06 ` [Intel-gfx] [v7 04/10] drm/i915/display: Enable BT2020 for HDR on LSPCON devices Uma Shankar
2020-10-08 11:18 ` Ville Syrjälä
2020-10-06 13:06 ` [Intel-gfx] [v7 05/10] drm/i915/display: Enable HDR for Parade based lspcon Uma Shankar
2020-10-06 13:06 ` [Intel-gfx] [v7 06/10] drm/i915/display: Implement infoframes readback for LSPCON Uma Shankar
2020-10-06 13:06 ` [Intel-gfx] [v7 07/10] drm/i915/display: Implement DRM infoframe read " Uma Shankar
2020-10-06 13:06 ` [Intel-gfx] [v7 08/10] drm/i915/lspcon: Create separate infoframe_enabled helper Uma Shankar
2020-10-06 13:06 ` [Intel-gfx] [v7 09/10] drm/i915/lspcon: Do not send DRM infoframes to non-HDMI sinks Uma Shankar
2020-10-06 13:06 ` [Intel-gfx] [v7 10/10] drm/i915/display: [NOT FOR MERGE] Reduce blanking to support 4k60@10bpp for LSPCON Uma Shankar
2020-10-06 15:00 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable HDR on MCA LSPCON based Gen9 devices (rev7) Patchwork
2020-10-06 15:24 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-06 19:27 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20201006130654.331-2-uma.shankar@intel.com \
--to=uma.shankar@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox