* [Intel-gfx] [PATCH 01/13] drm/i915/hdcp: Update CP property in update_pipe
2020-10-14 4:52 [Intel-gfx] [PATCH 00/13] HDCP 2.2 DP MST Support Anshuman Gupta
@ 2020-10-14 4:52 ` Anshuman Gupta
2020-10-14 4:52 ` [Intel-gfx] [PATCH 02/13] drm/i915/hotplug: Handle CP_IRQ for DP-MST Anshuman Gupta
` (18 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Anshuman Gupta @ 2020-10-14 4:52 UTC (permalink / raw)
To: intel-gfx; +Cc: seanpaul
When crtc state need_modeset is true it is not necessary
it is going to be a real modeset, it can turns to be a
update_pipe instead of modeset.
This turns content protection property to be DESIRED and hdcp
update_pipe left with property to be in DESIRED state but
actually hdcp->value was ENABLED.
This caught with DP MST setup, when disabling HDCP on a connector
sets the crtc state need_modeset to true for all crtc driving
the other DP-MST topology connectors.
Fixes: 33f9a623bfc6 ("drm/i915/hdcp: Update CP as per the kernel internal state")
Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index b2a4bbcfdcd2..cbe3ee661bb7 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -2220,6 +2220,10 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state,
/* Avoid enabling hdcp, if it already ENABLED */
desired_and_not_enabled =
hdcp->value != DRM_MODE_CONTENT_PROTECTION_ENABLED;
+
+ if (!desired_and_not_enabled && !content_protection_type_changed)
+ schedule_work(&hdcp->prop_work);
+
mutex_unlock(&hdcp->mutex);
}
--
2.26.2
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [Intel-gfx] [PATCH 02/13] drm/i915/hotplug: Handle CP_IRQ for DP-MST
2020-10-14 4:52 [Intel-gfx] [PATCH 00/13] HDCP 2.2 DP MST Support Anshuman Gupta
2020-10-14 4:52 ` [Intel-gfx] [PATCH 01/13] drm/i915/hdcp: Update CP property in update_pipe Anshuman Gupta
@ 2020-10-14 4:52 ` Anshuman Gupta
2020-10-14 4:52 ` [Intel-gfx] [PATCH 03/13] drm/i915/hdcp: DP MST transcoder for link and stream Anshuman Gupta
` (17 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Anshuman Gupta @ 2020-10-14 4:52 UTC (permalink / raw)
To: intel-gfx; +Cc: seanpaul
Handle CP_IRQ in DEVICE_SERVICE_IRQ_VECTOR_ESI0
It requires to call intel_hdcp_handle_cp_irq() in case
of CP_IRQ is triggered by a sink in DP-MST topology.
Cc: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4f8266c3ed43..eaa7de044534 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5674,6 +5674,17 @@ static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
"Could not write test response to sink\n");
}
+static void
+intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, bool *handled)
+{
+ drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, handled);
+
+ if (esi[1] & DP_CP_IRQ) {
+ intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
+ *handled = true;
+ }
+}
+
/**
* intel_dp_check_mst_status - service any pending MST interrupts, check link status
* @intel_dp: Intel DP struct
@@ -5718,7 +5729,8 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp)
drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
- drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
+ intel_dp_mst_hpd_irq(intel_dp, esi, &handled);
+
if (!handled)
break;
--
2.26.2
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [Intel-gfx] [PATCH 03/13] drm/i915/hdcp: DP MST transcoder for link and stream
2020-10-14 4:52 [Intel-gfx] [PATCH 00/13] HDCP 2.2 DP MST Support Anshuman Gupta
2020-10-14 4:52 ` [Intel-gfx] [PATCH 01/13] drm/i915/hdcp: Update CP property in update_pipe Anshuman Gupta
2020-10-14 4:52 ` [Intel-gfx] [PATCH 02/13] drm/i915/hotplug: Handle CP_IRQ for DP-MST Anshuman Gupta
@ 2020-10-14 4:52 ` Anshuman Gupta
2020-10-14 4:52 ` [Intel-gfx] [PATCH 04/13] drm/i915/hdcp: Move HDCP enc status timeout to header Anshuman Gupta
` (16 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Anshuman Gupta @ 2020-10-14 4:52 UTC (permalink / raw)
To: intel-gfx; +Cc: seanpaul
Gen12 has H/W delta with respect to HDCP{1.x,2.x} display engine
instances lies in Transcoder instead of DDI as in Gen11.
This requires hdcp driver to use mst_master_transcoder for link
authentication and stream transcoder for stream encryption
separately.
This will be used for both HDCP 1.4 and HDCP 2.2 over DP MST
on Gen12.
Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
.../gpu/drm/i915/display/intel_display_types.h | 2 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 15 +++++++++++----
drivers/gpu/drm/i915/display/intel_hdcp.h | 2 +-
5 files changed, 16 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 35edbd826443..d4c4afcfce99 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4059,7 +4059,7 @@ static void intel_enable_ddi(struct intel_atomic_state *state,
if (conn_state->content_protection ==
DRM_MODE_CONTENT_PROTECTION_DESIRED)
intel_hdcp_enable(to_intel_connector(conn_state->connector),
- crtc_state->cpu_transcoder,
+ crtc_state,
(u8)conn_state->hdcp_content_type);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 0b5df8e44966..bd4cd34d1923 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -432,6 +432,8 @@ struct intel_hdcp {
* Hence caching the transcoder here.
*/
enum transcoder cpu_transcoder;
+ /* Only used for DP MST stream encryption */
+ enum transcoder stream_transcoder;
};
struct intel_connector {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index e948aacbd4ab..23da9902c300 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -568,7 +568,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
if (conn_state->content_protection ==
DRM_MODE_CONTENT_PROTECTION_DESIRED)
intel_hdcp_enable(to_intel_connector(conn_state->connector),
- pipe_config->cpu_transcoder,
+ pipe_config,
(u8)conn_state->hdcp_content_type);
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index cbe3ee661bb7..29ac60d5e70e 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -2095,7 +2095,7 @@ int intel_hdcp_init(struct intel_connector *connector,
}
int intel_hdcp_enable(struct intel_connector *connector,
- enum transcoder cpu_transcoder, u8 content_type)
+ const struct intel_crtc_state *pipe_config, u8 content_type)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
@@ -2111,10 +2111,17 @@ int intel_hdcp_enable(struct intel_connector *connector,
drm_WARN_ON(&dev_priv->drm,
hdcp->value == DRM_MODE_CONTENT_PROTECTION_ENABLED);
hdcp->content_type = content_type;
- hdcp->cpu_transcoder = cpu_transcoder;
+
+ if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST)) {
+ hdcp->cpu_transcoder = pipe_config->mst_master_transcoder;
+ hdcp->stream_transcoder = pipe_config->cpu_transcoder;
+ } else {
+ hdcp->cpu_transcoder = pipe_config->cpu_transcoder;
+ hdcp->stream_transcoder = INVALID_TRANSCODER;
+ }
if (INTEL_GEN(dev_priv) >= 12)
- hdcp->port_data.fw_tc = intel_get_mei_fw_tc(cpu_transcoder);
+ hdcp->port_data.fw_tc = intel_get_mei_fw_tc(hdcp->cpu_transcoder);
/*
* Considering that HDCP2.2 is more secure than HDCP1.4, If the setup
@@ -2229,7 +2236,7 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state,
if (desired_and_not_enabled || content_protection_type_changed)
intel_hdcp_enable(connector,
- crtc_state->cpu_transcoder,
+ crtc_state,
(u8)conn_state->hdcp_content_type);
}
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h
index 1bbf5b67ed0a..bc51c1e9b481 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.h
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
@@ -25,7 +25,7 @@ void intel_hdcp_atomic_check(struct drm_connector *connector,
int intel_hdcp_init(struct intel_connector *connector, enum port port,
const struct intel_hdcp_shim *hdcp_shim);
int intel_hdcp_enable(struct intel_connector *connector,
- enum transcoder cpu_transcoder, u8 content_type);
+ const struct intel_crtc_state *pipe_config, u8 content_type);
int intel_hdcp_disable(struct intel_connector *connector);
void intel_hdcp_update_pipe(struct intel_atomic_state *state,
struct intel_encoder *encoder,
--
2.26.2
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [Intel-gfx] [PATCH 04/13] drm/i915/hdcp: Move HDCP enc status timeout to header
2020-10-14 4:52 [Intel-gfx] [PATCH 00/13] HDCP 2.2 DP MST Support Anshuman Gupta
` (2 preceding siblings ...)
2020-10-14 4:52 ` [Intel-gfx] [PATCH 03/13] drm/i915/hdcp: DP MST transcoder for link and stream Anshuman Gupta
@ 2020-10-14 4:52 ` Anshuman Gupta
2020-10-14 4:52 ` [Intel-gfx] [PATCH 05/13] drm/i915/hdcp: HDCP stream encryption support Anshuman Gupta
` (15 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Anshuman Gupta @ 2020-10-14 4:52 UTC (permalink / raw)
To: intel-gfx; +Cc: seanpaul
DP MST stream encryption status requires time of a link frame
in order to change its status, but as there were some HDCP
encryption timeout observed earlier, it is safer to use
ENCRYPT_STATUS_CHANGE_TIMEOUT_MS timeout for stream status too,
it requires to move the macro to a header.
It will be used by both HDCP{1.x,2.x} stream status timeout.
Related: 7e90e8d0c0ea ("drm/i915: Increase timeout for Encrypt
status change")
Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 9 ++++-----
drivers/gpu/drm/i915/display/intel_hdcp.h | 2 ++
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 29ac60d5e70e..ff9c13bc544b 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -23,7 +23,6 @@
#include "intel_connector.h"
#define KEY_LOAD_TRIES 5
-#define ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
#define HDCP2_LC_RETRY_CNT 3
static
@@ -762,7 +761,7 @@ static int intel_hdcp_auth(struct intel_connector *connector)
if (intel_de_wait_for_set(dev_priv,
HDCP_STATUS(dev_priv, cpu_transcoder, port),
HDCP_STATUS_ENC,
- ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
drm_err(&dev_priv->drm, "Timed out waiting for encryption\n");
return -ETIMEDOUT;
}
@@ -809,7 +808,7 @@ static int _intel_hdcp_disable(struct intel_connector *connector)
intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), 0);
if (intel_de_wait_for_clear(dev_priv,
HDCP_STATUS(dev_priv, cpu_transcoder, port),
- ~0, ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ ~0, HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
drm_err(&dev_priv->drm,
"Failed to disable HDCP, timeout clearing status\n");
return -ETIMEDOUT;
@@ -1641,7 +1640,7 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
HDCP2_STATUS(dev_priv, cpu_transcoder,
port),
LINK_ENCRYPTION_STATUS,
- ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
return ret;
}
@@ -1665,7 +1664,7 @@ static int hdcp2_disable_encryption(struct intel_connector *connector)
HDCP2_STATUS(dev_priv, cpu_transcoder,
port),
LINK_ENCRYPTION_STATUS,
- ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
if (ret == -ETIMEDOUT)
drm_dbg_kms(&dev_priv->drm, "Disable Encryption Timedout");
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h
index bc51c1e9b481..b912a3a0f5b8 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.h
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
@@ -8,6 +8,8 @@
#include <linux/types.h>
+#define HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
+
struct drm_connector;
struct drm_connector_state;
struct drm_i915_private;
--
2.26.2
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [Intel-gfx] [PATCH 05/13] drm/i915/hdcp: HDCP stream encryption support
2020-10-14 4:52 [Intel-gfx] [PATCH 00/13] HDCP 2.2 DP MST Support Anshuman Gupta
` (3 preceding siblings ...)
2020-10-14 4:52 ` [Intel-gfx] [PATCH 04/13] drm/i915/hdcp: Move HDCP enc status timeout to header Anshuman Gupta
@ 2020-10-14 4:52 ` Anshuman Gupta
2020-10-14 4:52 ` [Intel-gfx] [PATCH 06/13] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support Anshuman Gupta
` (14 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Anshuman Gupta @ 2020-10-14 4:52 UTC (permalink / raw)
To: intel-gfx; +Cc: seanpaul
Both HDCP_{1.x,2.x} requires to select/deselect Multistream HDCP bit
in TRANS_DDI_FUNC_CTL in order to enable/disable stream HDCP
encryption over DP MST Transport Link.
HDCP 1.4 stream encryption requires to validate the stream encryption
status in HDCP_STATUS_{TRANSCODER,PORT} register driving that link
in order to enable/disable the stream encryption.
Both of above requirement are same for all Gen with respect to
B.Spec Documentation.
Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 10 +--
drivers/gpu/drm/i915/display/intel_ddi.h | 6 +-
.../drm/i915/display/intel_display_types.h | 4 +
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 80 ++++++++++++++++---
drivers/gpu/drm/i915/display/intel_hdmi.c | 14 ++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
6 files changed, 90 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index d4c4afcfce99..c3de4afc1fc4 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1948,9 +1948,9 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state
}
}
-int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
- enum transcoder cpu_transcoder,
- bool enable)
+int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
+ enum transcoder cpu_transcoder,
+ bool enable, u32 hdcp_mask)
{
struct drm_device *dev = intel_encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -1965,9 +1965,9 @@ int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
if (enable)
- tmp |= TRANS_DDI_HDCP_SIGNALLING;
+ tmp |= hdcp_mask;
else
- tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
+ tmp &= ~hdcp_mask;
intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp);
intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
index dcc711cfe4fe..a4dd815c0000 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -50,9 +50,9 @@ u32 bxt_signal_levels(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
u32 ddi_signal_levels(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
-int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
- enum transcoder cpu_transcoder,
- bool enable);
+int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
+ enum transcoder cpu_transcoder,
+ bool enable, u32 hdcp_mask);
void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder);
#endif /* __INTEL_DDI_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index bd4cd34d1923..83a9690964a1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -339,6 +339,10 @@ struct intel_hdcp_shim {
enum transcoder cpu_transcoder,
bool enable);
+ /* Enable/Disable stream encryption on DP MST Transport Link */
+ int (*stream_encryption)(struct intel_digital_port *dig_port,
+ bool enable);
+
/* Ensures the link is still protected */
bool (*check_link)(struct intel_digital_port *dig_port,
struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 03424d20e9f7..652d4645f255 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -16,6 +16,30 @@
#include "intel_dp.h"
#include "intel_hdcp.h"
+static unsigned int transcoder_to_stream_enc_status(enum transcoder cpu_transcoder)
+{
+ u32 stream_enc_mask;
+
+ switch (cpu_transcoder) {
+ case TRANSCODER_A:
+ stream_enc_mask = HDCP_STATUS_STREAM_A_ENC;
+ break;
+ case TRANSCODER_B:
+ stream_enc_mask = HDCP_STATUS_STREAM_B_ENC;
+ break;
+ case TRANSCODER_C:
+ stream_enc_mask = HDCP_STATUS_STREAM_C_ENC;
+ break;
+ case TRANSCODER_D:
+ stream_enc_mask = HDCP_STATUS_STREAM_D_ENC;
+ break;
+ default:
+ stream_enc_mask = 0;
+ }
+
+ return stream_enc_mask;
+}
+
static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
{
long ret;
@@ -622,24 +646,57 @@ static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
};
static int
-intel_dp_mst_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
- enum transcoder cpu_transcoder,
- bool enable)
+intel_dp_mst_toggle_select_hdcp_stream(struct intel_digital_port *dig_port,
+ bool enable)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_dp *dp = &dig_port->dp;
+ struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
int ret;
- if (!enable)
- usleep_range(6, 60); /* Bspec says >= 6us */
-
- ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base,
- cpu_transcoder, enable);
+ ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
+ hdcp->stream_transcoder, enable,
+ TRANS_DDI_HDCP_SELECT);
if (ret)
- drm_dbg_kms(&i915->drm, "%s HDCP signalling failed (%d)\n",
- enable ? "Enable" : "Disable", ret);
+ drm_err(&i915->drm, "%s Multistream HDCP select failed (%d)\n",
+ enable ? "Enable" : "Disable", ret);
return ret;
}
+static int
+intel_dp_mst_hdcp_strem_encryption(struct intel_digital_port *dig_port,
+ bool enable)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_dp *dp = &dig_port->dp;
+ struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
+ enum port port = dig_port->base.port;
+ enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
+ u32 stream_enc_status;
+ int ret;
+
+ ret = intel_dp_mst_toggle_select_hdcp_stream(dig_port, enable);
+ if (ret)
+ return ret;
+
+ stream_enc_status = transcoder_to_stream_enc_status(hdcp->stream_transcoder);
+ if (!stream_enc_status)
+ return -EINVAL;
+
+ /* Wait for encryption confirmation */
+ if (intel_de_wait_for_register(i915,
+ HDCP_STATUS(i915, cpu_transcoder, port),
+ stream_enc_status,
+ enable ? stream_enc_status : 0,
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ drm_err(&i915->drm, "Timed out waiting for stream encryption %s\n",
+ enable ? "enabled" : "disabled");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
static
bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
struct intel_connector *connector)
@@ -673,7 +730,8 @@ static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
.read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
.read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
.read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
- .toggle_signalling = intel_dp_mst_hdcp_toggle_signalling,
+ .toggle_signalling = intel_dp_hdcp_toggle_signalling,
+ .stream_encryption = intel_dp_mst_hdcp_strem_encryption,
.check_link = intel_dp_mst_hdcp_check_link,
.hdcp_capable = intel_dp_hdcp_capable,
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index f90838bc74fb..f58469226694 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1495,15 +1495,16 @@ static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
usleep_range(25, 50);
}
- ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
- false);
+ ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
+ false, TRANS_DDI_HDCP_SIGNALLING);
if (ret) {
drm_err(&dev_priv->drm,
"Disable HDCP signalling failed (%d)\n", ret);
return ret;
}
- ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
- true);
+
+ ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
+ true, TRANS_DDI_HDCP_SIGNALLING);
if (ret) {
drm_err(&dev_priv->drm,
"Enable HDCP signalling failed (%d)\n", ret);
@@ -1526,8 +1527,9 @@ int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
if (!enable)
usleep_range(6, 60); /* Bspec says >= 6us */
- ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, cpu_transcoder,
- enable);
+ ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
+ cpu_transcoder, enable,
+ TRANS_DDI_HDCP_SIGNALLING);
if (ret) {
drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
enable ? "Enable" : "Disable", ret);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 04c966a524ce..050d7307ebc4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9939,6 +9939,7 @@ enum skl_power_gate {
#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1 << 8)
#define TRANS_DDI_HDMI_SCRAMBLER_CTS_ENABLE (1 << 7)
#define TRANS_DDI_HDMI_SCRAMBLER_RESET_FREQ (1 << 6)
+#define TRANS_DDI_HDCP_SELECT REG_BIT(5)
#define TRANS_DDI_BFI_ENABLE (1 << 4)
#define TRANS_DDI_HIGH_TMDS_CHAR_RATE (1 << 4)
#define TRANS_DDI_HDMI_SCRAMBLING (1 << 0)
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [Intel-gfx] [PATCH 06/13] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support
2020-10-14 4:52 [Intel-gfx] [PATCH 00/13] HDCP 2.2 DP MST Support Anshuman Gupta
` (4 preceding siblings ...)
2020-10-14 4:52 ` [Intel-gfx] [PATCH 05/13] drm/i915/hdcp: HDCP stream encryption support Anshuman Gupta
@ 2020-10-14 4:52 ` Anshuman Gupta
2020-10-14 4:52 ` [Intel-gfx] [PATCH 07/13] drm/i915/hdcp: Pass dig_port to intel_hdcp_init Anshuman Gupta
` (13 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Anshuman Gupta @ 2020-10-14 4:52 UTC (permalink / raw)
To: intel-gfx; +Cc: seanpaul
Enable HDCP 1.4 over DP MST for Gen12.
This also enable the stream encryption support for
older generations, which was missing earlier.
v2:
- Added debug print for stream encryption.
- Disable the hdcp on port after disabling last stream
encryption.
Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 10 ++---
drivers/gpu/drm/i915/display/intel_hdcp.c | 46 ++++++++++++++-------
2 files changed, 35 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 23da9902c300..5a6dd35c1663 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -826,13 +826,9 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo
intel_attach_force_audio_property(connector);
intel_attach_broadcast_rgb_property(connector);
-
- /* TODO: Figure out how to make HDCP work on GEN12+ */
- if (INTEL_GEN(dev_priv) < 12) {
- ret = intel_dp_init_hdcp(dig_port, intel_connector);
- if (ret)
- DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
- }
+ ret = intel_dp_init_hdcp(dig_port, intel_connector);
+ if (ret)
+ drm_dbg_kms(&dev_priv->drm, "HDCP init failed, skipping.\n");
/*
* Reuse the prop from the SST connector because we're
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index ff9c13bc544b..636e08b3c0ac 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -612,7 +612,12 @@ int intel_hdcp_auth_downstream(struct intel_connector *connector)
return ret;
}
-/* Implements Part 1 of the HDCP authorization procedure */
+/*
+ * Implements Part 1 of the HDCP authorization procedure.
+ * Authentication Part 1 steps for Multi-stream DisplayPort.
+ * Step 1. Auth Part 1 sequence on the driving MST Trasport Link.
+ * Step 2. Enable encryption for each stream that requires encryption.
+ */
static int intel_hdcp_auth(struct intel_connector *connector)
{
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
@@ -766,10 +771,16 @@ static int intel_hdcp_auth(struct intel_connector *connector)
return -ETIMEDOUT;
}
- /*
- * XXX: If we have MST-connected devices, we need to enable encryption
- * on those as well.
- */
+ /* DP MST Auth Part 1 Step 2.a and Step 2.b */
+ if (shim->stream_encryption) {
+ ret = shim->stream_encryption(dig_port, true);
+ if (ret) {
+ drm_err(&dev_priv->drm, "Failed to enable HDCP 1.4 stream enc\n");
+ return ret;
+ }
+ drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 tras %s stream encrypted\n",
+ transcoder_name(hdcp->stream_transcoder));
+ }
if (repeater_present)
return intel_hdcp_auth_downstream(connector);
@@ -790,19 +801,26 @@ static int _intel_hdcp_disable(struct intel_connector *connector)
drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP is being disabled...\n",
connector->base.name, connector->base.base.id);
+ /*
+ * Step 1: Deselect HDCP Multiplestream Bit.
+ * Step 2: poll for stream encryption status to be disable.
+ */
+ if (hdcp->shim->stream_encryption) {
+ ret = hdcp->shim->stream_encryption(dig_port, false);
+ if (ret) {
+ drm_err(&dev_priv->drm, "Failed to disable HDCP 1.4 stream enc\n");
+ return ret;
+ }
+ drm_dbg_kms(&dev_priv->drm, "HDCP 1.4 trans %s stream encryption disabled\n",
+ transcoder_name(hdcp->stream_transcoder));
+ }
/*
- * If there are other connectors on this port using HDCP, don't disable
- * it. Instead, toggle the HDCP signalling off on that particular
- * connector/pipe and exit.
+ * If there are other connectors on this port using HDCP, don't disable it.
+ * Repeat steps 1-2 for each stream that no longer requires encryption.
*/
- if (dig_port->num_hdcp_streams > 0) {
- ret = hdcp->shim->toggle_signalling(dig_port,
- cpu_transcoder, false);
- if (ret)
- DRM_ERROR("Failed to disable HDCP signalling\n");
+ if (dig_port->num_hdcp_streams > 0)
return ret;
- }
hdcp->hdcp_encrypted = false;
intel_de_write(dev_priv, HDCP_CONF(dev_priv, cpu_transcoder, port), 0);
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [Intel-gfx] [PATCH 07/13] drm/i915/hdcp: Pass dig_port to intel_hdcp_init
2020-10-14 4:52 [Intel-gfx] [PATCH 00/13] HDCP 2.2 DP MST Support Anshuman Gupta
` (5 preceding siblings ...)
2020-10-14 4:52 ` [Intel-gfx] [PATCH 06/13] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support Anshuman Gupta
@ 2020-10-14 4:52 ` Anshuman Gupta
2020-10-14 4:52 ` [Intel-gfx] [PATCH 08/13] drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port Anshuman Gupta
` (12 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Anshuman Gupta @ 2020-10-14 4:52 UTC (permalink / raw)
To: intel-gfx; +Cc: seanpaul
Pass dig_port as an argument to intel_hdcp_init()
and intel_hdcp2_init().
This will be required for HDCP 2.2 stream encryption.
Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 4 ++--
drivers/gpu/drm/i915/display/intel_hdcp.c | 12 +++++++-----
drivers/gpu/drm/i915/display/intel_hdcp.h | 4 +++-
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
4 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 652d4645f255..384e384cb9e2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -751,10 +751,10 @@ int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
return 0;
if (intel_connector->mst_port)
- return intel_hdcp_init(intel_connector, port,
+ return intel_hdcp_init(intel_connector, dig_port,
&intel_dp_mst_hdcp_shim);
else if (!intel_dp_is_edp(intel_dp))
- return intel_hdcp_init(intel_connector, port,
+ return intel_hdcp_init(intel_connector, dig_port,
&intel_dp_hdcp_shim);
return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 636e08b3c0ac..a48765e5e783 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1985,12 +1985,13 @@ static enum mei_fw_tc intel_get_mei_fw_tc(enum transcoder cpu_transcoder)
}
static int initialize_hdcp_port_data(struct intel_connector *connector,
- enum port port,
+ struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *shim)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
struct hdcp_port_data *data = &hdcp->port_data;
+ enum port port = dig_port->base.port;
if (INTEL_GEN(dev_priv) < 12)
data->fw_ddi = intel_get_mei_fw_ddi_index(port);
@@ -2063,14 +2064,15 @@ void intel_hdcp_component_init(struct drm_i915_private *dev_priv)
}
}
-static void intel_hdcp2_init(struct intel_connector *connector, enum port port,
+static void intel_hdcp2_init(struct intel_connector *connector,
+ struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *shim)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
int ret;
- ret = initialize_hdcp_port_data(connector, port, shim);
+ ret = initialize_hdcp_port_data(connector, dig_port, shim);
if (ret) {
drm_dbg_kms(&i915->drm, "Mei hdcp data init failed\n");
return;
@@ -2080,7 +2082,7 @@ static void intel_hdcp2_init(struct intel_connector *connector, enum port port,
}
int intel_hdcp_init(struct intel_connector *connector,
- enum port port,
+ struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *shim)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
@@ -2091,7 +2093,7 @@ int intel_hdcp_init(struct intel_connector *connector,
return -EINVAL;
if (is_hdcp2_supported(dev_priv) && !connector->mst_port)
- intel_hdcp2_init(connector, port, shim);
+ intel_hdcp2_init(connector, dig_port, shim);
ret =
drm_connector_attach_content_protection_property(&connector->base,
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h
index b912a3a0f5b8..8f53b0c7fe5c 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.h
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
@@ -18,13 +18,15 @@ struct intel_connector;
struct intel_crtc_state;
struct intel_encoder;
struct intel_hdcp_shim;
+struct intel_digital_port;
enum port;
enum transcoder;
void intel_hdcp_atomic_check(struct drm_connector *connector,
struct drm_connector_state *old_state,
struct drm_connector_state *new_state);
-int intel_hdcp_init(struct intel_connector *connector, enum port port,
+int intel_hdcp_init(struct intel_connector *connector,
+ struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *hdcp_shim);
int intel_hdcp_enable(struct intel_connector *connector,
const struct intel_crtc_state *pipe_config, u8 content_type);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index f58469226694..0788de04711b 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3302,7 +3302,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
intel_hdmi->attached_connector = intel_connector;
if (is_hdcp_supported(dev_priv, port)) {
- int ret = intel_hdcp_init(intel_connector, port,
+ int ret = intel_hdcp_init(intel_connector, dig_port,
&intel_hdmi_hdcp_shim);
if (ret)
drm_dbg_kms(&dev_priv->drm,
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [Intel-gfx] [PATCH 08/13] drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port
2020-10-14 4:52 [Intel-gfx] [PATCH 00/13] HDCP 2.2 DP MST Support Anshuman Gupta
` (6 preceding siblings ...)
2020-10-14 4:52 ` [Intel-gfx] [PATCH 07/13] drm/i915/hdcp: Pass dig_port to intel_hdcp_init Anshuman Gupta
@ 2020-10-14 4:52 ` Anshuman Gupta
2020-10-14 4:52 ` [Intel-gfx] [PATCH 09/13] drm/i915/hdcp: mst streams support in hdcp port_data Anshuman Gupta
` (11 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Anshuman Gupta @ 2020-10-14 4:52 UTC (permalink / raw)
To: intel-gfx; +Cc: seanpaul
hdcp_port_data is specific to a port on which HDCP
encryption is getting enabled, so encapsulate it to
intel_digital_port.
This will be required to enable HDCP 2.2 stream encryption.
Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
.../drm/i915/display/intel_display_types.h | 5 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 58 ++++++++++++-------
2 files changed, 39 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 83a9690964a1..6633a546449d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -402,7 +402,6 @@ struct intel_hdcp {
* content can flow only through a link protected by HDCP2.2.
*/
u8 content_type;
- struct hdcp_port_data port_data;
bool is_paired;
bool is_repeater;
@@ -1447,10 +1446,12 @@ struct intel_digital_port {
enum phy_fia tc_phy_fia;
u8 tc_phy_fia_idx;
- /* protects num_hdcp_streams reference count */
+ /* protects num_hdcp_streams reference count, port_data */
struct mutex hdcp_mutex;
/* the number of pipes using HDCP signalling out of this port */
unsigned int num_hdcp_streams;
+ /* HDCP port data need to pass to security f/w */
+ struct hdcp_port_data port_data;
void (*write_infoframe)(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index a48765e5e783..1a6ac24efe2d 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -15,6 +15,7 @@
#include <drm/drm_hdcp.h>
#include <drm/i915_component.h>
+#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_display_power.h"
#include "intel_display_types.h"
@@ -1031,7 +1032,8 @@ static int
hdcp2_prepare_ake_init(struct intel_connector *connector,
struct hdcp2_ake_init *ake_data)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1060,7 +1062,8 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector,
struct hdcp2_ake_no_stored_km *ek_pub_km,
size_t *msg_sz)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1087,7 +1090,8 @@ hdcp2_verify_rx_cert_prepare_km(struct intel_connector *connector,
static int hdcp2_verify_hprime(struct intel_connector *connector,
struct hdcp2_ake_send_hprime *rx_hprime)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1112,7 +1116,8 @@ static int
hdcp2_store_pairing_info(struct intel_connector *connector,
struct hdcp2_ake_send_pairing_info *pairing_info)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1138,7 +1143,8 @@ static int
hdcp2_prepare_lc_init(struct intel_connector *connector,
struct hdcp2_lc_init *lc_init)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1164,7 +1170,8 @@ static int
hdcp2_verify_lprime(struct intel_connector *connector,
struct hdcp2_lc_send_lprime *rx_lprime)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1189,7 +1196,8 @@ hdcp2_verify_lprime(struct intel_connector *connector,
static int hdcp2_prepare_skey(struct intel_connector *connector,
struct hdcp2_ske_send_eks *ske_data)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1217,7 +1225,8 @@ hdcp2_verify_rep_topology_prepare_ack(struct intel_connector *connector,
*rep_topology,
struct hdcp2_rep_send_ack *rep_send_ack)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1245,7 +1254,8 @@ static int
hdcp2_verify_mprime(struct intel_connector *connector,
struct hdcp2_rep_stream_ready *stream_ready)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1268,7 +1278,8 @@ hdcp2_verify_mprime(struct intel_connector *connector,
static int hdcp2_authenticate_port(struct intel_connector *connector)
{
- struct hdcp_port_data *data = &connector->hdcp.port_data;
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1292,6 +1303,7 @@ static int hdcp2_authenticate_port(struct intel_connector *connector)
static int hdcp2_close_mei_session(struct intel_connector *connector)
{
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
struct i915_hdcp_comp_master *comp;
int ret;
@@ -1305,7 +1317,7 @@ static int hdcp2_close_mei_session(struct intel_connector *connector)
}
ret = comp->ops->close_hdcp_session(comp->mei_dev,
- &connector->hdcp.port_data);
+ &dig_port->port_data);
mutex_unlock(&dev_priv->hdcp_comp_mutex);
return ret;
@@ -1498,8 +1510,9 @@ int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
if (ret < 0)
goto out;
- hdcp->port_data.seq_num_m = hdcp->seq_num_m;
- hdcp->port_data.streams[0].stream_type = hdcp->content_type;
+ dig_port->port_data.seq_num_m = hdcp->seq_num_m;
+ dig_port->port_data.streams[0].stream_type = hdcp->content_type;
+
ret = hdcp2_verify_mprime(connector, &msgs.stream_ready);
out:
@@ -1731,7 +1744,9 @@ hdcp2_propagate_stream_management_info(struct intel_connector *connector)
static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
{
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct intel_hdcp *hdcp = &connector->hdcp;
int ret, i, tries = 3;
@@ -1745,8 +1760,7 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
ret);
break;
}
- hdcp->port_data.streams[0].stream_type =
- hdcp->content_type;
+ data->streams[0].stream_type = hdcp->content_type;
ret = hdcp2_authenticate_port(connector);
if (!ret)
break;
@@ -1989,8 +2003,8 @@ static int initialize_hdcp_port_data(struct intel_connector *connector,
const struct intel_hdcp_shim *shim)
{
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct intel_hdcp *hdcp = &connector->hdcp;
- struct hdcp_port_data *data = &hdcp->port_data;
enum port port = dig_port->base.port;
if (INTEL_GEN(dev_priv) < 12)
@@ -2012,16 +2026,15 @@ static int initialize_hdcp_port_data(struct intel_connector *connector,
data->port_type = (u8)HDCP_PORT_TYPE_INTEGRATED;
data->protocol = (u8)shim->protocol;
- data->k = 1;
if (!data->streams)
- data->streams = kcalloc(data->k,
+ data->streams = kcalloc(INTEL_NUM_PIPES(dev_priv),
sizeof(struct hdcp2_streamid_type),
GFP_KERNEL);
if (!data->streams) {
drm_err(&dev_priv->drm, "Out of Memory\n");
return -ENOMEM;
}
-
+ /* For SST */
data->streams[0].stream_id = 0;
data->streams[0].stream_type = hdcp->content_type;
@@ -2100,7 +2113,7 @@ int intel_hdcp_init(struct intel_connector *connector,
hdcp->hdcp2_supported);
if (ret) {
hdcp->hdcp2_supported = false;
- kfree(hdcp->port_data.streams);
+ kfree(dig_port->port_data.streams);
return ret;
}
@@ -2140,7 +2153,7 @@ int intel_hdcp_enable(struct intel_connector *connector,
}
if (INTEL_GEN(dev_priv) >= 12)
- hdcp->port_data.fw_tc = intel_get_mei_fw_tc(hdcp->cpu_transcoder);
+ dig_port->port_data.fw_tc = intel_get_mei_fw_tc(hdcp->cpu_transcoder);
/*
* Considering that HDCP2.2 is more secure than HDCP1.4, If the setup
@@ -2275,6 +2288,7 @@ void intel_hdcp_component_fini(struct drm_i915_private *dev_priv)
void intel_hdcp_cleanup(struct intel_connector *connector)
{
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct intel_hdcp *hdcp = &connector->hdcp;
if (!hdcp->shim)
@@ -2305,7 +2319,7 @@ void intel_hdcp_cleanup(struct intel_connector *connector)
drm_WARN_ON(connector->base.dev, work_pending(&hdcp->prop_work));
mutex_lock(&hdcp->mutex);
- kfree(hdcp->port_data.streams);
+ kfree(dig_port->port_data.streams);
hdcp->shim = NULL;
mutex_unlock(&hdcp->mutex);
}
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [Intel-gfx] [PATCH 09/13] drm/i915/hdcp: mst streams support in hdcp port_data
2020-10-14 4:52 [Intel-gfx] [PATCH 00/13] HDCP 2.2 DP MST Support Anshuman Gupta
` (7 preceding siblings ...)
2020-10-14 4:52 ` [Intel-gfx] [PATCH 08/13] drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port Anshuman Gupta
@ 2020-10-14 4:52 ` Anshuman Gupta
2020-10-19 10:20 ` Anshuman Gupta
2020-10-14 4:52 ` [Intel-gfx] [PATCH 10/13] drm/i915/hdcp: Pass connector to check_2_2_link Anshuman Gupta
` (10 subsequent siblings)
19 siblings, 1 reply; 27+ messages in thread
From: Anshuman Gupta @ 2020-10-14 4:52 UTC (permalink / raw)
To: intel-gfx; +Cc: seanpaul
Add support for multiple mst stream in hdcp port data
which will be used by RepeaterAuthStreamManage msg and
HDCP 2.2 security f/w for m' validation.
security f/w enforce a policy to do RepeaterAuthStreamManage
management only once with established HDCP session with
all available streams in DP MST topology. This requires
to do the stream management for each connector in DP MST
topology.
Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
.../drm/i915/display/intel_display_types.h | 4 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 85 ++++++++++++++++---
drivers/misc/mei/hdcp/mei_hdcp.c | 3 +-
include/drm/drm_hdcp.h | 8 +-
4 files changed, 80 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 6633a546449d..79750daa83aa 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1446,10 +1446,12 @@ struct intel_digital_port {
enum phy_fia tc_phy_fia;
u8 tc_phy_fia_idx;
- /* protects num_hdcp_streams reference count, port_data */
+ /* protects num_hdcp_streams reference count, port_data and port_auth */
struct mutex hdcp_mutex;
/* the number of pipes using HDCP signalling out of this port */
unsigned int num_hdcp_streams;
+ /* port HDCP auth status */
+ bool port_auth;
/* HDCP port data need to pass to security f/w */
struct hdcp_port_data port_data;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 1a6ac24efe2d..b36b87941c1a 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -26,6 +26,50 @@
#define KEY_LOAD_TRIES 5
#define HDCP2_LC_RETRY_CNT 3
+static int intel_conn_to_vcpi(struct intel_connector *connector)
+{
+ /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
+ return connector->port ? connector->port->vcpi.vcpi : 0;
+}
+
+static void
+intel_hdcp_required_content_stream(struct intel_digital_port *dig_port)
+{
+ struct drm_connector_list_iter conn_iter;
+ struct intel_digital_port *conn_dig_port;
+ struct intel_connector *connector;
+ struct intel_hdcp *hdcp;
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct hdcp_port_data *data = &dig_port->port_data;
+ bool enforce_type0 = false;
+
+ if (dig_port->port_auth)
+ return;
+
+ drm_connector_list_iter_begin(&i915->drm, &conn_iter);
+ for_each_intel_connector_iter(connector, &conn_iter) {
+ if (connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort)
+ continue;
+
+ conn_dig_port = intel_attached_dig_port(connector);
+ if (conn_dig_port != dig_port)
+ continue;
+
+ if (connector->base.status == connector_status_disconnected)
+ continue;
+
+ hdcp = &connector->hdcp;
+ if (hdcp->content_type && !intel_hdcp2_capable(connector))
+ enforce_type0 = true;
+
+ data->streams[data->k].stream_type =
+ enforce_type0 ? DRM_MODE_HDCP_CONTENT_TYPE1 : hdcp->content_type;
+ data->streams[data->k].stream_id = intel_conn_to_vcpi(connector);
+ data->k++;
+ }
+ drm_connector_list_iter_end(&conn_iter);
+}
+
static
bool intel_hdcp_is_ksv_valid(u8 *ksv)
{
@@ -1296,6 +1340,7 @@ static int hdcp2_authenticate_port(struct intel_connector *connector)
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Enable hdcp auth failed. %d\n",
ret);
+
mutex_unlock(&dev_priv->hdcp_comp_mutex);
return ret;
@@ -1477,13 +1522,14 @@ static
int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
{
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct intel_hdcp *hdcp = &connector->hdcp;
union {
struct hdcp2_rep_stream_manage stream_manage;
struct hdcp2_rep_stream_ready stream_ready;
} msgs;
const struct intel_hdcp_shim *shim = hdcp->shim;
- int ret;
+ int ret, streams_size_delta, i;
if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX)
return -ERANGE;
@@ -1493,15 +1539,18 @@ int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
drm_hdcp_cpu_to_be24(msgs.stream_manage.seq_num_m, hdcp->seq_num_m);
/* K no of streams is fixed as 1. Stored as big-endian. */
- msgs.stream_manage.k = cpu_to_be16(1);
+ msgs.stream_manage.k = cpu_to_be16(data->k);
- /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
- msgs.stream_manage.streams[0].stream_id = 0;
- msgs.stream_manage.streams[0].stream_type = hdcp->content_type;
+ for (i = 0; i < data->k; i++) {
+ msgs.stream_manage.streams[i].stream_id = data->streams[i].stream_id;
+ msgs.stream_manage.streams[i].stream_type = data->streams[i].stream_type;
+ }
+ streams_size_delta = HDCP_2_2_MAX_CONTENT_STREAMS_CNT *
+ sizeof(struct hdcp2_streamid_type) - data->k * sizeof(struct hdcp2_streamid_type);
/* Send it to Repeater */
ret = shim->write_2_2_msg(dig_port, &msgs.stream_manage,
- sizeof(msgs.stream_manage));
+ sizeof(msgs.stream_manage) - streams_size_delta);
if (ret < 0)
goto out;
@@ -1510,8 +1559,7 @@ int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
if (ret < 0)
goto out;
- dig_port->port_data.seq_num_m = hdcp->seq_num_m;
- dig_port->port_data.streams[0].stream_type = hdcp->content_type;
+ data->seq_num_m = hdcp->seq_num_m;
ret = hdcp2_verify_mprime(connector, &msgs.stream_ready);
@@ -1672,6 +1720,7 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
port),
LINK_ENCRYPTION_STATUS,
HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
+ dig_port->port_auth = true;
return ret;
}
@@ -1746,11 +1795,9 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
{
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
- struct hdcp_port_data *data = &dig_port->port_data;
- struct intel_hdcp *hdcp = &connector->hdcp;
- int ret, i, tries = 3;
+ int ret = 0, i, tries = 3;
- for (i = 0; i < tries; i++) {
+ for (i = 0; i < tries && !dig_port->port_auth; i++) {
ret = hdcp2_authenticate_sink(connector);
if (!ret) {
ret = hdcp2_propagate_stream_management_info(connector);
@@ -1760,7 +1807,7 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
ret);
break;
}
- data->streams[0].stream_type = hdcp->content_type;
+
ret = hdcp2_authenticate_port(connector);
if (!ret)
break;
@@ -1795,7 +1842,9 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
static int _intel_hdcp2_enable(struct intel_connector *connector)
{
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct intel_hdcp *hdcp = &connector->hdcp;
int ret;
@@ -1803,6 +1852,12 @@ static int _intel_hdcp2_enable(struct intel_connector *connector)
connector->base.name, connector->base.base.id,
hdcp->content_type);
+ /* Stream which requires encryption */
+ intel_hdcp_required_content_stream(dig_port);
+
+ if (drm_WARN_ON(&i915->drm, data->k > INTEL_NUM_PIPES(i915)))
+ return -EINVAL;
+
ret = hdcp2_authenticate_and_encrypt(connector);
if (ret) {
drm_dbg_kms(&i915->drm, "HDCP2 Type%d Enabling Failed. (%d)\n",
@@ -1820,7 +1875,9 @@ static int _intel_hdcp2_enable(struct intel_connector *connector)
static int _intel_hdcp2_disable(struct intel_connector *connector)
{
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct hdcp_port_data *data = &dig_port->port_data;
int ret;
drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is being Disabled\n",
@@ -1832,6 +1889,8 @@ static int _intel_hdcp2_disable(struct intel_connector *connector)
drm_dbg_kms(&i915->drm, "Port deauth failed.\n");
connector->hdcp.hdcp2_encrypted = false;
+ dig_port->port_auth = false;
+ data->k = 0;
return ret;
}
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index 9ae9669e46ea..b10d266fb60a 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -569,8 +569,7 @@ static int mei_hdcp_verify_mprime(struct device *dev,
verify_mprime_in->header.api_version = HDCP_API_VERSION;
verify_mprime_in->header.command_id = WIRED_REPEATER_AUTH_STREAM_REQ;
verify_mprime_in->header.status = ME_HDCP_STATUS_SUCCESS;
- verify_mprime_in->header.buffer_len =
- WIRED_CMD_BUF_LEN_REPEATER_AUTH_STREAM_REQ_MIN_IN;
+ verify_mprime_in->header.buffer_len = cmd_size - sizeof(struct hdcp_cmd_header);
verify_mprime_in->port.integrated_port_type = data->port_type;
verify_mprime_in->port.physical_port = (u8)data->fw_ddi;
diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
index fe58dbb46962..c8a37bb406b2 100644
--- a/include/drm/drm_hdcp.h
+++ b/include/drm/drm_hdcp.h
@@ -101,11 +101,11 @@
/* Following Macros take a byte at a time for bit(s) masking */
/*
- * TODO: This has to be changed for DP MST, as multiple stream on
- * same port is possible.
- * For HDCP2.2 on HDMI and DP SST this value is always 1.
+ * TODO: This is based upon actual H/W MST streams capacity.
+ *
+ * This is should be moved out to platform specific header.
*/
-#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1
+#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 4
#define HDCP_2_2_TXCAP_MASK_LEN 2
#define HDCP_2_2_RXCAPS_LEN 3
#define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0))
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [Intel-gfx] [PATCH 09/13] drm/i915/hdcp: mst streams support in hdcp port_data
2020-10-14 4:52 ` [Intel-gfx] [PATCH 09/13] drm/i915/hdcp: mst streams support in hdcp port_data Anshuman Gupta
@ 2020-10-19 10:20 ` Anshuman Gupta
2020-10-20 8:31 ` Jani Nikula
0 siblings, 1 reply; 27+ messages in thread
From: Anshuman Gupta @ 2020-10-19 10:20 UTC (permalink / raw)
To: intel-gfx; +Cc: seanpaul
Add support for multiple mst stream in hdcp port data
which will be used by RepeaterAuthStreamManage msg and
HDCP 2.2 security f/w for m' validation.
v2:
Init the hdcp port data k for HDMI/DP SST strem.
Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
.../drm/i915/display/intel_display_types.h | 4 +-
drivers/gpu/drm/i915/display/intel_hdcp.c | 92 ++++++++++++++++---
drivers/misc/mei/hdcp/mei_hdcp.c | 3 +-
include/drm/drm_hdcp.h | 8 +-
4 files changed, 87 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 6633a546449d..79750daa83aa 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1446,10 +1446,12 @@ struct intel_digital_port {
enum phy_fia tc_phy_fia;
u8 tc_phy_fia_idx;
- /* protects num_hdcp_streams reference count, port_data */
+ /* protects num_hdcp_streams reference count, port_data and port_auth */
struct mutex hdcp_mutex;
/* the number of pipes using HDCP signalling out of this port */
unsigned int num_hdcp_streams;
+ /* port HDCP auth status */
+ bool port_auth;
/* HDCP port data need to pass to security f/w */
struct hdcp_port_data port_data;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 1a6ac24efe2d..97d521b216a6 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -26,6 +26,54 @@
#define KEY_LOAD_TRIES 5
#define HDCP2_LC_RETRY_CNT 3
+static int intel_conn_to_vcpi(struct intel_connector *connector)
+{
+ /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
+ return connector->port ? connector->port->vcpi.vcpi : 0;
+}
+
+static void
+intel_hdcp_required_content_stream(struct intel_digital_port *dig_port)
+{
+ struct drm_connector_list_iter conn_iter;
+ struct intel_digital_port *conn_dig_port;
+ struct intel_connector *connector;
+ struct intel_hdcp *hdcp;
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct hdcp_port_data *data = &dig_port->port_data;
+ bool enforce_type0 = false;
+
+ if (dig_port->port_auth)
+ return;
+
+ drm_connector_list_iter_begin(&i915->drm, &conn_iter);
+ for_each_intel_connector_iter(connector, &conn_iter) {
+ if (!intel_encoder_is_mst(intel_attached_encoder(connector)))
+ continue;
+
+ conn_dig_port = intel_attached_dig_port(connector);
+ if (conn_dig_port != dig_port)
+ continue;
+
+ if (connector->base.status == connector_status_disconnected)
+ continue;
+
+ hdcp = &connector->hdcp;
+ if (hdcp->content_type && !intel_hdcp2_capable(connector))
+ enforce_type0 = true;
+
+ data->streams[data->k].stream_type =
+ enforce_type0 ? DRM_MODE_HDCP_CONTENT_TYPE1 : hdcp->content_type;
+ data->streams[data->k].stream_id = intel_conn_to_vcpi(connector);
+ data->k++;
+
+ /* if there is only one active stream */
+ if (dig_port->dp.active_mst_links <= 1)
+ break;
+ }
+ drm_connector_list_iter_end(&conn_iter);
+}
+
static
bool intel_hdcp_is_ksv_valid(u8 *ksv)
{
@@ -1296,6 +1344,7 @@ static int hdcp2_authenticate_port(struct intel_connector *connector)
if (ret < 0)
drm_dbg_kms(&dev_priv->drm, "Enable hdcp auth failed. %d\n",
ret);
+
mutex_unlock(&dev_priv->hdcp_comp_mutex);
return ret;
@@ -1477,13 +1526,14 @@ static
int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
{
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct intel_hdcp *hdcp = &connector->hdcp;
union {
struct hdcp2_rep_stream_manage stream_manage;
struct hdcp2_rep_stream_ready stream_ready;
} msgs;
const struct intel_hdcp_shim *shim = hdcp->shim;
- int ret;
+ int ret, streams_size_delta, i;
if (connector->hdcp.seq_num_m > HDCP_2_2_SEQ_NUM_MAX)
return -ERANGE;
@@ -1493,15 +1543,18 @@ int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
drm_hdcp_cpu_to_be24(msgs.stream_manage.seq_num_m, hdcp->seq_num_m);
/* K no of streams is fixed as 1. Stored as big-endian. */
- msgs.stream_manage.k = cpu_to_be16(1);
+ msgs.stream_manage.k = cpu_to_be16(data->k);
- /* For HDMI this is forced to be 0x0. For DP SST also this is 0x0. */
- msgs.stream_manage.streams[0].stream_id = 0;
- msgs.stream_manage.streams[0].stream_type = hdcp->content_type;
+ for (i = 0; i < data->k; i++) {
+ msgs.stream_manage.streams[i].stream_id = data->streams[i].stream_id;
+ msgs.stream_manage.streams[i].stream_type = data->streams[i].stream_type;
+ }
+ streams_size_delta = HDCP_2_2_MAX_CONTENT_STREAMS_CNT *
+ sizeof(struct hdcp2_streamid_type) - data->k * sizeof(struct hdcp2_streamid_type);
/* Send it to Repeater */
ret = shim->write_2_2_msg(dig_port, &msgs.stream_manage,
- sizeof(msgs.stream_manage));
+ sizeof(msgs.stream_manage) - streams_size_delta);
if (ret < 0)
goto out;
@@ -1510,8 +1563,7 @@ int _hdcp2_propagate_stream_management_info(struct intel_connector *connector)
if (ret < 0)
goto out;
- dig_port->port_data.seq_num_m = hdcp->seq_num_m;
- dig_port->port_data.streams[0].stream_type = hdcp->content_type;
+ data->seq_num_m = hdcp->seq_num_m;
ret = hdcp2_verify_mprime(connector, &msgs.stream_ready);
@@ -1672,6 +1724,7 @@ static int hdcp2_enable_encryption(struct intel_connector *connector)
port),
LINK_ENCRYPTION_STATUS,
HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS);
+ dig_port->port_auth = true;
return ret;
}
@@ -1746,11 +1799,9 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
{
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
- struct hdcp_port_data *data = &dig_port->port_data;
- struct intel_hdcp *hdcp = &connector->hdcp;
- int ret, i, tries = 3;
+ int ret = 0, i, tries = 3;
- for (i = 0; i < tries; i++) {
+ for (i = 0; i < tries && !dig_port->port_auth; i++) {
ret = hdcp2_authenticate_sink(connector);
if (!ret) {
ret = hdcp2_propagate_stream_management_info(connector);
@@ -1760,7 +1811,7 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
ret);
break;
}
- data->streams[0].stream_type = hdcp->content_type;
+
ret = hdcp2_authenticate_port(connector);
if (!ret)
break;
@@ -1795,7 +1846,9 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
static int _intel_hdcp2_enable(struct intel_connector *connector)
{
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct hdcp_port_data *data = &dig_port->port_data;
struct intel_hdcp *hdcp = &connector->hdcp;
int ret;
@@ -1803,6 +1856,15 @@ static int _intel_hdcp2_enable(struct intel_connector *connector)
connector->base.name, connector->base.base.id,
hdcp->content_type);
+ /* Stream which requires encryption */
+ if (!intel_encoder_is_mst(intel_attached_encoder(connector)))
+ data->k = 1;
+ else
+ intel_hdcp_required_content_stream(dig_port);
+
+ if (drm_WARN_ON(&i915->drm, data->k > INTEL_NUM_PIPES(i915)))
+ return -EINVAL;
+
ret = hdcp2_authenticate_and_encrypt(connector);
if (ret) {
drm_dbg_kms(&i915->drm, "HDCP2 Type%d Enabling Failed. (%d)\n",
@@ -1820,7 +1882,9 @@ static int _intel_hdcp2_enable(struct intel_connector *connector)
static int _intel_hdcp2_disable(struct intel_connector *connector)
{
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct hdcp_port_data *data = &dig_port->port_data;
int ret;
drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is being Disabled\n",
@@ -1832,6 +1896,8 @@ static int _intel_hdcp2_disable(struct intel_connector *connector)
drm_dbg_kms(&i915->drm, "Port deauth failed.\n");
connector->hdcp.hdcp2_encrypted = false;
+ dig_port->port_auth = false;
+ data->k = 0;
return ret;
}
diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
index 9ae9669e46ea..b10d266fb60a 100644
--- a/drivers/misc/mei/hdcp/mei_hdcp.c
+++ b/drivers/misc/mei/hdcp/mei_hdcp.c
@@ -569,8 +569,7 @@ static int mei_hdcp_verify_mprime(struct device *dev,
verify_mprime_in->header.api_version = HDCP_API_VERSION;
verify_mprime_in->header.command_id = WIRED_REPEATER_AUTH_STREAM_REQ;
verify_mprime_in->header.status = ME_HDCP_STATUS_SUCCESS;
- verify_mprime_in->header.buffer_len =
- WIRED_CMD_BUF_LEN_REPEATER_AUTH_STREAM_REQ_MIN_IN;
+ verify_mprime_in->header.buffer_len = cmd_size - sizeof(struct hdcp_cmd_header);
verify_mprime_in->port.integrated_port_type = data->port_type;
verify_mprime_in->port.physical_port = (u8)data->fw_ddi;
diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
index fe58dbb46962..c8a37bb406b2 100644
--- a/include/drm/drm_hdcp.h
+++ b/include/drm/drm_hdcp.h
@@ -101,11 +101,11 @@
/* Following Macros take a byte at a time for bit(s) masking */
/*
- * TODO: This has to be changed for DP MST, as multiple stream on
- * same port is possible.
- * For HDCP2.2 on HDMI and DP SST this value is always 1.
+ * TODO: This is based upon actual H/W MST streams capacity.
+ *
+ * This is should be moved out to platform specific header.
*/
-#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1
+#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 4
#define HDCP_2_2_TXCAP_MASK_LEN 2
#define HDCP_2_2_RXCAPS_LEN 3
#define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0))
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 09/13] drm/i915/hdcp: mst streams support in hdcp port_data
2020-10-19 10:20 ` Anshuman Gupta
@ 2020-10-20 8:31 ` Jani Nikula
2020-10-20 8:30 ` Anshuman Gupta
0 siblings, 1 reply; 27+ messages in thread
From: Jani Nikula @ 2020-10-20 8:31 UTC (permalink / raw)
To: Anshuman Gupta, intel-gfx; +Cc: Tomas Winkler, seanpaul, dri-devel
On Mon, 19 Oct 2020, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> Add support for multiple mst stream in hdcp port data
> which will be used by RepeaterAuthStreamManage msg and
> HDCP 2.2 security f/w for m' validation.
>
> v2:
> Init the hdcp port data k for HDMI/DP SST strem.
>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 4 +-
> drivers/gpu/drm/i915/display/intel_hdcp.c | 92 ++++++++++++++++---
> drivers/misc/mei/hdcp/mei_hdcp.c | 3 +-
> include/drm/drm_hdcp.h | 8 +-
...
> diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
> index 9ae9669e46ea..b10d266fb60a 100644
> --- a/drivers/misc/mei/hdcp/mei_hdcp.c
> +++ b/drivers/misc/mei/hdcp/mei_hdcp.c
> @@ -569,8 +569,7 @@ static int mei_hdcp_verify_mprime(struct device *dev,
> verify_mprime_in->header.api_version = HDCP_API_VERSION;
> verify_mprime_in->header.command_id = WIRED_REPEATER_AUTH_STREAM_REQ;
> verify_mprime_in->header.status = ME_HDCP_STATUS_SUCCESS;
> - verify_mprime_in->header.buffer_len =
> - WIRED_CMD_BUF_LEN_REPEATER_AUTH_STREAM_REQ_MIN_IN;
> + verify_mprime_in->header.buffer_len = cmd_size - sizeof(struct hdcp_cmd_header);
>
> verify_mprime_in->port.integrated_port_type = data->port_type;
> verify_mprime_in->port.physical_port = (u8)data->fw_ddi;
> diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
> index fe58dbb46962..c8a37bb406b2 100644
> --- a/include/drm/drm_hdcp.h
> +++ b/include/drm/drm_hdcp.h
> @@ -101,11 +101,11 @@
>
> /* Following Macros take a byte at a time for bit(s) masking */
> /*
> - * TODO: This has to be changed for DP MST, as multiple stream on
> - * same port is possible.
> - * For HDCP2.2 on HDMI and DP SST this value is always 1.
> + * TODO: This is based upon actual H/W MST streams capacity.
> + *
> + * This is should be moved out to platform specific header.
> */
> -#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1
> +#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 4
> #define HDCP_2_2_TXCAP_MASK_LEN 2
> #define HDCP_2_2_RXCAPS_LEN 3
> #define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0))
These two hunk should probably be separate changes... would be easier to
record the changes (as they're not mentioned in the commit message at
all!) and the acks from other maintainers.
Cc: Tomas.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 09/13] drm/i915/hdcp: mst streams support in hdcp port_data
2020-10-20 8:31 ` Jani Nikula
@ 2020-10-20 8:30 ` Anshuman Gupta
2020-10-20 9:39 ` Jani Nikula
0 siblings, 1 reply; 27+ messages in thread
From: Anshuman Gupta @ 2020-10-20 8:30 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, seanpaul, Tomas Winkler, dri-devel
On 2020-10-20 at 11:31:37 +0300, Jani Nikula wrote:
> On Mon, 19 Oct 2020, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> > Add support for multiple mst stream in hdcp port data
> > which will be used by RepeaterAuthStreamManage msg and
> > HDCP 2.2 security f/w for m' validation.
> >
> > v2:
> > Init the hdcp port data k for HDMI/DP SST strem.
> >
> > Cc: Ramalingam C <ramalingam.c@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > ---
> > .../drm/i915/display/intel_display_types.h | 4 +-
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 92 ++++++++++++++++---
> > drivers/misc/mei/hdcp/mei_hdcp.c | 3 +-
> > include/drm/drm_hdcp.h | 8 +-
>
> ...
>
> > diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
> > index 9ae9669e46ea..b10d266fb60a 100644
> > --- a/drivers/misc/mei/hdcp/mei_hdcp.c
> > +++ b/drivers/misc/mei/hdcp/mei_hdcp.c
> > @@ -569,8 +569,7 @@ static int mei_hdcp_verify_mprime(struct device *dev,
> > verify_mprime_in->header.api_version = HDCP_API_VERSION;
> > verify_mprime_in->header.command_id = WIRED_REPEATER_AUTH_STREAM_REQ;
> > verify_mprime_in->header.status = ME_HDCP_STATUS_SUCCESS;
> > - verify_mprime_in->header.buffer_len =
> > - WIRED_CMD_BUF_LEN_REPEATER_AUTH_STREAM_REQ_MIN_IN;
> > + verify_mprime_in->header.buffer_len = cmd_size - sizeof(struct hdcp_cmd_header);
> >
> > verify_mprime_in->port.integrated_port_type = data->port_type;
> > verify_mprime_in->port.physical_port = (u8)data->fw_ddi;
> > diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
> > index fe58dbb46962..c8a37bb406b2 100644
> > --- a/include/drm/drm_hdcp.h
> > +++ b/include/drm/drm_hdcp.h
> > @@ -101,11 +101,11 @@
> >
> > /* Following Macros take a byte at a time for bit(s) masking */
> > /*
> > - * TODO: This has to be changed for DP MST, as multiple stream on
> > - * same port is possible.
> > - * For HDCP2.2 on HDMI and DP SST this value is always 1.
> > + * TODO: This is based upon actual H/W MST streams capacity.
> > + *
> > + * This is should be moved out to platform specific header.
> > */
> > -#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1
> > +#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 4
> > #define HDCP_2_2_TXCAP_MASK_LEN 2
> > #define HDCP_2_2_RXCAPS_LEN 3
> > #define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0))
>
> These two hunk should probably be separate changes... would be easier to
> record the changes (as they're not mentioned in the commit message at
> all!) and the acks from other maintainers.
Thanks Jani for comment, as this need to sens DRI too, so I formatted a
separate patch to avoid other related HDCP noise.
https://patchwork.freedesktop.org/series/82806/
Based upon ack of maintainers i will rebase my this series.
Thanks,
Anshuman Gupta.
>
> Cc: Tomas.
>
>
> BR,
> Jani.
>
>
> --
> Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 09/13] drm/i915/hdcp: mst streams support in hdcp port_data
2020-10-20 8:30 ` Anshuman Gupta
@ 2020-10-20 9:39 ` Jani Nikula
2020-10-20 9:38 ` Anshuman Gupta
0 siblings, 1 reply; 27+ messages in thread
From: Jani Nikula @ 2020-10-20 9:39 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx, seanpaul, Tomas Winkler, dri-devel
On Tue, 20 Oct 2020, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> On 2020-10-20 at 11:31:37 +0300, Jani Nikula wrote:
>> On Mon, 19 Oct 2020, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
>> > Add support for multiple mst stream in hdcp port data
>> > which will be used by RepeaterAuthStreamManage msg and
>> > HDCP 2.2 security f/w for m' validation.
>> >
>> > v2:
>> > Init the hdcp port data k for HDMI/DP SST strem.
>> >
>> > Cc: Ramalingam C <ramalingam.c@intel.com>
>> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
>> > ---
>> > .../drm/i915/display/intel_display_types.h | 4 +-
>> > drivers/gpu/drm/i915/display/intel_hdcp.c | 92 ++++++++++++++++---
>> > drivers/misc/mei/hdcp/mei_hdcp.c | 3 +-
>> > include/drm/drm_hdcp.h | 8 +-
>>
>> ...
>>
>> > diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
>> > index 9ae9669e46ea..b10d266fb60a 100644
>> > --- a/drivers/misc/mei/hdcp/mei_hdcp.c
>> > +++ b/drivers/misc/mei/hdcp/mei_hdcp.c
>> > @@ -569,8 +569,7 @@ static int mei_hdcp_verify_mprime(struct device *dev,
>> > verify_mprime_in->header.api_version = HDCP_API_VERSION;
>> > verify_mprime_in->header.command_id = WIRED_REPEATER_AUTH_STREAM_REQ;
>> > verify_mprime_in->header.status = ME_HDCP_STATUS_SUCCESS;
>> > - verify_mprime_in->header.buffer_len =
>> > - WIRED_CMD_BUF_LEN_REPEATER_AUTH_STREAM_REQ_MIN_IN;
>> > + verify_mprime_in->header.buffer_len = cmd_size - sizeof(struct hdcp_cmd_header);
>> >
>> > verify_mprime_in->port.integrated_port_type = data->port_type;
>> > verify_mprime_in->port.physical_port = (u8)data->fw_ddi;
>> > diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
>> > index fe58dbb46962..c8a37bb406b2 100644
>> > --- a/include/drm/drm_hdcp.h
>> > +++ b/include/drm/drm_hdcp.h
>> > @@ -101,11 +101,11 @@
>> >
>> > /* Following Macros take a byte at a time for bit(s) masking */
>> > /*
>> > - * TODO: This has to be changed for DP MST, as multiple stream on
>> > - * same port is possible.
>> > - * For HDCP2.2 on HDMI and DP SST this value is always 1.
>> > + * TODO: This is based upon actual H/W MST streams capacity.
>> > + *
>> > + * This is should be moved out to platform specific header.
>> > */
>> > -#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1
>> > +#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 4
>> > #define HDCP_2_2_TXCAP_MASK_LEN 2
>> > #define HDCP_2_2_RXCAPS_LEN 3
>> > #define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0))
>>
>> These two hunk should probably be separate changes... would be easier to
>> record the changes (as they're not mentioned in the commit message at
>> all!) and the acks from other maintainers.
> Thanks Jani for comment, as this need to sens DRI too, so I formatted a
> separate patch to avoid other related HDCP noise.
> https://patchwork.freedesktop.org/series/82806/
> Based upon ack of maintainers i will rebase my this series.
I see the mei change as more important to be split out to be honest, and
I'd prefer all of these to be retained in the same *series* albeit as
separate patches. We'll want to get the acks to merge via drm-intel as
dependencies, instead of them being merged directly in their trees and
then waiting for weeks for merges and backmerges.
BR,
Jani.
> Thanks,
> Anshuman Gupta.
>>
>> Cc: Tomas.
>>
>>
>> BR,
>> Jani.
>>
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 09/13] drm/i915/hdcp: mst streams support in hdcp port_data
2020-10-20 9:39 ` Jani Nikula
@ 2020-10-20 9:38 ` Anshuman Gupta
2020-10-20 10:18 ` Jani Nikula
0 siblings, 1 reply; 27+ messages in thread
From: Anshuman Gupta @ 2020-10-20 9:38 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, seanpaul, Tomas Winkler, dri-devel
On 2020-10-20 at 12:39:04 +0300, Jani Nikula wrote:
> On Tue, 20 Oct 2020, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> > On 2020-10-20 at 11:31:37 +0300, Jani Nikula wrote:
> >> On Mon, 19 Oct 2020, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> >> > Add support for multiple mst stream in hdcp port data
> >> > which will be used by RepeaterAuthStreamManage msg and
> >> > HDCP 2.2 security f/w for m' validation.
> >> >
> >> > v2:
> >> > Init the hdcp port data k for HDMI/DP SST strem.
> >> >
> >> > Cc: Ramalingam C <ramalingam.c@intel.com>
> >> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> >> > ---
> >> > .../drm/i915/display/intel_display_types.h | 4 +-
> >> > drivers/gpu/drm/i915/display/intel_hdcp.c | 92 ++++++++++++++++---
> >> > drivers/misc/mei/hdcp/mei_hdcp.c | 3 +-
> >> > include/drm/drm_hdcp.h | 8 +-
> >>
> >> ...
> >>
> >> > diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
> >> > index 9ae9669e46ea..b10d266fb60a 100644
> >> > --- a/drivers/misc/mei/hdcp/mei_hdcp.c
> >> > +++ b/drivers/misc/mei/hdcp/mei_hdcp.c
> >> > @@ -569,8 +569,7 @@ static int mei_hdcp_verify_mprime(struct device *dev,
> >> > verify_mprime_in->header.api_version = HDCP_API_VERSION;
> >> > verify_mprime_in->header.command_id = WIRED_REPEATER_AUTH_STREAM_REQ;
> >> > verify_mprime_in->header.status = ME_HDCP_STATUS_SUCCESS;
> >> > - verify_mprime_in->header.buffer_len =
> >> > - WIRED_CMD_BUF_LEN_REPEATER_AUTH_STREAM_REQ_MIN_IN;
> >> > + verify_mprime_in->header.buffer_len = cmd_size - sizeof(struct hdcp_cmd_header);
> >> >
> >> > verify_mprime_in->port.integrated_port_type = data->port_type;
> >> > verify_mprime_in->port.physical_port = (u8)data->fw_ddi;
> >> > diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
> >> > index fe58dbb46962..c8a37bb406b2 100644
> >> > --- a/include/drm/drm_hdcp.h
> >> > +++ b/include/drm/drm_hdcp.h
> >> > @@ -101,11 +101,11 @@
> >> >
> >> > /* Following Macros take a byte at a time for bit(s) masking */
> >> > /*
> >> > - * TODO: This has to be changed for DP MST, as multiple stream on
> >> > - * same port is possible.
> >> > - * For HDCP2.2 on HDMI and DP SST this value is always 1.
> >> > + * TODO: This is based upon actual H/W MST streams capacity.
> >> > + *
> >> > + * This is should be moved out to platform specific header.
> >> > */
> >> > -#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1
> >> > +#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 4
> >> > #define HDCP_2_2_TXCAP_MASK_LEN 2
> >> > #define HDCP_2_2_RXCAPS_LEN 3
> >> > #define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0))
> >>
> >> These two hunk should probably be separate changes... would be easier to
> >> record the changes (as they're not mentioned in the commit message at
> >> all!) and the acks from other maintainers.
> > Thanks Jani for comment, as this need to sens DRI too, so I formatted a
> > separate patch to avoid other related HDCP noise.
> > https://patchwork.freedesktop.org/series/82806/
> > Based upon ack of maintainers i will rebase my this series.
>
> I see the mei change as more important to be split out to be honest, and
> I'd prefer all of these to be retained in the same *series* albeit as
> separate patches. We'll want to get the acks to merge via drm-intel as
> dependencies, instead of them being merged directly in their trees and
> then waiting for weeks for merges and backmerges.
Sure i will do that this with same series.
>
> BR,
> Jani.
>
>
> > Thanks,
> > Anshuman Gupta.
> >>
> >> Cc: Tomas.
> >>
> >>
> >> BR,
> >> Jani.
> >>
> >>
> >> --
> >> Jani Nikula, Intel Open Source Graphics Center
>
> --
> Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
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^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 09/13] drm/i915/hdcp: mst streams support in hdcp port_data
2020-10-20 9:38 ` Anshuman Gupta
@ 2020-10-20 10:18 ` Jani Nikula
0 siblings, 0 replies; 27+ messages in thread
From: Jani Nikula @ 2020-10-20 10:18 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx, seanpaul, Tomas Winkler, dri-devel
On Tue, 20 Oct 2020, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
> On 2020-10-20 at 12:39:04 +0300, Jani Nikula wrote:
>> On Tue, 20 Oct 2020, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
>> > On 2020-10-20 at 11:31:37 +0300, Jani Nikula wrote:
>> >> On Mon, 19 Oct 2020, Anshuman Gupta <anshuman.gupta@intel.com> wrote:
>> >> > Add support for multiple mst stream in hdcp port data
>> >> > which will be used by RepeaterAuthStreamManage msg and
>> >> > HDCP 2.2 security f/w for m' validation.
>> >> >
>> >> > v2:
>> >> > Init the hdcp port data k for HDMI/DP SST strem.
>> >> >
>> >> > Cc: Ramalingam C <ramalingam.c@intel.com>
>> >> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
>> >> > ---
>> >> > .../drm/i915/display/intel_display_types.h | 4 +-
>> >> > drivers/gpu/drm/i915/display/intel_hdcp.c | 92 ++++++++++++++++---
>> >> > drivers/misc/mei/hdcp/mei_hdcp.c | 3 +-
>> >> > include/drm/drm_hdcp.h | 8 +-
>> >>
>> >> ...
>> >>
>> >> > diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c
>> >> > index 9ae9669e46ea..b10d266fb60a 100644
>> >> > --- a/drivers/misc/mei/hdcp/mei_hdcp.c
>> >> > +++ b/drivers/misc/mei/hdcp/mei_hdcp.c
>> >> > @@ -569,8 +569,7 @@ static int mei_hdcp_verify_mprime(struct device *dev,
>> >> > verify_mprime_in->header.api_version = HDCP_API_VERSION;
>> >> > verify_mprime_in->header.command_id = WIRED_REPEATER_AUTH_STREAM_REQ;
>> >> > verify_mprime_in->header.status = ME_HDCP_STATUS_SUCCESS;
>> >> > - verify_mprime_in->header.buffer_len =
>> >> > - WIRED_CMD_BUF_LEN_REPEATER_AUTH_STREAM_REQ_MIN_IN;
>> >> > + verify_mprime_in->header.buffer_len = cmd_size - sizeof(struct hdcp_cmd_header);
>> >> >
>> >> > verify_mprime_in->port.integrated_port_type = data->port_type;
>> >> > verify_mprime_in->port.physical_port = (u8)data->fw_ddi;
>> >> > diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
>> >> > index fe58dbb46962..c8a37bb406b2 100644
>> >> > --- a/include/drm/drm_hdcp.h
>> >> > +++ b/include/drm/drm_hdcp.h
>> >> > @@ -101,11 +101,11 @@
>> >> >
>> >> > /* Following Macros take a byte at a time for bit(s) masking */
>> >> > /*
>> >> > - * TODO: This has to be changed for DP MST, as multiple stream on
>> >> > - * same port is possible.
>> >> > - * For HDCP2.2 on HDMI and DP SST this value is always 1.
>> >> > + * TODO: This is based upon actual H/W MST streams capacity.
>> >> > + *
>> >> > + * This is should be moved out to platform specific header.
>> >> > */
>> >> > -#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1
>> >> > +#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 4
>> >> > #define HDCP_2_2_TXCAP_MASK_LEN 2
>> >> > #define HDCP_2_2_RXCAPS_LEN 3
>> >> > #define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0))
>> >>
>> >> These two hunk should probably be separate changes... would be easier to
>> >> record the changes (as they're not mentioned in the commit message at
>> >> all!) and the acks from other maintainers.
>> > Thanks Jani for comment, as this need to sens DRI too, so I formatted a
>> > separate patch to avoid other related HDCP noise.
>> > https://patchwork.freedesktop.org/series/82806/
>> > Based upon ack of maintainers i will rebase my this series.
>>
>> I see the mei change as more important to be split out to be honest, and
>> I'd prefer all of these to be retained in the same *series* albeit as
>> separate patches. We'll want to get the acks to merge via drm-intel as
>> dependencies, instead of them being merged directly in their trees and
>> then waiting for weeks for merges and backmerges.
> Sure i will do that this with same series.
Please be sure to record the ack we got from Maarten.
BR,
Jani.
>>
>> BR,
>> Jani.
>>
>>
>> > Thanks,
>> > Anshuman Gupta.
>> >>
>> >> Cc: Tomas.
>> >>
>> >>
>> >> BR,
>> >> Jani.
>> >>
>> >>
>> >> --
>> >> Jani Nikula, Intel Open Source Graphics Center
>>
>> --
>> Jani Nikula, Intel Open Source Graphics Center
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 10/13] drm/i915/hdcp: Pass connector to check_2_2_link
2020-10-14 4:52 [Intel-gfx] [PATCH 00/13] HDCP 2.2 DP MST Support Anshuman Gupta
` (8 preceding siblings ...)
2020-10-14 4:52 ` [Intel-gfx] [PATCH 09/13] drm/i915/hdcp: mst streams support in hdcp port_data Anshuman Gupta
@ 2020-10-14 4:52 ` Anshuman Gupta
2020-10-14 4:52 ` [Intel-gfx] [PATCH 11/13] drm/i915/hdcp: Add HDCP 2.2 stream register Anshuman Gupta
` (9 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Anshuman Gupta @ 2020-10-14 4:52 UTC (permalink / raw)
To: intel-gfx; +Cc: seanpaul
This requires for HDCP 2.2 MST check link.
Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_types.h | 3 ++-
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 3 ++-
drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++-
4 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 79750daa83aa..c395a202dbca 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -375,7 +375,8 @@ struct intel_hdcp_shim {
bool is_repeater, u8 type);
/* HDCP2.2 Link Integrity Check */
- int (*check_2_2_link)(struct intel_digital_port *dig_port);
+ int (*check_2_2_link)(struct intel_digital_port *dig_port,
+ struct intel_connector *connector);
};
struct intel_hdcp {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 384e384cb9e2..a0c62e363c39 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -585,7 +585,8 @@ int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *dig_port,
}
static
-int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port)
+int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
{
u8 rx_status;
int ret;
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index b36b87941c1a..5e9c5f330c70 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1927,7 +1927,7 @@ static int intel_hdcp2_check_link(struct intel_connector *connector)
goto out;
}
- ret = hdcp->shim->check_2_2_link(dig_port);
+ ret = hdcp->shim->check_2_2_link(dig_port, connector);
if (ret == HDCP_LINK_PROTECTED) {
if (hdcp->value != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) {
intel_hdcp_update_value(connector,
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 0788de04711b..bd0d91101464 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -1734,7 +1734,8 @@ int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port,
}
static
-int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port)
+int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
{
u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
int ret;
--
2.26.2
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [Intel-gfx] [PATCH 11/13] drm/i915/hdcp: Add HDCP 2.2 stream register
2020-10-14 4:52 [Intel-gfx] [PATCH 00/13] HDCP 2.2 DP MST Support Anshuman Gupta
` (9 preceding siblings ...)
2020-10-14 4:52 ` [Intel-gfx] [PATCH 10/13] drm/i915/hdcp: Pass connector to check_2_2_link Anshuman Gupta
@ 2020-10-14 4:52 ` Anshuman Gupta
2020-10-14 4:52 ` [Intel-gfx] [PATCH 12/13] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks Anshuman Gupta
` (8 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Anshuman Gupta @ 2020-10-14 4:52 UTC (permalink / raw)
To: intel-gfx; +Cc: seanpaul
Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS
and HDCP2_AUTH_STREAM register in i915_reg header.
Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 050d7307ebc4..654f1d11eb02 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9851,6 +9851,7 @@ enum skl_power_gate {
_PORTD_HDCP2_BASE, \
_PORTE_HDCP2_BASE, \
_PORTF_HDCP2_BASE) + (x))
+
#define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98)
#define _TRANSA_HDCP2_AUTH 0x66498
#define _TRANSB_HDCP2_AUTH 0x66598
@@ -9890,6 +9891,35 @@ enum skl_power_gate {
TRANS_HDCP2_STATUS(trans) : \
PORT_HDCP2_STATUS(port))
+#define PORT_HDCP2_STREAM_STATUS(port) _PORT_HDCP2_BASE(port, 0xC0)
+#define _TRANSA_HDCP2_STREAM_STATUS 0x664C0
+#define _TRANSB_HDCP2_STREAM_STATUS 0x665C0
+#define TRANS_HDCP2_STREAM_STATUS(trans) _MMIO_TRANS(trans, \
+ _TRANSA_HDCP2_STREAM_STATUS, \
+ _TRANSB_HDCP2_STREAM_STATUS)
+#define STREAM_ENCRYPTION_STATUS BIT(31)
+#define STREAM_TYPE_STATUS BIT(30)
+#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+ TRANS_HDCP2_STREAM_STATUS(trans) : \
+ PORT_HDCP2_STREAM_STATUS(port))
+
+#define _PORTA_HDCP2_AUTH_STREAM 0x66F00
+#define _PORTB_HDCP2_AUTH_STREAM 0x66F04
+#define PORT_HDCP2_AUTH_STREAM(port) _MMIO_PORT(port, \
+ _PORTA_HDCP2_AUTH_STREAM, \
+ _PORTB_HDCP2_AUTH_STREAM)
+#define _TRANSA_HDCP2_AUTH_STREAM 0x66F00
+#define _TRANSB_HDCP2_AUTH_STREAM 0x66F04
+#define TRANS_HDCP2_AUTH_STREAM(trans) _MMIO_TRANS(trans, \
+ _TRANSA_HDCP2_AUTH_STREAM, \
+ _TRANSB_HDCP2_AUTH_STREAM)
+#define AUTH_STREAM_TYPE BIT(31)
+#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \
+ (INTEL_GEN(dev_priv) >= 12 ? \
+ TRANS_HDCP2_AUTH_STREAM(trans) : \
+ PORT_HDCP2_AUTH_STREAM(port))
+
/* Per-pipe DDI Function Control */
#define _TRANS_DDI_FUNC_CTL_A 0x60400
#define _TRANS_DDI_FUNC_CTL_B 0x61400
--
2.26.2
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [Intel-gfx] [PATCH 12/13] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks
2020-10-14 4:52 [Intel-gfx] [PATCH 00/13] HDCP 2.2 DP MST Support Anshuman Gupta
` (10 preceding siblings ...)
2020-10-14 4:52 ` [Intel-gfx] [PATCH 11/13] drm/i915/hdcp: Add HDCP 2.2 stream register Anshuman Gupta
@ 2020-10-14 4:52 ` Anshuman Gupta
2020-10-14 4:52 ` [Intel-gfx] [PATCH 13/13] drm/i915/hdcp: Enable HDCP 2.2 MST support Anshuman Gupta
` (7 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Anshuman Gupta @ 2020-10-14 4:52 UTC (permalink / raw)
To: intel-gfx; +Cc: seanpaul
Add support for HDCP 2.2 DP MST shim callback.
This adds existing DP HDCP shim callback for Link Authentication
and Encryption and HDCP 2.2 stream encryption
callback.
Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
.../drm/i915/display/intel_display_types.h | 4 +
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 81 +++++++++++++++++--
2 files changed, 77 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index c395a202dbca..37850711b6c1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -374,6 +374,10 @@ struct intel_hdcp_shim {
int (*config_stream_type)(struct intel_digital_port *dig_port,
bool is_repeater, u8 type);
+ /* Enable/Disable HDCP 2.2 stream encryption on DP MST Transport Link */
+ int (*stream_2_2_encryption)(struct intel_digital_port *dig_port,
+ bool enable);
+
/* HDCP2.2 Link Integrity Check */
int (*check_2_2_link)(struct intel_digital_port *dig_port,
struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index a0c62e363c39..7e45b9964a29 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -698,18 +698,14 @@ intel_dp_mst_hdcp_strem_encryption(struct intel_digital_port *dig_port,
return 0;
}
-static
-bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
- struct intel_connector *connector)
+static bool intel_dp_mst_get_qses_status(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- struct intel_dp *intel_dp = &dig_port->dp;
struct drm_dp_query_stream_enc_status_ack_reply reply;
+ struct intel_dp *intel_dp = &dig_port->dp;
int ret;
- if (!intel_dp_hdcp_check_link(dig_port, connector))
- return false;
-
ret = drm_dp_send_query_stream_enc_status(&intel_dp->mst_mgr,
connector->port, &reply);
if (ret) {
@@ -722,6 +718,70 @@ bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
return reply.auth_completed && reply.encryption_enabled;
}
+static
+bool intel_dp_mst_hdcp_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
+{
+ if (!intel_dp_hdcp_check_link(dig_port, connector))
+ return false;
+
+ return intel_dp_mst_get_qses_status(dig_port, connector);
+}
+
+static int
+intel_dp_mst_hdcp2_strem_encryption(struct intel_digital_port *dig_port,
+ bool enable)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_dp *dp = &dig_port->dp;
+ struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
+ enum port port = dig_port->base.port;
+ /* HDCP2.x register uses stream transcoder */
+ enum transcoder cpu_transcoder = hdcp->stream_transcoder;
+ int ret;
+
+ if (enable && (intel_de_read(i915, HDCP2_AUTH_STREAM(i915, cpu_transcoder, port)) &
+ AUTH_STREAM_TYPE) != hdcp->content_type) {
+ drm_err(&i915->drm, "Seurity f/w didn't set correct auth strem_type\n");
+ return -EINVAL;
+ }
+
+ ret = intel_dp_mst_toggle_select_hdcp_stream(dig_port, enable);
+ if (ret)
+ return ret;
+
+ /* Wait for encryption confirmation */
+ if (intel_de_wait_for_register(i915,
+ HDCP2_STREAM_STATUS(i915, cpu_transcoder, port),
+ STREAM_ENCRYPTION_STATUS,
+ enable ? STREAM_ENCRYPTION_STATUS : 0,
+ HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
+ drm_err(&i915->drm, "Timed out waiting for stream encryption %s\n",
+ enable ? "enabled" : "disabled");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+/*
+ * DP v2.0 I.3.3 ignore the stream signature L' is QSES reply msg reply.
+ * I.3.5 MST source device may use a QSES msg to query downstream status
+ * for a particular stream.
+ */
+static
+int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port,
+ struct intel_connector *connector)
+{
+ int ret;
+
+ ret = intel_dp_hdcp2_check_link(dig_port, connector);
+ if (ret)
+ return ret;
+
+ return intel_dp_mst_get_qses_status(dig_port, connector) ? 0 : -EINVAL;
+}
+
static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
.write_an_aksv = intel_dp_hdcp_write_an_aksv,
.read_bksv = intel_dp_hdcp_read_bksv,
@@ -735,7 +795,12 @@ static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
.stream_encryption = intel_dp_mst_hdcp_strem_encryption,
.check_link = intel_dp_mst_hdcp_check_link,
.hdcp_capable = intel_dp_hdcp_capable,
-
+ .write_2_2_msg = intel_dp_hdcp2_write_msg,
+ .read_2_2_msg = intel_dp_hdcp2_read_msg,
+ .config_stream_type = intel_dp_hdcp2_config_stream_type,
+ .stream_2_2_encryption = intel_dp_mst_hdcp2_strem_encryption,
+ .check_2_2_link = intel_dp_mst_hdcp2_check_link,
+ .hdcp_2_2_capable = intel_dp_hdcp2_capable,
.protocol = HDCP_PROTOCOL_DP,
};
--
2.26.2
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^ permalink raw reply related [flat|nested] 27+ messages in thread* [Intel-gfx] [PATCH 13/13] drm/i915/hdcp: Enable HDCP 2.2 MST support
2020-10-14 4:52 [Intel-gfx] [PATCH 00/13] HDCP 2.2 DP MST Support Anshuman Gupta
` (11 preceding siblings ...)
2020-10-14 4:52 ` [Intel-gfx] [PATCH 12/13] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks Anshuman Gupta
@ 2020-10-14 4:52 ` Anshuman Gupta
2020-10-14 5:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for HDCP 2.2 DP MST Support (rev2) Patchwork
` (6 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Anshuman Gupta @ 2020-10-14 4:52 UTC (permalink / raw)
To: intel-gfx; +Cc: seanpaul
Enable HDCP 2.2 over DP MST.
Cc: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 46 ++++++++++++++++++++++-
1 file changed, 44 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 5e9c5f330c70..8dcc78cc3dcc 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1684,6 +1684,32 @@ static int hdcp2_authenticate_sink(struct intel_connector *connector)
return ret;
}
+static int hdcp2_enable_stream_encryption(struct intel_connector *connector)
+{
+ struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
+ struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
+ struct intel_hdcp *hdcp = &connector->hdcp;
+ enum transcoder cpu_transcoder = hdcp->cpu_transcoder;
+ enum port port = dig_port->base.port;
+ int ret = 0;
+
+ if (!(intel_de_read(dev_priv, HDCP2_STATUS(dev_priv, cpu_transcoder, port)) &
+ LINK_ENCRYPTION_STATUS)) {
+ drm_err(&dev_priv->drm, "HDCP 2.2 Link is not encrypted\n");
+ return -EPERM;
+ }
+
+ if (hdcp->shim->stream_2_2_encryption) {
+ ret = hdcp->shim->stream_2_2_encryption(dig_port, true);
+ if (ret) {
+ drm_err(&dev_priv->drm, "Failed to enable HDCP 2.2 stream enc\n");
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
static int hdcp2_enable_encryption(struct intel_connector *connector)
{
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
@@ -1822,7 +1848,7 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
drm_dbg_kms(&i915->drm, "Port deauth failed.\n");
}
- if (!ret) {
+ if (!ret && !dig_port->port_auth) {
/*
* Ensuring the required 200mSec min time interval between
* Session Key Exchange and encryption.
@@ -1837,6 +1863,8 @@ static int hdcp2_authenticate_and_encrypt(struct intel_connector *connector)
}
}
+ ret = hdcp2_enable_stream_encryption(connector);
+
return ret;
}
@@ -1878,11 +1906,23 @@ static int _intel_hdcp2_disable(struct intel_connector *connector)
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct hdcp_port_data *data = &dig_port->port_data;
+ struct intel_hdcp *hdcp = &connector->hdcp;
int ret;
drm_dbg_kms(&i915->drm, "[%s:%d] HDCP2.2 is being Disabled\n",
connector->base.name, connector->base.base.id);
+ if (hdcp->shim->stream_2_2_encryption) {
+ ret = hdcp->shim->stream_2_2_encryption(dig_port, false);
+ if (ret) {
+ drm_err(&i915->drm, "Failed to disable HDCP 2.2 stream enc\n");
+ return ret;
+ }
+ }
+
+ if (dig_port->num_hdcp_streams > 0)
+ return ret;
+
ret = hdcp2_disable_encryption(connector);
if (hdcp2_deauthenticate_port(connector) < 0)
@@ -1906,6 +1946,7 @@ static int intel_hdcp2_check_link(struct intel_connector *connector)
int ret = 0;
mutex_lock(&hdcp->mutex);
+ mutex_lock(&dig_port->hdcp_mutex);
cpu_transcoder = hdcp->cpu_transcoder;
/* hdcp2_check_link is expected only when HDCP2.2 is Enabled */
@@ -1983,6 +2024,7 @@ static int intel_hdcp2_check_link(struct intel_connector *connector)
}
out:
+ mutex_unlock(&dig_port->hdcp_mutex);
mutex_unlock(&hdcp->mutex);
return ret;
}
@@ -2164,7 +2206,7 @@ int intel_hdcp_init(struct intel_connector *connector,
if (!shim)
return -EINVAL;
- if (is_hdcp2_supported(dev_priv) && !connector->mst_port)
+ if (is_hdcp2_supported(dev_priv))
intel_hdcp2_init(connector, dig_port, shim);
ret =
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 27+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for HDCP 2.2 DP MST Support (rev2)
2020-10-14 4:52 [Intel-gfx] [PATCH 00/13] HDCP 2.2 DP MST Support Anshuman Gupta
` (12 preceding siblings ...)
2020-10-14 4:52 ` [Intel-gfx] [PATCH 13/13] drm/i915/hdcp: Enable HDCP 2.2 MST support Anshuman Gupta
@ 2020-10-14 5:15 ` Patchwork
2020-10-14 5:16 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (5 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2020-10-14 5:15 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
== Series Details ==
Series: HDCP 2.2 DP MST Support (rev2)
URL : https://patchwork.freedesktop.org/series/81538/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
51e1dc4c0c75 drm/i915/hdcp: Update CP property in update_pipe
46a92a431c4f drm/i915/hotplug: Handle CP_IRQ for DP-MST
2147d0efa227 drm/i915/hdcp: DP MST transcoder for link and stream
ec157320f9ee drm/i915/hdcp: Move HDCP enc status timeout to header
-:13: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 7e90e8d0c0ea ("drm/i915: Increase timeout for Encrypt status change")'
#13:
Related: 7e90e8d0c0ea ("drm/i915: Increase timeout for Encrypt
total: 1 errors, 0 warnings, 0 checks, 47 lines checked
3a6056295149 drm/i915/hdcp: HDCP stream encryption support
87a4a87a3296 drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support
86046073868b drm/i915/hdcp: Pass dig_port to intel_hdcp_init
03477decebcc drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port
629f09e3ddea drm/i915/hdcp: mst streams support in hdcp port_data
1300b2ad499f drm/i915/hdcp: Pass connector to check_2_2_link
f47295717b3e drm/i915/hdcp: Add HDCP 2.2 stream register
0b04d5020a92 drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks
ac59ab83da2a drm/i915/hdcp: Enable HDCP 2.2 MST support
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for HDCP 2.2 DP MST Support (rev2)
2020-10-14 4:52 [Intel-gfx] [PATCH 00/13] HDCP 2.2 DP MST Support Anshuman Gupta
` (13 preceding siblings ...)
2020-10-14 5:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for HDCP 2.2 DP MST Support (rev2) Patchwork
@ 2020-10-14 5:16 ` Patchwork
2020-10-14 5:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (4 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2020-10-14 5:16 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
== Series Details ==
Series: HDCP 2.2 DP MST Support (rev2)
URL : https://patchwork.freedesktop.org/series/81538/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216
+./include/linux/seqlock.h:752:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:778:16: warning: trying to copy expression type 31
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for HDCP 2.2 DP MST Support (rev2)
2020-10-14 4:52 [Intel-gfx] [PATCH 00/13] HDCP 2.2 DP MST Support Anshuman Gupta
` (14 preceding siblings ...)
2020-10-14 5:16 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2020-10-14 5:45 ` Patchwork
2020-10-14 16:03 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
` (3 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2020-10-14 5:45 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 12636 bytes --]
== Series Details ==
Series: HDCP 2.2 DP MST Support (rev2)
URL : https://patchwork.freedesktop.org/series/81538/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9137 -> Patchwork_18696
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18696:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@core_hotunplug@unbind-rebind}:
- fi-skl-6700k2: [DMESG-WARN][1] ([i915#2203]) -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/fi-skl-6700k2/igt@core_hotunplug@unbind-rebind.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-skl-6700k2/igt@core_hotunplug@unbind-rebind.html
- fi-skl-lmem: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/fi-skl-lmem/igt@core_hotunplug@unbind-rebind.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-skl-lmem/igt@core_hotunplug@unbind-rebind.html
- {fi-ehl-1}: [PASS][5] -> [INCOMPLETE][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/fi-ehl-1/igt@core_hotunplug@unbind-rebind.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-ehl-1/igt@core_hotunplug@unbind-rebind.html
- fi-tgl-u2: [PASS][7] -> [INCOMPLETE][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html
- fi-cfl-guc: [PASS][9] -> [INCOMPLETE][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/fi-cfl-guc/igt@core_hotunplug@unbind-rebind.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-cfl-guc/igt@core_hotunplug@unbind-rebind.html
- {fi-kbl-7560u}: [PASS][11] -> [INCOMPLETE][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/fi-kbl-7560u/igt@core_hotunplug@unbind-rebind.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-kbl-7560u/igt@core_hotunplug@unbind-rebind.html
- fi-skl-6600u: [PASS][13] -> [INCOMPLETE][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/fi-skl-6600u/igt@core_hotunplug@unbind-rebind.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-skl-6600u/igt@core_hotunplug@unbind-rebind.html
- fi-cml-s: [PASS][15] -> [INCOMPLETE][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/fi-cml-s/igt@core_hotunplug@unbind-rebind.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-cml-s/igt@core_hotunplug@unbind-rebind.html
- fi-kbl-soraka: [PASS][17] -> [INCOMPLETE][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/fi-kbl-soraka/igt@core_hotunplug@unbind-rebind.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-kbl-soraka/igt@core_hotunplug@unbind-rebind.html
- fi-kbl-r: [PASS][19] -> [INCOMPLETE][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/fi-kbl-r/igt@core_hotunplug@unbind-rebind.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-kbl-r/igt@core_hotunplug@unbind-rebind.html
- fi-cfl-8700k: [PASS][21] -> [INCOMPLETE][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/fi-cfl-8700k/igt@core_hotunplug@unbind-rebind.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-cfl-8700k/igt@core_hotunplug@unbind-rebind.html
- {fi-tgl-dsi}: [PASS][23] -> [INCOMPLETE][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/fi-tgl-dsi/igt@core_hotunplug@unbind-rebind.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-tgl-dsi/igt@core_hotunplug@unbind-rebind.html
- fi-icl-u2: [DMESG-WARN][25] ([i915#289]) -> [INCOMPLETE][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/fi-icl-u2/igt@core_hotunplug@unbind-rebind.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-icl-u2/igt@core_hotunplug@unbind-rebind.html
- fi-kbl-7500u: [PASS][27] -> [INCOMPLETE][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/fi-kbl-7500u/igt@core_hotunplug@unbind-rebind.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-kbl-7500u/igt@core_hotunplug@unbind-rebind.html
- fi-icl-y: [PASS][29] -> [INCOMPLETE][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/fi-icl-y/igt@core_hotunplug@unbind-rebind.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-icl-y/igt@core_hotunplug@unbind-rebind.html
- fi-cfl-8109u: [PASS][31] -> [INCOMPLETE][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/fi-cfl-8109u/igt@core_hotunplug@unbind-rebind.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-cfl-8109u/igt@core_hotunplug@unbind-rebind.html
- fi-kbl-guc: [DMESG-WARN][33] ([i915#2203]) -> [INCOMPLETE][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/fi-kbl-guc/igt@core_hotunplug@unbind-rebind.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-kbl-guc/igt@core_hotunplug@unbind-rebind.html
- fi-skl-guc: [DMESG-WARN][35] ([i915#2203]) -> [INCOMPLETE][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/fi-skl-guc/igt@core_hotunplug@unbind-rebind.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-skl-guc/igt@core_hotunplug@unbind-rebind.html
- fi-tgl-y: [PASS][37] -> [INCOMPLETE][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/fi-tgl-y/igt@core_hotunplug@unbind-rebind.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-tgl-y/igt@core_hotunplug@unbind-rebind.html
- fi-kbl-x1275: [PASS][39] -> [INCOMPLETE][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/fi-kbl-x1275/igt@core_hotunplug@unbind-rebind.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-kbl-x1275/igt@core_hotunplug@unbind-rebind.html
- fi-glk-dsi: [PASS][41] -> [INCOMPLETE][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/fi-glk-dsi/igt@core_hotunplug@unbind-rebind.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-glk-dsi/igt@core_hotunplug@unbind-rebind.html
* igt@runner@aborted:
- {fi-ehl-1}: NOTRUN -> [FAIL][43]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-ehl-1/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_18696 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-byt-j1900: [PASS][44] -> [DMESG-WARN][45] ([i915#1982])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1:
- fi-tgl-y: [PASS][46] -> [DMESG-WARN][47] ([i915#1982])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/fi-tgl-y/igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-tgl-y/igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1.html
* igt@prime_self_import@basic-with_one_bo_two_files:
- fi-tgl-y: [PASS][48] -> [DMESG-WARN][49] ([i915#402]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-tgl-y/igt@prime_self_import@basic-with_one_bo_two_files.html
#### Possible fixes ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [DMESG-WARN][50] ([i915#1982]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][52] ([i915#1161] / [i915#262]) -> [PASS][53]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: [DMESG-WARN][54] ([i915#1982]) -> [PASS][55] +1 similar issue
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- {fi-tgl-dsi}: [DMESG-WARN][56] ([i915#1982]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/fi-tgl-dsi/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-tgl-dsi/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
* {igt@prime_vgem@basic-userptr}:
- fi-tgl-y: [DMESG-WARN][58] ([i915#402]) -> [PASS][59] +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/fi-tgl-y/igt@prime_vgem@basic-userptr.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-tgl-y/igt@prime_vgem@basic-userptr.html
#### Warnings ####
* igt@gem_exec_suspend@basic-s3:
- fi-tgl-y: [DMESG-WARN][60] ([i915#2411] / [i915#402]) -> [DMESG-WARN][61] ([i915#2411])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/fi-tgl-y/igt@gem_exec_suspend@basic-s3.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1161]: https://gitlab.freedesktop.org/drm/intel/issues/1161
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
[i915#289]: https://gitlab.freedesktop.org/drm/intel/issues/289
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
Participating hosts (46 -> 40)
------------------------------
Missing (6): fi-cml-u2 fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper
Build changes
-------------
* Linux: CI_DRM_9137 -> Patchwork_18696
CI-20190529: 20190529
CI_DRM_9137: 9c7e985c2336328b14dd87c0f6a83af094f59d53 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5813: d4e6dd955a1dad02271aa41c9389f5097ee17765 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18696: ac59ab83da2ad34c09a723697b4ff7635e8b2cd7 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
ac59ab83da2a drm/i915/hdcp: Enable HDCP 2.2 MST support
0b04d5020a92 drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks
f47295717b3e drm/i915/hdcp: Add HDCP 2.2 stream register
1300b2ad499f drm/i915/hdcp: Pass connector to check_2_2_link
629f09e3ddea drm/i915/hdcp: mst streams support in hdcp port_data
03477decebcc drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port
86046073868b drm/i915/hdcp: Pass dig_port to intel_hdcp_init
87a4a87a3296 drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support
3a6056295149 drm/i915/hdcp: HDCP stream encryption support
ec157320f9ee drm/i915/hdcp: Move HDCP enc status timeout to header
2147d0efa227 drm/i915/hdcp: DP MST transcoder for link and stream
46a92a431c4f drm/i915/hotplug: Handle CP_IRQ for DP-MST
51e1dc4c0c75 drm/i915/hdcp: Update CP property in update_pipe
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/index.html
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for HDCP 2.2 DP MST Support (rev2)
2020-10-14 4:52 [Intel-gfx] [PATCH 00/13] HDCP 2.2 DP MST Support Anshuman Gupta
` (15 preceding siblings ...)
2020-10-14 5:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-10-14 16:03 ` Patchwork
2020-10-19 11:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for HDCP 2.2 DP MST Support (rev3) Patchwork
` (2 subsequent siblings)
19 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2020-10-14 16:03 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 26337 bytes --]
== Series Details ==
Series: HDCP 2.2 DP MST Support (rev2)
URL : https://patchwork.freedesktop.org/series/81538/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9137_full -> Patchwork_18696_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18696_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18696_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18696_full:
### IGT changes ###
#### Possible regressions ####
* igt@device_reset@unbind-reset-rebind:
- shard-glk: [PASS][1] -> [INCOMPLETE][2] +4 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-glk5/igt@device_reset@unbind-reset-rebind.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-glk8/igt@device_reset@unbind-reset-rebind.html
* igt@i915_module_load@reload:
- shard-skl: [PASS][3] -> [INCOMPLETE][4] +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-skl7/igt@i915_module_load@reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-skl3/igt@i915_module_load@reload.html
- shard-tglb: [PASS][5] -> [INCOMPLETE][6] +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-tglb5/igt@i915_module_load@reload.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-tglb1/igt@i915_module_load@reload.html
- shard-kbl: [PASS][7] -> [INCOMPLETE][8] +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-kbl6/igt@i915_module_load@reload.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-kbl1/igt@i915_module_load@reload.html
* igt@i915_module_load@reload-no-display:
- shard-iclb: [PASS][9] -> [INCOMPLETE][10] +2 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-iclb7/igt@i915_module_load@reload-no-display.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-iclb5/igt@i915_module_load@reload-no-display.html
* igt@i915_selftest@mock:
- shard-glk: NOTRUN -> [INCOMPLETE][11] +2 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-glk5/igt@i915_selftest@mock.html
- shard-iclb: NOTRUN -> [INCOMPLETE][12] +2 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-iclb1/igt@i915_selftest@mock.html
* igt@i915_selftest@perf:
- shard-kbl: NOTRUN -> [INCOMPLETE][13] +2 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-kbl6/igt@i915_selftest@perf.html
- shard-tglb: NOTRUN -> [INCOMPLETE][14] +2 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-tglb3/igt@i915_selftest@perf.html
- shard-skl: NOTRUN -> [INCOMPLETE][15] +2 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-skl3/igt@i915_selftest@perf.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
- shard-tglb: [PASS][16] -> [FAIL][17] +1 similar issue
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
* igt@runner@aborted:
- shard-kbl: NOTRUN -> ([FAIL][18], [FAIL][19], [FAIL][20], [FAIL][21], [FAIL][22], [FAIL][23], [FAIL][24], [FAIL][25], [FAIL][26]) ([i915#1436] / [i915#2292] / [i915#2439] / [i915#92] / [k.org#204565])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-kbl4/igt@runner@aborted.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-kbl1/igt@runner@aborted.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-kbl6/igt@runner@aborted.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-kbl1/igt@runner@aborted.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-kbl2/igt@runner@aborted.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-kbl1/igt@runner@aborted.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-kbl7/igt@runner@aborted.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-kbl2/igt@runner@aborted.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-kbl6/igt@runner@aborted.html
- shard-iclb: NOTRUN -> ([FAIL][27], [FAIL][28], [FAIL][29], [FAIL][30], [FAIL][31], [FAIL][32], [FAIL][33], [FAIL][34], [FAIL][35]) ([i915#1580] / [i915#2283] / [i915#2292] / [i915#2439] / [k.org#204565])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-iclb8/igt@runner@aborted.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-iclb1/igt@runner@aborted.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-iclb7/igt@runner@aborted.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-iclb5/igt@runner@aborted.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-iclb2/igt@runner@aborted.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-iclb3/igt@runner@aborted.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-iclb1/igt@runner@aborted.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-iclb4/igt@runner@aborted.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-iclb4/igt@runner@aborted.html
- shard-tglb: NOTRUN -> ([FAIL][36], [FAIL][37], [FAIL][38], [FAIL][39], [FAIL][40], [FAIL][41], [FAIL][42], [FAIL][43], [FAIL][44]) ([i915#1759] / [i915#1852] / [i915#2045] / [i915#2292] / [i915#2439] / [k.org#204565])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-tglb5/igt@runner@aborted.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-tglb5/igt@runner@aborted.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-tglb3/igt@runner@aborted.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-tglb2/igt@runner@aborted.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-tglb2/igt@runner@aborted.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-tglb6/igt@runner@aborted.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-tglb3/igt@runner@aborted.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-tglb1/igt@runner@aborted.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-tglb8/igt@runner@aborted.html
#### Warnings ####
* igt@runner@aborted:
- shard-skl: [FAIL][45] ([i915#1436]) -> ([FAIL][46], [FAIL][47], [FAIL][48], [FAIL][49], [FAIL][50], [FAIL][51], [FAIL][52], [FAIL][53], [FAIL][54]) ([i915#1436] / [i915#1982] / [i915#2292] / [i915#2439] / [k.org#204565])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-skl4/igt@runner@aborted.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-skl9/igt@runner@aborted.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-skl6/igt@runner@aborted.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-skl3/igt@runner@aborted.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-skl5/igt@runner@aborted.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-skl3/igt@runner@aborted.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-skl8/igt@runner@aborted.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-skl7/igt@runner@aborted.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-skl10/igt@runner@aborted.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-skl2/igt@runner@aborted.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@core_hotunplug@hotrebind-lateclose}:
- shard-iclb: [PASS][55] -> [INCOMPLETE][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-iclb4/igt@core_hotunplug@hotrebind-lateclose.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-iclb2/igt@core_hotunplug@hotrebind-lateclose.html
- shard-tglb: [PASS][57] -> [INCOMPLETE][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-tglb7/igt@core_hotunplug@hotrebind-lateclose.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-tglb3/igt@core_hotunplug@hotrebind-lateclose.html
- shard-glk: [PASS][59] -> [INCOMPLETE][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-glk7/igt@core_hotunplug@hotrebind-lateclose.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-glk1/igt@core_hotunplug@hotrebind-lateclose.html
- shard-skl: [PASS][61] -> [INCOMPLETE][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-skl4/igt@core_hotunplug@hotrebind-lateclose.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-skl8/igt@core_hotunplug@hotrebind-lateclose.html
- shard-kbl: [PASS][63] -> [INCOMPLETE][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-kbl7/igt@core_hotunplug@hotrebind-lateclose.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-kbl6/igt@core_hotunplug@hotrebind-lateclose.html
Known issues
------------
Here are the changes found in Patchwork_18696_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@device_reset@unbind-reset-rebind:
- shard-apl: [PASS][65] -> [INCOMPLETE][66] ([i915#1635]) +3 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-apl8/igt@device_reset@unbind-reset-rebind.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-apl7/igt@device_reset@unbind-reset-rebind.html
- shard-tglb: [PASS][67] -> [INCOMPLETE][68] ([i915#750])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-tglb1/igt@device_reset@unbind-reset-rebind.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-tglb6/igt@device_reset@unbind-reset-rebind.html
* igt@gem_exec_reloc@basic-many-active@vecs0:
- shard-glk: [PASS][69] -> [FAIL][70] ([i915#2389]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-glk5/igt@gem_exec_reloc@basic-many-active@vecs0.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-glk2/igt@gem_exec_reloc@basic-many-active@vecs0.html
* igt@gem_exec_whisper@basic-fds:
- shard-glk: [PASS][71] -> [DMESG-WARN][72] ([i915#118] / [i915#95])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-glk7/igt@gem_exec_whisper@basic-fds.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-glk4/igt@gem_exec_whisper@basic-fds.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: [PASS][73] -> [SKIP][74] ([i915#2190])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-tglb8/igt@gem_huc_copy@huc-copy.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-tglb6/igt@gem_huc_copy@huc-copy.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-skl: [PASS][75] -> [TIMEOUT][76] ([i915#2424]) +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-skl2/igt@gem_userptr_blits@unsync-unmap-cycles.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-skl9/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-skl: [PASS][77] -> [INCOMPLETE][78] ([i915#198])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-skl9/igt@i915_module_load@reload-with-fault-injection.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-skl7/igt@i915_module_load@reload-with-fault-injection.html
- shard-kbl: [PASS][79] -> [INCOMPLETE][80] ([i915#1373])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-kbl1/igt@i915_module_load@reload-with-fault-injection.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-kbl2/igt@i915_module_load@reload-with-fault-injection.html
- shard-apl: [PASS][81] -> [INCOMPLETE][82] ([i915#1373] / [i915#1635])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-apl8/igt@i915_module_load@reload-with-fault-injection.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-apl8/igt@i915_module_load@reload-with-fault-injection.html
- shard-iclb: [PASS][83] -> [INCOMPLETE][84] ([i915#926])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-iclb6/igt@i915_module_load@reload-with-fault-injection.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-iclb1/igt@i915_module_load@reload-with-fault-injection.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-skl: [PASS][85] -> [INCOMPLETE][86] ([i915#300])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-skl10/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-skl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge:
- shard-skl: [PASS][87] -> [DMESG-WARN][88] ([i915#1982]) +8 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-skl8/igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-skl4/igt@kms_cursor_edge_walk@pipe-b-256x256-left-edge.html
* igt@kms_cursor_edge_walk@pipe-c-128x128-top-edge:
- shard-glk: [PASS][89] -> [DMESG-WARN][90] ([i915#1982])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-glk6/igt@kms_cursor_edge_walk@pipe-c-128x128-top-edge.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-glk3/igt@kms_cursor_edge_walk@pipe-c-128x128-top-edge.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl: [PASS][91] -> [FAIL][92] ([i915#79])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
- shard-skl: [PASS][93] -> [FAIL][94] ([i915#2122])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-skl4/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-skl6/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: [PASS][95] -> [SKIP][96] ([fdo#109441]) +2 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-iclb2/igt@kms_psr@psr2_suspend.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-iclb7/igt@kms_psr@psr2_suspend.html
* igt@perf_pmu@module-unload:
- shard-iclb: [PASS][97] -> [INCOMPLETE][98] ([i915#1373])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-iclb1/igt@perf_pmu@module-unload.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-iclb3/igt@perf_pmu@module-unload.html
#### Possible fixes ####
* igt@api_intel_bb@offset-control:
- shard-skl: [DMESG-WARN][99] ([i915#1982]) -> [PASS][100] +2 similar issues
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-skl6/igt@api_intel_bb@offset-control.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-skl8/igt@api_intel_bb@offset-control.html
* igt@gem_exec_whisper@basic-queues:
- shard-glk: [DMESG-WARN][101] ([i915#118] / [i915#95]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-glk9/igt@gem_exec_whisper@basic-queues.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-glk4/igt@gem_exec_whisper@basic-queues.html
* {igt@kms_async_flips@async-flip-with-page-flip-events}:
- shard-kbl: [FAIL][103] ([i915#2521]) -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-kbl6/igt@kms_async_flips@async-flip-with-page-flip-events.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-kbl6/igt@kms_async_flips@async-flip-with-page-flip-events.html
- shard-tglb: [FAIL][105] ([i915#2521]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-tglb5/igt@kms_async_flips@async-flip-with-page-flip-events.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-tglb3/igt@kms_async_flips@async-flip-with-page-flip-events.html
* igt@kms_big_fb@linear-64bpp-rotate-0:
- shard-iclb: [DMESG-WARN][107] ([i915#1982]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-iclb3/igt@kms_big_fb@linear-64bpp-rotate-0.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-iclb6/igt@kms_big_fb@linear-64bpp-rotate-0.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt:
- shard-tglb: [FAIL][109] -> [PASS][110] +1 similar issue
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-shrfb-pgflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt:
- shard-tglb: [DMESG-WARN][111] ([i915#1982]) -> [PASS][112] +1 similar issue
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt:
- shard-tglb: [FAIL][113] ([i915#2416]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence:
- shard-skl: [FAIL][115] ([i915#53]) -> [PASS][116]
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-skl1/igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-skl1/igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][117] ([fdo#108145] / [i915#265]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [SKIP][119] ([fdo#109441]) -> [PASS][120] +1 similar issue
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-iclb4/igt@kms_psr@psr2_cursor_render.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
* igt@kms_setmode@basic:
- shard-glk: [FAIL][121] ([i915#31]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-glk8/igt@kms_setmode@basic.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-glk6/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-skl: [INCOMPLETE][123] ([i915#198]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-skl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-skl10/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-b-wait-busy-hang:
- shard-glk: [DMESG-WARN][125] ([i915#1982]) -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-glk2/igt@kms_vblank@pipe-b-wait-busy-hang.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-glk8/igt@kms_vblank@pipe-b-wait-busy-hang.html
#### Warnings ####
* igt@perf_pmu@module-unload:
- shard-tglb: [DMESG-WARN][127] ([i915#1982]) -> [INCOMPLETE][128] ([i915#1373])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-tglb3/igt@perf_pmu@module-unload.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-tglb8/igt@perf_pmu@module-unload.html
* igt@runner@aborted:
- shard-glk: [FAIL][129] ([i915#2439] / [k.org#202321]) -> ([FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138]) ([i915#2292] / [i915#2439] / [k.org#202321] / [k.org#204565])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9137/shard-glk1/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-glk2/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-glk7/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-glk5/igt@runner@aborted.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-glk1/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-glk9/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-glk3/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-glk8/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-glk6/igt@runner@aborted.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/shard-glk5/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1373]: https://gitlab.freedesktop.org/drm/intel/issues/1373
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1580]: https://gitlab.freedesktop.org/drm/intel/issues/1580
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1759]: https://gitlab.freedesktop.org/drm/intel/issues/1759
[i915#1852]: https://gitlab.freedesktop.org/drm/intel/issues/1852
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2045]: https://gitlab.freedesktop.org/drm/intel/issues/2045
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283
[i915#2292]: https://gitlab.freedesktop.org/drm/intel/issues/2292
[i915#2389]: https://gitlab.freedesktop.org/drm/intel/issues/2389
[i915#2416]: https://gitlab.freedesktop.org/drm/intel/issues/2416
[i915#2424]: https://gitlab.freedesktop.org/drm/intel/issues/2424
[i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53
[i915#750]: https://gitlab.freedesktop.org/drm/intel/issues/750
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#926]: https://gitlab.freedesktop.org/drm/intel/issues/926
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
[k.org#204565]: https://bugzilla.kernel.org/show_bug.cgi?id=204565
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_9137 -> Patchwork_18696
CI-20190529: 20190529
CI_DRM_9137: 9c7e985c2336328b14dd87c0f6a83af094f59d53 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5813: d4e6dd955a1dad02271aa41c9389f5097ee17765 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18696: ac59ab83da2ad34c09a723697b4ff7635e8b2cd7 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18696/index.html
[-- Attachment #1.2: Type: text/html, Size: 30508 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for HDCP 2.2 DP MST Support (rev3)
2020-10-14 4:52 [Intel-gfx] [PATCH 00/13] HDCP 2.2 DP MST Support Anshuman Gupta
` (16 preceding siblings ...)
2020-10-14 16:03 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-10-19 11:10 ` Patchwork
2020-10-19 11:12 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-10-19 11:41 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
19 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2020-10-19 11:10 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
== Series Details ==
Series: HDCP 2.2 DP MST Support (rev3)
URL : https://patchwork.freedesktop.org/series/81538/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d159760a4a56 drm/i915/hdcp: Update CP property in update_pipe
e2cb41b29aef drm/i915/hotplug: Handle CP_IRQ for DP-MST
a3760c25fe05 drm/i915/hdcp: DP MST transcoder for link and stream
cbd9c3a4e52a drm/i915/hdcp: Move HDCP enc status timeout to header
-:13: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 7e90e8d0c0ea ("drm/i915: Increase timeout for Encrypt status change")'
#13:
Related: 7e90e8d0c0ea ("drm/i915: Increase timeout for Encrypt
total: 1 errors, 0 warnings, 0 checks, 47 lines checked
4eb24e191127 drm/i915/hdcp: HDCP stream encryption support
b3989e70aca4 drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support
6b28dbb7e514 drm/i915/hdcp: Pass dig_port to intel_hdcp_init
5c581b2656f3 drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port
314fe93f46f3 drm/i915/hdcp: mst streams support in hdcp port_data
72ebe4518d5f drm/i915/hdcp: Pass connector to check_2_2_link
d98518fe6e4c drm/i915/hdcp: Add HDCP 2.2 stream register
b1bde86ff7ea drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks
f2b5ebaa2bd3 drm/i915/hdcp: Enable HDCP 2.2 MST support
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for HDCP 2.2 DP MST Support (rev3)
2020-10-14 4:52 [Intel-gfx] [PATCH 00/13] HDCP 2.2 DP MST Support Anshuman Gupta
` (17 preceding siblings ...)
2020-10-19 11:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for HDCP 2.2 DP MST Support (rev3) Patchwork
@ 2020-10-19 11:12 ` Patchwork
2020-10-19 11:41 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
19 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2020-10-19 11:12 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
== Series Details ==
Series: HDCP 2.2 DP MST Support (rev3)
URL : https://patchwork.freedesktop.org/series/81538/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:257:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:261:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+drivers/gpu/drm/i915/gt/intel_reset.c:1312:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gvt/mmio.c:290:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1440:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1494:15: warning: memset with byte count of 16777216
+./include/linux/seqlock.h:752:24: warning: trying to copy expression type 31
+./include/linux/seqlock.h:778:16: warning: trying to copy expression type 31
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 27+ messages in thread* [Intel-gfx] ✗ Fi.CI.BAT: failure for HDCP 2.2 DP MST Support (rev3)
2020-10-14 4:52 [Intel-gfx] [PATCH 00/13] HDCP 2.2 DP MST Support Anshuman Gupta
` (18 preceding siblings ...)
2020-10-19 11:12 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2020-10-19 11:41 ` Patchwork
19 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2020-10-19 11:41 UTC (permalink / raw)
To: Anshuman Gupta; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 13411 bytes --]
== Series Details ==
Series: HDCP 2.2 DP MST Support (rev3)
URL : https://patchwork.freedesktop.org/series/81538/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9162 -> Patchwork_18727
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18727 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18727, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18727:
### IGT changes ###
#### Possible regressions ####
* igt@core_hotunplug@unbind-rebind:
- fi-skl-lmem: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-skl-lmem/igt@core_hotunplug@unbind-rebind.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-skl-lmem/igt@core_hotunplug@unbind-rebind.html
- fi-tgl-u2: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html
- fi-cfl-guc: [PASS][5] -> [INCOMPLETE][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-cfl-guc/igt@core_hotunplug@unbind-rebind.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-cfl-guc/igt@core_hotunplug@unbind-rebind.html
- fi-skl-6600u: [PASS][7] -> [INCOMPLETE][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-skl-6600u/igt@core_hotunplug@unbind-rebind.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-skl-6600u/igt@core_hotunplug@unbind-rebind.html
- fi-cml-s: [PASS][9] -> [INCOMPLETE][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-cml-s/igt@core_hotunplug@unbind-rebind.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-cml-s/igt@core_hotunplug@unbind-rebind.html
- fi-kbl-soraka: [PASS][11] -> [INCOMPLETE][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-kbl-soraka/igt@core_hotunplug@unbind-rebind.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-kbl-soraka/igt@core_hotunplug@unbind-rebind.html
- fi-kbl-r: [PASS][13] -> [INCOMPLETE][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-kbl-r/igt@core_hotunplug@unbind-rebind.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-kbl-r/igt@core_hotunplug@unbind-rebind.html
- fi-cfl-8700k: [PASS][15] -> [INCOMPLETE][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-cfl-8700k/igt@core_hotunplug@unbind-rebind.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-cfl-8700k/igt@core_hotunplug@unbind-rebind.html
- fi-cml-u2: [PASS][17] -> [INCOMPLETE][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-cml-u2/igt@core_hotunplug@unbind-rebind.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-cml-u2/igt@core_hotunplug@unbind-rebind.html
- fi-kbl-7500u: [PASS][19] -> [INCOMPLETE][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-kbl-7500u/igt@core_hotunplug@unbind-rebind.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-kbl-7500u/igt@core_hotunplug@unbind-rebind.html
- fi-icl-y: [PASS][21] -> [INCOMPLETE][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-icl-y/igt@core_hotunplug@unbind-rebind.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-icl-y/igt@core_hotunplug@unbind-rebind.html
- fi-cfl-8109u: [PASS][23] -> [INCOMPLETE][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-cfl-8109u/igt@core_hotunplug@unbind-rebind.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-cfl-8109u/igt@core_hotunplug@unbind-rebind.html
- fi-kbl-x1275: [PASS][25] -> [INCOMPLETE][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-kbl-x1275/igt@core_hotunplug@unbind-rebind.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-kbl-x1275/igt@core_hotunplug@unbind-rebind.html
- fi-glk-dsi: [PASS][27] -> [INCOMPLETE][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-glk-dsi/igt@core_hotunplug@unbind-rebind.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-glk-dsi/igt@core_hotunplug@unbind-rebind.html
#### Warnings ####
* igt@core_hotunplug@unbind-rebind:
- fi-skl-6700k2: [DMESG-WARN][29] ([i915#2203]) -> [INCOMPLETE][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-skl-6700k2/igt@core_hotunplug@unbind-rebind.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-skl-6700k2/igt@core_hotunplug@unbind-rebind.html
- fi-icl-u2: [DMESG-WARN][31] ([i915#289]) -> [INCOMPLETE][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-icl-u2/igt@core_hotunplug@unbind-rebind.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-icl-u2/igt@core_hotunplug@unbind-rebind.html
- fi-kbl-guc: [DMESG-WARN][33] ([i915#2203]) -> [INCOMPLETE][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-kbl-guc/igt@core_hotunplug@unbind-rebind.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-kbl-guc/igt@core_hotunplug@unbind-rebind.html
- fi-skl-guc: [DMESG-WARN][35] ([i915#2203]) -> [INCOMPLETE][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-skl-guc/igt@core_hotunplug@unbind-rebind.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-skl-guc/igt@core_hotunplug@unbind-rebind.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@core_hotunplug@unbind-rebind:
- {fi-ehl-1}: [PASS][37] -> [INCOMPLETE][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-ehl-1/igt@core_hotunplug@unbind-rebind.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-ehl-1/igt@core_hotunplug@unbind-rebind.html
- {fi-kbl-7560u}: [PASS][39] -> [INCOMPLETE][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-kbl-7560u/igt@core_hotunplug@unbind-rebind.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-kbl-7560u/igt@core_hotunplug@unbind-rebind.html
- {fi-tgl-dsi}: [PASS][41] -> [INCOMPLETE][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-tgl-dsi/igt@core_hotunplug@unbind-rebind.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-tgl-dsi/igt@core_hotunplug@unbind-rebind.html
* igt@runner@aborted:
- {fi-ehl-1}: NOTRUN -> [FAIL][43]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-ehl-1/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_18727 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@core_hotunplug@unbind-rebind:
- fi-apl-guc: [PASS][44] -> [INCOMPLETE][45] ([i915#1635])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-apl-guc/igt@core_hotunplug@unbind-rebind.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-apl-guc/igt@core_hotunplug@unbind-rebind.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-byt-j1900: [PASS][46] -> [DMESG-WARN][47] ([i915#1982])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-byt-j1900/igt@i915_pm_rpm@basic-pci-d3-state.html
- fi-bsw-kefka: [PASS][48] -> [DMESG-WARN][49] ([i915#1982])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-apl-guc: [PASS][50] -> [DMESG-WARN][51] ([i915#1635] / [i915#1982])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-apl-guc/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-apl-guc/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_flip@basic-flip-vs-wf_vblank@b-edp1:
- fi-icl-u2: [PASS][52] -> [DMESG-WARN][53] ([i915#1982])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@b-edp1.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-icl-u2/igt@kms_flip@basic-flip-vs-wf_vblank@b-edp1.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- fi-blb-e6850: [INCOMPLETE][54] ([i915#2540]) -> [PASS][55]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-blb-e6850/igt@core_hotunplug@unbind-rebind.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-blb-e6850/igt@core_hotunplug@unbind-rebind.html
* igt@i915_module_load@reload:
- fi-byt-j1900: [DMESG-WARN][56] ([i915#1982]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-byt-j1900/igt@i915_module_load@reload.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-byt-j1900/igt@i915_module_load@reload.html
* igt@kms_busy@basic@flip:
- {fi-tgl-dsi}: [DMESG-WARN][58] ([i915#1982]) -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-tgl-dsi/igt@kms_busy@basic@flip.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-tgl-dsi/igt@kms_busy@basic@flip.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- {fi-kbl-7560u}: [DMESG-WARN][60] ([i915#1982]) -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-kbl-7560u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- fi-icl-u2: [DMESG-WARN][62] ([i915#1982]) -> [PASS][63]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- fi-bsw-kefka: [DMESG-WARN][64] ([i915#1982]) -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9162/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/fi-bsw-kefka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2203]: https://gitlab.freedesktop.org/drm/intel/issues/2203
[i915#2540]: https://gitlab.freedesktop.org/drm/intel/issues/2540
[i915#289]: https://gitlab.freedesktop.org/drm/intel/issues/289
Participating hosts (45 -> 39)
------------------------------
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9162 -> Patchwork_18727
CI-20190529: 20190529
CI_DRM_9162: 837e8c755c4a5087a1f87ccbe6893e37bd99ea85 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5821: 2bf22b1cff7905f7e214c0707941929a09450257 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18727: f2b5ebaa2bd3955d387e56528a83f613307acda9 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f2b5ebaa2bd3 drm/i915/hdcp: Enable HDCP 2.2 MST support
b1bde86ff7ea drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks
d98518fe6e4c drm/i915/hdcp: Add HDCP 2.2 stream register
72ebe4518d5f drm/i915/hdcp: Pass connector to check_2_2_link
314fe93f46f3 drm/i915/hdcp: mst streams support in hdcp port_data
5c581b2656f3 drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port
6b28dbb7e514 drm/i915/hdcp: Pass dig_port to intel_hdcp_init
b3989e70aca4 drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support
4eb24e191127 drm/i915/hdcp: HDCP stream encryption support
cbd9c3a4e52a drm/i915/hdcp: Move HDCP enc status timeout to header
a3760c25fe05 drm/i915/hdcp: DP MST transcoder for link and stream
e2cb41b29aef drm/i915/hotplug: Handle CP_IRQ for DP-MST
d159760a4a56 drm/i915/hdcp: Update CP property in update_pipe
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18727/index.html
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