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From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [CI 06/11] drm/i915/dg1: Enable DPLL for DG1
Date: Wed, 14 Oct 2020 12:19:32 -0700	[thread overview]
Message-ID: <20201014191937.1266226-6-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20201014191937.1266226-1-lucas.demarchi@intel.com>

Add DG1 DPLL Enable register macro and use the macro to enable the
correct DPLL based on PLL id. Although we use
_MG_PLL1_ENABLE/_MG_PLL2_ENABLE these are rather combo phys.

While at it, fix coding style: wrong newlines and use if/else chain

v2: Rewrite original patch from Aditya Swarup based on refactors
upstream

Bspec: 49443, 49206

Cc: Clinton Taylor <Clinton.A.Taylor@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Aditya Swarup <aditya.swarup@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 8 ++++----
 drivers/gpu/drm/i915/i915_reg.h               | 4 ++++
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 2f412d2c9d09..eaef7a2d041f 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -151,14 +151,14 @@ static i915_reg_t
 intel_combo_pll_enable_reg(struct drm_i915_private *i915,
 			   struct intel_shared_dpll *pll)
 {
-
-	if (IS_JSL_EHL(i915) && (pll->info->id == DPLL_ID_EHL_DPLL4))
+	if (IS_DG1(i915))
+		return DG1_DPLL_ENABLE(pll->info->id);
+	else if (IS_JSL_EHL(i915) && (pll->info->id == DPLL_ID_EHL_DPLL4))
 		return MG_PLL_ENABLE(0);
 
 	return CNL_DPLL_ENABLE(pll->info->id);
-
-
 }
+
 /**
  * intel_prepare_shared_dpll - call a dpll's prepare hook
  * @crtc_state: CRTC, and its state, which has a shared dpll
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0b67c868c51d..49945e33f573 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10316,6 +10316,10 @@ enum skl_power_gate {
 #define MG_PLL_ENABLE(tc_port)	_MMIO_PORT((tc_port), _MG_PLL1_ENABLE, \
 					   _MG_PLL2_ENABLE)
 
+/* DG1 PLL */
+#define DG1_DPLL_ENABLE(pll)    _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
+					   _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)
+
 #define _MG_REFCLKIN_CTL_PORT1				0x16892C
 #define _MG_REFCLKIN_CTL_PORT2				0x16992C
 #define _MG_REFCLKIN_CTL_PORT3				0x16A92C
-- 
2.28.0

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  parent reply	other threads:[~2020-10-14 19:21 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-14 19:19 [Intel-gfx] [CI 01/11] drm/i915/display: allow to skip certain power wells Lucas De Marchi
2020-10-14 19:19 ` [Intel-gfx] [CI 02/11] drm/i915/cnl: skip PW_DDI_F on certain skus Lucas De Marchi
2020-10-14 19:19 ` [Intel-gfx] [CI 03/11] drm/i915/dg1: Add DG1 power wells Lucas De Marchi
2020-10-14 19:19 ` [Intel-gfx] [CI 04/11] drm/i915/dg1: Add DPLL macros for DG1 Lucas De Marchi
2020-10-14 19:19 ` [Intel-gfx] [CI 05/11] drm/i915/dg1: Add and setup DPLLs " Lucas De Marchi
2020-10-14 19:19 ` Lucas De Marchi [this message]
2020-10-14 19:19 ` [Intel-gfx] [CI 07/11] drm/i915/dg1: Load DMC Lucas De Marchi
2020-10-14 19:19 ` [Intel-gfx] [CI 08/11] drm/i915/dg1: Add initial DG1 workarounds Lucas De Marchi
2020-10-14 19:19 ` [Intel-gfx] [CI 09/11] drm/i915/dg1: DG1 does not support DC6 Lucas De Marchi
2020-10-14 19:19 ` [Intel-gfx] [CI 10/11] drm/i915/dg1: Update DMC_DEBUG register Lucas De Marchi
2020-10-14 19:19 ` [Intel-gfx] [CI 11/11] drm/i915/dgfx: define llc and snooping behaviour Lucas De Marchi
2020-10-14 19:45 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,01/11] drm/i915/display: allow to skip certain power wells Patchwork
2020-10-14 19:47 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-10-14 20:10 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-14 21:16 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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