From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [CI 09/11] drm/i915/dg1: DG1 does not support DC6
Date: Wed, 14 Oct 2020 12:19:35 -0700 [thread overview]
Message-ID: <20201014191937.1266226-9-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20201014191937.1266226-1-lucas.demarchi@intel.com>
From: Anshuman Gupta <anshuman.gupta@intel.com>
DC6 is not supported on DG1, so change the allowed DC mask for DG1.
This is not yet on bspec, but it has been confirmed by HW engineers.
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 18af078c208b..45806cfc679a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4492,7 +4492,10 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
int max_dc;
if (INTEL_GEN(dev_priv) >= 12) {
- max_dc = 4;
+ if (IS_DG1(dev_priv))
+ max_dc = 3;
+ else
+ max_dc = 4;
/*
* DC9 has a separate HW flow from the rest of the DC states,
* not depending on the DMC firmware. It's needed by system
--
2.28.0
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next prev parent reply other threads:[~2020-10-14 19:21 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-14 19:19 [Intel-gfx] [CI 01/11] drm/i915/display: allow to skip certain power wells Lucas De Marchi
2020-10-14 19:19 ` [Intel-gfx] [CI 02/11] drm/i915/cnl: skip PW_DDI_F on certain skus Lucas De Marchi
2020-10-14 19:19 ` [Intel-gfx] [CI 03/11] drm/i915/dg1: Add DG1 power wells Lucas De Marchi
2020-10-14 19:19 ` [Intel-gfx] [CI 04/11] drm/i915/dg1: Add DPLL macros for DG1 Lucas De Marchi
2020-10-14 19:19 ` [Intel-gfx] [CI 05/11] drm/i915/dg1: Add and setup DPLLs " Lucas De Marchi
2020-10-14 19:19 ` [Intel-gfx] [CI 06/11] drm/i915/dg1: Enable DPLL " Lucas De Marchi
2020-10-14 19:19 ` [Intel-gfx] [CI 07/11] drm/i915/dg1: Load DMC Lucas De Marchi
2020-10-14 19:19 ` [Intel-gfx] [CI 08/11] drm/i915/dg1: Add initial DG1 workarounds Lucas De Marchi
2020-10-14 19:19 ` Lucas De Marchi [this message]
2020-10-14 19:19 ` [Intel-gfx] [CI 10/11] drm/i915/dg1: Update DMC_DEBUG register Lucas De Marchi
2020-10-14 19:19 ` [Intel-gfx] [CI 11/11] drm/i915/dgfx: define llc and snooping behaviour Lucas De Marchi
2020-10-14 19:45 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,01/11] drm/i915/display: allow to skip certain power wells Patchwork
2020-10-14 19:47 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-10-14 20:10 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-14 21:16 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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