* [Intel-gfx] [RFC 1/2] drm/i915: Improve record of hung engines in error state
@ 2020-11-04 12:20 Tvrtko Ursulin
2020-11-04 12:20 ` [Intel-gfx] [RFC 2/2] drm/i915: Use user engine names in error state ecode Tvrtko Ursulin
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: Tvrtko Ursulin @ 2020-11-04 12:20 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Between events which trigger engine and GPU resets and capturing the error
state we lose information on which engine triggered the reset. Improve
this by passing in the hung engine mask down to error capture.
Result is that the list of engines in user visible "GPU HANG: ecode
<gen>:<engines>:<ecode>, <process>" is now a list of hanging and not just
active engines. Most importantly the displayed process is now the one
which was actually hung.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 2 ++
drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 35 ++++++++++++++++++---------
drivers/gpu/drm/i915/i915_gpu_error.h | 7 ++++--
5 files changed, 32 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index f3eb68a76a25..8a51c1c3a091 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3037,6 +3037,8 @@ static struct execlists_capture *capture_regs(struct intel_engine_cs *engine)
if (!cap->error->gt->engine)
goto err_gt;
+ cap->error->gt->engine->hung = true;
+
return cap;
err_gt:
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 4e5e13dc95da..9fb4306b2900 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1251,7 +1251,7 @@ void intel_gt_handle_error(struct intel_gt *gt,
engine_mask &= gt->info.engine_mask;
if (flags & I915_ERROR_CAPTURE) {
- i915_capture_error_state(gt->i915);
+ i915_capture_error_state(gt, engine_mask);
intel_gt_clear_error_registers(gt, engine_mask);
}
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 200f6b86f864..77e76b665098 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -725,7 +725,7 @@ static int i915_gpu_info_open(struct inode *inode, struct file *file)
gpu = NULL;
with_intel_runtime_pm(&i915->runtime_pm, wakeref)
- gpu = i915_gpu_coredump(i915);
+ gpu = i915_gpu_coredump(&i915->gt, ALL_ENGINES);
if (IS_ERR(gpu))
return PTR_ERR(gpu);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index b3f3a2e07408..857db66cc4a3 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -570,6 +570,7 @@ static void error_print_engine(struct drm_i915_error_state_buf *m,
ee->vm_info.pp_dir_base);
}
}
+ err_printf(m, " hung: %u\n", ee->hung);
err_printf(m, " engine reset count: %u\n", ee->reset_count);
for (n = 0; n < ee->num_ports; n++) {
@@ -1456,6 +1457,7 @@ capture_engine(struct intel_engine_cs *engine,
static void
gt_record_engines(struct intel_gt_coredump *gt,
+ intel_engine_mask_t engine_mask,
struct i915_vma_compress *compress)
{
struct intel_engine_cs *engine;
@@ -1471,6 +1473,8 @@ gt_record_engines(struct intel_gt_coredump *gt,
if (!ee)
continue;
+ ee->hung = engine->mask & engine_mask;
+
gt->simulated |= ee->simulated;
if (ee->simulated) {
kfree(ee);
@@ -1663,11 +1667,13 @@ static const char *error_msg(struct i915_gpu_coredump *error)
for (gt = error->gt; gt; gt = gt->next) {
struct intel_engine_coredump *cs;
- if (gt->engine && !first)
- first = gt->engine;
-
- for (cs = gt->engine; cs; cs = cs->next)
- engines |= cs->engine->mask;
+ for (cs = gt->engine; cs; cs = cs->next) {
+ if (cs->hung) {
+ engines |= cs->engine->mask;
+ if (!first)
+ first = cs;
+ }
+ }
}
len = scnprintf(error->error_msg, sizeof(error->error_msg),
@@ -1781,8 +1787,10 @@ void i915_vma_capture_finish(struct intel_gt_coredump *gt,
kfree(compress);
}
-struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915)
+struct i915_gpu_coredump *
+i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask)
{
+ struct drm_i915_private *i915 = gt->i915;
struct i915_gpu_coredump *error;
/* Check if GPU capture has been disabled */
@@ -1794,7 +1802,7 @@ struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915)
if (!error)
return ERR_PTR(-ENOMEM);
- error->gt = intel_gt_coredump_alloc(&i915->gt, ALLOW_FAIL);
+ error->gt = intel_gt_coredump_alloc(gt, ALLOW_FAIL);
if (error->gt) {
struct i915_vma_compress *compress;
@@ -1806,7 +1814,7 @@ struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915)
}
gt_record_info(error->gt);
- gt_record_engines(error->gt, compress);
+ gt_record_engines(error->gt, engine_mask, compress);
if (INTEL_INFO(i915)->has_gt_uc)
error->gt->uc = gt_record_uc(error->gt, compress);
@@ -1853,20 +1861,23 @@ void i915_error_state_store(struct i915_gpu_coredump *error)
/**
* i915_capture_error_state - capture an error record for later analysis
- * @i915: i915 device
+ * @gt: intel_gt which originated the hang
+ * @engine_mask: hung engines
+ *
*
* Should be called when an error is detected (either a hang or an error
* interrupt) to capture error state from the time of the error. Fills
* out a structure which becomes available in debugfs for user level tools
* to pick up.
*/
-void i915_capture_error_state(struct drm_i915_private *i915)
+void i915_capture_error_state(struct intel_gt *gt,
+ intel_engine_mask_t engine_mask)
{
struct i915_gpu_coredump *error;
- error = i915_gpu_coredump(i915);
+ error = i915_gpu_coredump(gt, engine_mask);
if (IS_ERR(error)) {
- cmpxchg(&i915->gpu_error.first_error, NULL, error);
+ cmpxchg(>->i915->gpu_error.first_error, NULL, error);
return;
}
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h b/drivers/gpu/drm/i915/i915_gpu_error.h
index 0220b0992808..3a7ca90a3436 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.h
+++ b/drivers/gpu/drm/i915/i915_gpu_error.h
@@ -59,6 +59,7 @@ struct i915_request_coredump {
struct intel_engine_coredump {
const struct intel_engine_cs *engine;
+ bool hung;
bool simulated;
u32 reset_count;
@@ -218,8 +219,10 @@ struct drm_i915_error_state_buf {
__printf(2, 3)
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
-struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915);
-void i915_capture_error_state(struct drm_i915_private *i915);
+struct i915_gpu_coredump *i915_gpu_coredump(struct intel_gt *gt,
+ intel_engine_mask_t engine_mask);
+void i915_capture_error_state(struct intel_gt *gt,
+ intel_engine_mask_t engine_mask);
struct i915_gpu_coredump *
i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp);
--
2.25.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] [RFC 2/2] drm/i915: Use user engine names in error state ecode
2020-11-04 12:20 [Intel-gfx] [RFC 1/2] drm/i915: Improve record of hung engines in error state Tvrtko Ursulin
@ 2020-11-04 12:20 ` Tvrtko Ursulin
2020-11-04 12:33 ` Chris Wilson
2020-11-04 12:30 ` [Intel-gfx] [RFC 1/2] drm/i915: Improve record of hung engines in error state Chris Wilson
` (2 subsequent siblings)
3 siblings, 1 reply; 10+ messages in thread
From: Tvrtko Ursulin @ 2020-11-04 12:20 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Instead of printing out the internal engine mask, which can change between
kernel versions making it difficult to map to actual engines, list user
friendly engine names in the ecode string. For example:
[drm] GPU HANG: ecode 9:vcs1:a77ffefe, in gem_exec_captur [929]
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/i915_gpu_error.c | 38 ++++++++++++++++-----------
drivers/gpu/drm/i915/i915_gpu_error.h | 2 +-
2 files changed, 24 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 857db66cc4a3..ce876e3f3ec5 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1659,32 +1659,40 @@ static u32 generate_ecode(const struct intel_engine_coredump *ee)
static const char *error_msg(struct i915_gpu_coredump *error)
{
struct intel_engine_coredump *first = NULL;
+ int space = sizeof(error->error_msg) - 1, len;
struct intel_gt_coredump *gt;
- intel_engine_mask_t engines;
- int len;
+ char *p = error->error_msg;
+
+ len = scnprintf(p, space, "GPU HANG: ecode %d:",
+ INTEL_GEN(error->i915));
+ p += len;
+ space -= len;
- engines = 0;
for (gt = error->gt; gt; gt = gt->next) {
struct intel_engine_coredump *cs;
for (cs = gt->engine; cs; cs = cs->next) {
- if (cs->hung) {
- engines |= cs->engine->mask;
- if (!first)
- first = cs;
- }
+ if (!cs->hung)
+ continue;
+
+ len = scnprintf(p, space, "%s%s",
+ first ? "," : "",
+ cs->engine->name);
+ p += len;
+ space -= len;
+
+ if (!first)
+ first = cs;
}
}
- len = scnprintf(error->error_msg, sizeof(error->error_msg),
- "GPU HANG: ecode %d:%x:%08x",
- INTEL_GEN(error->i915), engines,
- generate_ecode(first));
+ len = scnprintf(p, space, ":%08x", generate_ecode(first));
+ p += len;
+ space -= len;
+
if (first && first->context.pid) {
/* Just show the first executing process, more is confusing */
- len += scnprintf(error->error_msg + len,
- sizeof(error->error_msg) - len,
- ", in %s [%d]",
+ len += scnprintf(p, space, ", in %s [%d]",
first->context.comm, first->context.pid);
}
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h b/drivers/gpu/drm/i915/i915_gpu_error.h
index 3a7ca90a3436..6b8573ddbe67 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.h
+++ b/drivers/gpu/drm/i915/i915_gpu_error.h
@@ -168,7 +168,7 @@ struct i915_gpu_coredump {
struct intel_gt_coredump *gt;
- char error_msg[128];
+ char error_msg[256];
bool simulated;
bool wakelock;
bool suspended;
--
2.25.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [RFC 1/2] drm/i915: Improve record of hung engines in error state
2020-11-04 12:20 [Intel-gfx] [RFC 1/2] drm/i915: Improve record of hung engines in error state Tvrtko Ursulin
2020-11-04 12:20 ` [Intel-gfx] [RFC 2/2] drm/i915: Use user engine names in error state ecode Tvrtko Ursulin
@ 2020-11-04 12:30 ` Chris Wilson
2020-11-04 13:03 ` Tvrtko Ursulin
2020-11-04 13:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [RFC,1/2] " Patchwork
2020-11-04 15:37 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
3 siblings, 1 reply; 10+ messages in thread
From: Chris Wilson @ 2020-11-04 12:30 UTC (permalink / raw)
To: Intel-gfx, Tvrtko Ursulin
Quoting Tvrtko Ursulin (2020-11-04 12:20:42)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Between events which trigger engine and GPU resets and capturing the error
> state we lose information on which engine triggered the reset. Improve
> this by passing in the hung engine mask down to error capture.
>
> Result is that the list of engines in user visible "GPU HANG: ecode
> <gen>:<engines>:<ecode>, <process>" is now a list of hanging and not just
> active engines. Most importantly the displayed process is now the one
> which was actually hung.
You could also suggest to only include the hanging engine in the report,
as is intended to be the normal means of generating the report
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h b/drivers/gpu/drm/i915/i915_gpu_error.h
> index 0220b0992808..3a7ca90a3436 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.h
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.h
> @@ -59,6 +59,7 @@ struct i915_request_coredump {
> struct intel_engine_coredump {
> const struct intel_engine_cs *engine;
>
> + bool hung;
> bool simulated;
> u32 reset_count;
>
> @@ -218,8 +219,10 @@ struct drm_i915_error_state_buf {
> __printf(2, 3)
> void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
>
> -struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915);
> -void i915_capture_error_state(struct drm_i915_private *i915);
> +struct i915_gpu_coredump *i915_gpu_coredump(struct intel_gt *gt,
> + intel_engine_mask_t engine_mask);
> +void i915_capture_error_state(struct intel_gt *gt,
> + intel_engine_mask_t engine_mask);
Don't forget the stubs.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [RFC 2/2] drm/i915: Use user engine names in error state ecode
2020-11-04 12:20 ` [Intel-gfx] [RFC 2/2] drm/i915: Use user engine names in error state ecode Tvrtko Ursulin
@ 2020-11-04 12:33 ` Chris Wilson
2020-11-04 13:06 ` Tvrtko Ursulin
0 siblings, 1 reply; 10+ messages in thread
From: Chris Wilson @ 2020-11-04 12:33 UTC (permalink / raw)
To: Intel-gfx, Tvrtko Ursulin
Quoting Tvrtko Ursulin (2020-11-04 12:20:43)
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Instead of printing out the internal engine mask, which can change between
> kernel versions making it difficult to map to actual engines, list user
> friendly engine names in the ecode string. For example:
Nah. It's a nonsense number, just exists for quick and futile discrimination.
Trying to interpret it is pointless.
There's very little value to be gained from it, it should just serve as a
tale-tell that we have captured an error state. The action and impact of
the reset should be separately recorded.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [RFC 1/2] drm/i915: Improve record of hung engines in error state
2020-11-04 12:30 ` [Intel-gfx] [RFC 1/2] drm/i915: Improve record of hung engines in error state Chris Wilson
@ 2020-11-04 13:03 ` Tvrtko Ursulin
0 siblings, 0 replies; 10+ messages in thread
From: Tvrtko Ursulin @ 2020-11-04 13:03 UTC (permalink / raw)
To: Chris Wilson, Intel-gfx
On 04/11/2020 12:30, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2020-11-04 12:20:42)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Between events which trigger engine and GPU resets and capturing the error
>> state we lose information on which engine triggered the reset. Improve
>> this by passing in the hung engine mask down to error capture.
>>
>> Result is that the list of engines in user visible "GPU HANG: ecode
>> <gen>:<engines>:<ecode>, <process>" is now a list of hanging and not just
>> active engines. Most importantly the displayed process is now the one
>> which was actually hung.
>
> You could also suggest to only include the hanging engine in the report,
> as is intended to be the normal means of generating the report
I thought it is potentially useful to have a full picture, but can do
that as well.
>> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h b/drivers/gpu/drm/i915/i915_gpu_error.h
>> index 0220b0992808..3a7ca90a3436 100644
>> --- a/drivers/gpu/drm/i915/i915_gpu_error.h
>> +++ b/drivers/gpu/drm/i915/i915_gpu_error.h
>> @@ -59,6 +59,7 @@ struct i915_request_coredump {
>> struct intel_engine_coredump {
>> const struct intel_engine_cs *engine;
>>
>> + bool hung;
>> bool simulated;
>> u32 reset_count;
>>
>> @@ -218,8 +219,10 @@ struct drm_i915_error_state_buf {
>> __printf(2, 3)
>> void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
>>
>> -struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915);
>> -void i915_capture_error_state(struct drm_i915_private *i915);
>> +struct i915_gpu_coredump *i915_gpu_coredump(struct intel_gt *gt,
>> + intel_engine_mask_t engine_mask);
>> +void i915_capture_error_state(struct intel_gt *gt,
>> + intel_engine_mask_t engine_mask);
>
> Don't forget the stubs.
Right, thanks.
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [RFC 2/2] drm/i915: Use user engine names in error state ecode
2020-11-04 12:33 ` Chris Wilson
@ 2020-11-04 13:06 ` Tvrtko Ursulin
2020-11-04 13:21 ` Chris Wilson
0 siblings, 1 reply; 10+ messages in thread
From: Tvrtko Ursulin @ 2020-11-04 13:06 UTC (permalink / raw)
To: Chris Wilson, Intel-gfx
On 04/11/2020 12:33, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2020-11-04 12:20:43)
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Instead of printing out the internal engine mask, which can change between
>> kernel versions making it difficult to map to actual engines, list user
>> friendly engine names in the ecode string. For example:
>
> Nah. It's a nonsense number, just exists for quick and futile discrimination.
> Trying to interpret it is pointless.
>
> There's very little value to be gained from it, it should just serve as a
> tale-tell that we have captured an error state. The action and impact of
> the reset should be separately recorded.
My problem with the nonsense number is that we have it, but that is is
unstable and people are interpreting it.
How about a bitmask of uabi classes instead? As you can see I really
want something from the ABI-land, or not at all. Classes might be just
the thing for the purpose of a signature.
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [RFC,1/2] drm/i915: Improve record of hung engines in error state
2020-11-04 12:20 [Intel-gfx] [RFC 1/2] drm/i915: Improve record of hung engines in error state Tvrtko Ursulin
2020-11-04 12:20 ` [Intel-gfx] [RFC 2/2] drm/i915: Use user engine names in error state ecode Tvrtko Ursulin
2020-11-04 12:30 ` [Intel-gfx] [RFC 1/2] drm/i915: Improve record of hung engines in error state Chris Wilson
@ 2020-11-04 13:19 ` Patchwork
2020-11-04 15:37 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
3 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2020-11-04 13:19 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 5634 bytes --]
== Series Details ==
Series: series starting with [RFC,1/2] drm/i915: Improve record of hung engines in error state
URL : https://patchwork.freedesktop.org/series/83493/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9263 -> Patchwork_18850
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/index.html
New tests
---------
New tests have been introduced between CI_DRM_9263 and Patchwork_18850:
### New CI tests (1) ###
* boot:
- Statuses : 40 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_18850 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload:
- fi-byt-j1900: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-byt-j1900/igt@i915_module_load@reload.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/fi-byt-j1900/igt@i915_module_load@reload.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-bsw-kefka: [PASS][3] -> [DMESG-WARN][4] ([i915#1982])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/fi-bsw-kefka/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: [PASS][5] -> [DMESG-FAIL][6] ([i915#541])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-icl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#1982]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [PASS][9] -> [DMESG-WARN][10] ([i915#165]) +15 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html
- fi-icl-u2: [DMESG-WARN][13] ([i915#1982]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-icl-u2/igt@core_hotunplug@unbind-rebind.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/fi-icl-u2/igt@core_hotunplug@unbind-rebind.html
* igt@i915_pm_rpm@module-reload:
- fi-byt-j1900: [DMESG-WARN][15] ([i915#1982]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/fi-byt-j1900/igt@i915_pm_rpm@module-reload.html
- fi-apl-guc: [DMESG-WARN][17] ([i915#1635] / [i915#1982]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-apl-guc/igt@i915_pm_rpm@module-reload.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/fi-apl-guc/igt@i915_pm_rpm@module-reload.html
* igt@kms_flip@basic-flip-vs-modeset@d-dsi1:
- {fi-tgl-dsi}: [DMESG-WARN][19] ([i915#1982]) -> [PASS][20] +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/fi-tgl-dsi/igt@kms_flip@basic-flip-vs-modeset@d-dsi1.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/fi-tgl-dsi/igt@kms_flip@basic-flip-vs-modeset@d-dsi1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Participating hosts (45 -> 40)
------------------------------
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9263 -> Patchwork_18850
CI-20190529: 20190529
CI_DRM_9263: d024f57bbf34cd9dedaff4d026a7ed8f58325bad @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5832: 9c583f7e2a6638b5ff6a3682fea548a1313512e7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18850: ca731d18e828dccce4340125ea27f22e0f6d6e84 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
ca731d18e828 drm/i915: Use user engine names in error state ecode
3c852854e2b3 drm/i915: Improve record of hung engines in error state
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/index.html
[-- Attachment #1.2: Type: text/html, Size: 6921 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Intel-gfx] [RFC 2/2] drm/i915: Use user engine names in error state ecode
2020-11-04 13:06 ` Tvrtko Ursulin
@ 2020-11-04 13:21 ` Chris Wilson
0 siblings, 0 replies; 10+ messages in thread
From: Chris Wilson @ 2020-11-04 13:21 UTC (permalink / raw)
To: Intel-gfx, Tvrtko Ursulin
Quoting Tvrtko Ursulin (2020-11-04 13:06:43)
>
> On 04/11/2020 12:33, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2020-11-04 12:20:43)
> >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >>
> >> Instead of printing out the internal engine mask, which can change between
> >> kernel versions making it difficult to map to actual engines, list user
> >> friendly engine names in the ecode string. For example:
> >
> > Nah. It's a nonsense number, just exists for quick and futile discrimination.
> > Trying to interpret it is pointless.
> >
> > There's very little value to be gained from it, it should just serve as a
> > tale-tell that we have captured an error state. The action and impact of
> > the reset should be separately recorded.
>
> My problem with the nonsense number is that we have it, but that is is
> unstable and people are interpreting it.
>
> How about a bitmask of uabi classes instead? As you can see I really
> want something from the ABI-land, or not at all. Classes might be just
> the thing for the purpose of a signature.
You can probably tell I've been pushing for the not-at-all :)
I've personally not found it helpful, it's too simplistic and unstable
even for repeated GL hangs. The concept of having a hash that can
summarise the hang is definitely a good idea, but the input to that hash
is flawed.
Given that we record the reset action, and the context that was
impacted, I wonder how much we need to say here. Just announce a new
error state has been captured?
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Intel-gfx] [RFC 1/2] drm/i915: Improve record of hung engines in error state
@ 2020-11-04 13:47 Tvrtko Ursulin
0 siblings, 0 replies; 10+ messages in thread
From: Tvrtko Ursulin @ 2020-11-04 13:47 UTC (permalink / raw)
To: Intel-gfx
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Between events which trigger engine and GPU resets and capturing the error
state we lose information on which engine triggered the reset. Improve
this by passing in the hung engine mask down to error capture.
Result is that the list of engines in user visible "GPU HANG: ecode
<gen>:<engines>:<ecode>, <process>" is now a list of hanging and not just
active engines. Most importantly the displayed process is now the one
which was actually hung.
v2:
* Stub prototype. (Chris)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 2 ++
drivers/gpu/drm/i915/gt/intel_reset.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 35 ++++++++++++++++++---------
drivers/gpu/drm/i915/i915_gpu_error.h | 10 +++++---
5 files changed, 34 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index f3eb68a76a25..8a51c1c3a091 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3037,6 +3037,8 @@ static struct execlists_capture *capture_regs(struct intel_engine_cs *engine)
if (!cap->error->gt->engine)
goto err_gt;
+ cap->error->gt->engine->hung = true;
+
return cap;
err_gt:
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index 4e5e13dc95da..9fb4306b2900 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1251,7 +1251,7 @@ void intel_gt_handle_error(struct intel_gt *gt,
engine_mask &= gt->info.engine_mask;
if (flags & I915_ERROR_CAPTURE) {
- i915_capture_error_state(gt->i915);
+ i915_capture_error_state(gt, engine_mask);
intel_gt_clear_error_registers(gt, engine_mask);
}
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 200f6b86f864..77e76b665098 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -725,7 +725,7 @@ static int i915_gpu_info_open(struct inode *inode, struct file *file)
gpu = NULL;
with_intel_runtime_pm(&i915->runtime_pm, wakeref)
- gpu = i915_gpu_coredump(i915);
+ gpu = i915_gpu_coredump(&i915->gt, ALL_ENGINES);
if (IS_ERR(gpu))
return PTR_ERR(gpu);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index b3f3a2e07408..857db66cc4a3 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -570,6 +570,7 @@ static void error_print_engine(struct drm_i915_error_state_buf *m,
ee->vm_info.pp_dir_base);
}
}
+ err_printf(m, " hung: %u\n", ee->hung);
err_printf(m, " engine reset count: %u\n", ee->reset_count);
for (n = 0; n < ee->num_ports; n++) {
@@ -1456,6 +1457,7 @@ capture_engine(struct intel_engine_cs *engine,
static void
gt_record_engines(struct intel_gt_coredump *gt,
+ intel_engine_mask_t engine_mask,
struct i915_vma_compress *compress)
{
struct intel_engine_cs *engine;
@@ -1471,6 +1473,8 @@ gt_record_engines(struct intel_gt_coredump *gt,
if (!ee)
continue;
+ ee->hung = engine->mask & engine_mask;
+
gt->simulated |= ee->simulated;
if (ee->simulated) {
kfree(ee);
@@ -1663,11 +1667,13 @@ static const char *error_msg(struct i915_gpu_coredump *error)
for (gt = error->gt; gt; gt = gt->next) {
struct intel_engine_coredump *cs;
- if (gt->engine && !first)
- first = gt->engine;
-
- for (cs = gt->engine; cs; cs = cs->next)
- engines |= cs->engine->mask;
+ for (cs = gt->engine; cs; cs = cs->next) {
+ if (cs->hung) {
+ engines |= cs->engine->mask;
+ if (!first)
+ first = cs;
+ }
+ }
}
len = scnprintf(error->error_msg, sizeof(error->error_msg),
@@ -1781,8 +1787,10 @@ void i915_vma_capture_finish(struct intel_gt_coredump *gt,
kfree(compress);
}
-struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915)
+struct i915_gpu_coredump *
+i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask)
{
+ struct drm_i915_private *i915 = gt->i915;
struct i915_gpu_coredump *error;
/* Check if GPU capture has been disabled */
@@ -1794,7 +1802,7 @@ struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915)
if (!error)
return ERR_PTR(-ENOMEM);
- error->gt = intel_gt_coredump_alloc(&i915->gt, ALLOW_FAIL);
+ error->gt = intel_gt_coredump_alloc(gt, ALLOW_FAIL);
if (error->gt) {
struct i915_vma_compress *compress;
@@ -1806,7 +1814,7 @@ struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915)
}
gt_record_info(error->gt);
- gt_record_engines(error->gt, compress);
+ gt_record_engines(error->gt, engine_mask, compress);
if (INTEL_INFO(i915)->has_gt_uc)
error->gt->uc = gt_record_uc(error->gt, compress);
@@ -1853,20 +1861,23 @@ void i915_error_state_store(struct i915_gpu_coredump *error)
/**
* i915_capture_error_state - capture an error record for later analysis
- * @i915: i915 device
+ * @gt: intel_gt which originated the hang
+ * @engine_mask: hung engines
+ *
*
* Should be called when an error is detected (either a hang or an error
* interrupt) to capture error state from the time of the error. Fills
* out a structure which becomes available in debugfs for user level tools
* to pick up.
*/
-void i915_capture_error_state(struct drm_i915_private *i915)
+void i915_capture_error_state(struct intel_gt *gt,
+ intel_engine_mask_t engine_mask)
{
struct i915_gpu_coredump *error;
- error = i915_gpu_coredump(i915);
+ error = i915_gpu_coredump(gt, engine_mask);
if (IS_ERR(error)) {
- cmpxchg(&i915->gpu_error.first_error, NULL, error);
+ cmpxchg(>->i915->gpu_error.first_error, NULL, error);
return;
}
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h b/drivers/gpu/drm/i915/i915_gpu_error.h
index 0220b0992808..16bc42de4b84 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.h
+++ b/drivers/gpu/drm/i915/i915_gpu_error.h
@@ -59,6 +59,7 @@ struct i915_request_coredump {
struct intel_engine_coredump {
const struct intel_engine_cs *engine;
+ bool hung;
bool simulated;
u32 reset_count;
@@ -218,8 +219,10 @@ struct drm_i915_error_state_buf {
__printf(2, 3)
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
-struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915);
-void i915_capture_error_state(struct drm_i915_private *i915);
+struct i915_gpu_coredump *i915_gpu_coredump(struct intel_gt *gt,
+ intel_engine_mask_t engine_mask);
+void i915_capture_error_state(struct intel_gt *gt,
+ intel_engine_mask_t engine_mask);
struct i915_gpu_coredump *
i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp);
@@ -271,7 +274,8 @@ void i915_disable_error_state(struct drm_i915_private *i915, int err);
#else
-static inline void i915_capture_error_state(struct drm_i915_private *i915)
+static inline void
+i915_capture_error_state(struct intel_gt *gt, intel_engine_mask_t engine_mask)
{
}
--
2.25.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [RFC,1/2] drm/i915: Improve record of hung engines in error state
2020-11-04 12:20 [Intel-gfx] [RFC 1/2] drm/i915: Improve record of hung engines in error state Tvrtko Ursulin
` (2 preceding siblings ...)
2020-11-04 13:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [RFC,1/2] " Patchwork
@ 2020-11-04 15:37 ` Patchwork
3 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2020-11-04 15:37 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 17853 bytes --]
== Series Details ==
Series: series starting with [RFC,1/2] drm/i915: Improve record of hung engines in error state
URL : https://patchwork.freedesktop.org/series/83493/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9263_full -> Patchwork_18850_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_18850_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18850_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18850_full:
### IGT changes ###
#### Possible regressions ####
* igt@gen7_exec_parse@basic-allowed:
- shard-hsw: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-hsw6/igt@gen7_exec_parse@basic-allowed.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-hsw1/igt@gen7_exec_parse@basic-allowed.html
New tests
---------
New tests have been introduced between CI_DRM_9263_full and Patchwork_18850_full:
### New CI tests (1) ###
* boot:
- Statuses : 200 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_18850_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@core_hotunplug@hotrebind-lateclose:
- shard-snb: [PASS][3] -> [INCOMPLETE][4] ([i915#82])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-snb4/igt@core_hotunplug@hotrebind-lateclose.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-snb5/igt@core_hotunplug@hotrebind-lateclose.html
* igt@gem_exec_schedule@submit-late-slice@rcs0:
- shard-glk: [PASS][5] -> [INCOMPLETE][6] ([i915#1888])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-glk6/igt@gem_exec_schedule@submit-late-slice@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-glk2/igt@gem_exec_schedule@submit-late-slice@rcs0.html
* igt@gem_exec_whisper@basic-fds-priority:
- shard-glk: [PASS][7] -> [DMESG-WARN][8] ([i915#118] / [i915#95])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-glk2/igt@gem_exec_whisper@basic-fds-priority.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-glk3/igt@gem_exec_whisper@basic-fds-priority.html
* igt@gem_exec_whisper@basic-normal-all:
- shard-hsw: [PASS][9] -> [FAIL][10] ([i915#1888]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-hsw6/igt@gem_exec_whisper@basic-normal-all.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-hsw1/igt@gem_exec_whisper@basic-normal-all.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][11] -> [FAIL][12] ([i915#454])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-iclb6/igt@i915_pm_dc@dc6-psr.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- shard-skl: [PASS][13] -> [DMESG-WARN][14] ([i915#1982]) +6 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-skl2/igt@i915_pm_rpm@modeset-lpsp-stress.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-skl4/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@kms_color@pipe-b-ctm-0-5:
- shard-glk: [PASS][15] -> [FAIL][16] ([i915#182])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-glk3/igt@kms_color@pipe-b-ctm-0-5.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-glk4/igt@kms_color@pipe-b-ctm-0-5.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-skl: [PASS][17] -> [INCOMPLETE][18] ([i915#300])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-skl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-skl8/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-c-cursor-128x42-offscreen:
- shard-skl: [PASS][19] -> [FAIL][20] ([i915#54])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-skl8/igt@kms_cursor_crc@pipe-c-cursor-128x42-offscreen.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-skl9/igt@kms_cursor_crc@pipe-c-cursor-128x42-offscreen.html
* igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
- shard-tglb: [PASS][21] -> [FAIL][22] ([i915#2346])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-tglb6/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-tglb6/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [PASS][23] -> [FAIL][24] ([i915#79])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-skl2/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt:
- shard-snb: [PASS][25] -> [FAIL][26] ([i915#2546])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-snb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-snb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-render:
- shard-glk: [PASS][27] -> [FAIL][28] ([i915#49]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-glk3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-render.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-glk4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-cpu:
- shard-tglb: [PASS][29] -> [DMESG-WARN][30] ([i915#1982])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-tglb1/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-cpu.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-rgb101010-draw-mmap-cpu.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [PASS][31] -> [FAIL][32] ([i915#1188])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-skl6/igt@kms_hdr@bpc-switch.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-skl8/igt@kms_hdr@bpc-switch.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence:
- shard-glk: [PASS][33] -> [FAIL][34] ([i915#53])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-glk3/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-glk4/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-iclb: [PASS][35] -> [SKIP][36] ([fdo#109441]) +2 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-iclb3/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@kms_universal_plane@universal-plane-gen9-features-pipe-b:
- shard-apl: [PASS][37] -> [DMESG-WARN][38] ([i915#1635] / [i915#1982]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-apl8/igt@kms_universal_plane@universal-plane-gen9-features-pipe-b.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-apl3/igt@kms_universal_plane@universal-plane-gen9-features-pipe-b.html
#### Possible fixes ####
* igt@gem_eio@kms:
- shard-hsw: [INCOMPLETE][39] ([i915#1888] / [i915#2244]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-hsw8/igt@gem_eio@kms.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-hsw1/igt@gem_eio@kms.html
* igt@gem_exec_whisper@basic-queues-all:
- shard-glk: [DMESG-WARN][41] ([i915#118] / [i915#95]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-glk8/igt@gem_exec_whisper@basic-queues-all.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-glk9/igt@gem_exec_whisper@basic-queues-all.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-180:
- shard-glk: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-glk9/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-glk1/igt@kms_big_fb@yf-tiled-32bpp-rotate-180.html
* igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding:
- shard-skl: [FAIL][45] ([i915#54]) -> [PASS][46] +3 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-skl7/igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-skl10/igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size:
- shard-hsw: [FAIL][47] ([i915#2370]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-hsw2/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@cursor-vs-flip-toggle:
- shard-iclb: [DMESG-WARN][49] ([i915#1226]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-iclb8/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-iclb5/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [FAIL][51] ([i915#2346]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl: [FAIL][53] ([i915#79]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt:
- shard-apl: [DMESG-WARN][55] ([i915#1635] / [i915#1982]) -> [PASS][56] +2 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-apl7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-apl6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-modesetfrombusy:
- shard-iclb: [FAIL][57] ([i915#49]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-iclb8/igt@kms_frontbuffer_tracking@psr-modesetfrombusy.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-iclb5/igt@kms_frontbuffer_tracking@psr-modesetfrombusy.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [FAIL][59] ([fdo#108145] / [i915#265]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_plane_cursor@pipe-a-overlay-size-64:
- shard-skl: [DMESG-WARN][61] ([i915#1982]) -> [PASS][62] +3 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-skl10/igt@kms_plane_cursor@pipe-a-overlay-size-64.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-skl2/igt@kms_plane_cursor@pipe-a-overlay-size-64.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [SKIP][63] ([fdo#109441]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-iclb3/igt@kms_psr@psr2_sprite_mmap_gtt.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@perf@polling:
- shard-skl: [FAIL][65] ([i915#1542]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-skl8/igt@perf@polling.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-skl3/igt@perf@polling.html
* igt@sysfs_heartbeat_interval@mixed@rcs0:
- shard-skl: [FAIL][67] ([i915#1731]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-skl2/igt@sysfs_heartbeat_interval@mixed@rcs0.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-skl4/igt@sysfs_heartbeat_interval@mixed@rcs0.html
#### Warnings ####
* igt@runner@aborted:
- shard-iclb: ([FAIL][69], [FAIL][70]) ([i915#1814] / [i915#2439]) -> ([FAIL][71], [FAIL][72]) ([i915#1814] / [i915#2439] / [i915#483])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-iclb6/igt@runner@aborted.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-iclb3/igt@runner@aborted.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-iclb8/igt@runner@aborted.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-iclb7/igt@runner@aborted.html
- shard-glk: ([FAIL][73], [FAIL][74], [FAIL][75]) ([i915#1611] / [i915#1814] / [i915#2439] / [k.org#202321]) -> ([FAIL][76], [FAIL][77]) ([i915#1814] / [i915#2439] / [k.org#202321])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-glk9/igt@runner@aborted.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-glk5/igt@runner@aborted.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9263/shard-glk8/igt@runner@aborted.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-glk6/igt@runner@aborted.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/shard-glk9/igt@runner@aborted.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1226]: https://gitlab.freedesktop.org/drm/intel/issues/1226
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1611]: https://gitlab.freedesktop.org/drm/intel/issues/1611
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1731]: https://gitlab.freedesktop.org/drm/intel/issues/1731
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#182]: https://gitlab.freedesktop.org/drm/intel/issues/182
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2244]: https://gitlab.freedesktop.org/drm/intel/issues/2244
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2370]: https://gitlab.freedesktop.org/drm/intel/issues/2370
[i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
[i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#483]: https://gitlab.freedesktop.org/drm/intel/issues/483
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_9263 -> Patchwork_18850
CI-20190529: 20190529
CI_DRM_9263: d024f57bbf34cd9dedaff4d026a7ed8f58325bad @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5832: 9c583f7e2a6638b5ff6a3682fea548a1313512e7 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18850: ca731d18e828dccce4340125ea27f22e0f6d6e84 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18850/index.html
[-- Attachment #1.2: Type: text/html, Size: 21109 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2020-11-04 15:37 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-11-04 12:20 [Intel-gfx] [RFC 1/2] drm/i915: Improve record of hung engines in error state Tvrtko Ursulin
2020-11-04 12:20 ` [Intel-gfx] [RFC 2/2] drm/i915: Use user engine names in error state ecode Tvrtko Ursulin
2020-11-04 12:33 ` Chris Wilson
2020-11-04 13:06 ` Tvrtko Ursulin
2020-11-04 13:21 ` Chris Wilson
2020-11-04 12:30 ` [Intel-gfx] [RFC 1/2] drm/i915: Improve record of hung engines in error state Chris Wilson
2020-11-04 13:03 ` Tvrtko Ursulin
2020-11-04 13:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [RFC,1/2] " Patchwork
2020-11-04 15:37 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2020-11-04 13:47 [Intel-gfx] [RFC 1/2] " Tvrtko Ursulin
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox